ICS9250BF-27T

DATASHEET Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Pin Configuration *FS2//REF0 VDD X1 X2 GND GND 3V66-0 3V66-1 3V66-2 VDD VDD PCICLK_F PCICLK0 GND PCICLK1 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 VDD VDD GND GND 48MHz_0 48MHz_1 VDD FS0 810/810E and 815 type chipset. Output Features: • • • • • 3 CPU (2.5V) (up to 133MHz achievable through I2C) 9 SDRAM (3.3V) (up to 133MHz achievable through I2C) 7 PCI (3.3 V) @33.3MHz 2 IOAPIC (2.5V) @ 33.3 MHz 3 Hublink clocks (3.3 V) @ 66.6 MHz 2 (3.3V) @ 48 MHz (Non spread spectrum) 1 REF (3.3V) @ 14.318 MHz Features: • • • • • Supports spread spectrum modulation, 0 to -0.5% down spread. I2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal Alternate frequency selections available through I2C control. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS9250-27 Recommended Application: • • ICS9250-27 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND IOAPIC0 IOAPIC1 VDDL CPUCLK0 VDDL0 CPUCLK1 CPUCLK2 GNDL GND SDRAM0 SDRAM1 VDD SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD SDRAM6 SDRAM7 GND SDRAM_F VDD PD# SCLK SDATA FS1 56-Pin 300mil SSOP * This input has a 50KΩ pull-down to GND. Block Diagram Functionality X1 X2 XTAL OSC REF0 PLL1 Spread Spectrum /2 /3 VDDL FS2 FS1 FS0 X X 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 CPU66/100/133 (2:0) 3 FS (2:0) PD# 3 Control Logic 8 3V66 (2:0) SDRAM (7:0) SDRAM_F SDATA /2 SCLK 6 Config Reg PCICLK (5:0) Function Tristate Test Active CPU = 66MHz SDRAM = 100MHz Active CPU = 100MHz SDRAM = 100MHz Active CPU = 133MHz SDRAM = 133MHz Active CPU = 133MHz SDRAM = 100MHz PCICLK_F /2 2 PLL2 2 IOAPIC (1:0) VDDL Power Groups AVDD = Pin 22 Analog power for PLL AGND = Pin 23 Analog ground VDD48 = Pin 27 Analog power for 48MHz PLL GND = Pin 24 Analog ground for 48MHz PLL 48MHz (1:0) IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 1 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM General Description The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS925027 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Pin Description PIN NUMBER 1 PIN NAME FS2 TYPE IN 3 X1 IN 4 X2 OUT 3.3V, 14.318MHz reference clock output. Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) PWR Ground pins for 3.3V supply 3V66 (2:0) OUT 3.3V Fixed 66MHz clock outputs for HUB VDD PWR 3 . 3 V p ow e r s u p p l y PCICLK_F OUT Free r unning 3.3V PCI clock output PCICLK (5:0) OUT 3.3V PCI clock outputs 25 48MHz_0 OUT 3.3V Fixed 48MHz clock outputs for USB 26 48MHz_1 OUT 3.3V fixed 48MHz clock output. Stronger output for graphics/video interface (minimum 1V/ns edge rate) Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 1 REF0 5, 6, 14, 17, 23, 24, 35, 41, 47, GND 48, 56 9, 8, 7 2, 10, 11, 21, 22, 27, 33, 38, 44 12 20, 19, 18, 16, 15, 13 OUT DESCRIPTION Function Select pin. Determines CPU frequency, all output functionality 29, 28 FS (1:0) IN 30 SDATA I/O Data pin for I2C circuitr y 5V tolerant 31 SCLK IN Clock pin of I2C circuitr y 5V tolerant 32 36, 37, 39, 40, 42, 43, 45, 46 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. 3.3V output r unning 100MHz. All SDRAM outputs can be tur ned off t h r o u g h I 2C SDRAM (7:0) OUT SDRAM_F OUT 3 . 3 V f r e e r u n n i n g 1 0 0 M H z S D R A M , c a n n o t b e t u r n e d o f f t h r o u g h I 2C CPUCLK (2:0) OUT 2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending o n F S p i n s. 51, 53 VDDL PWR 2.5V power suypply for CPU & IOAPIC 54, 55 IOAPIC (1:0) OUT 2.5V clock outputs r unning at 33.3MHz. 34 49, 50, 52 IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 2 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency