ICS93722CFLF

DATASHEET 93722 Low Cost DDR Phase Lock Loop Zero Delay Buffer Pin Configuration DDR Zero Delay Clock Buffer CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLK_INT N/C VDDA GND VDD CLKT2 CLKC2 Output Features • • • • • Low skew, low jitter PLL clock driver I2C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs 3.3V tolerant CLK_INT input Key Specifications • • • • • • • PEAK - PEAK jitter (66MHz): 100MHz):