ICS950410AFLFT

ICS950410 Preliminary Product Preview AMD - K8™ System Clock Chip ~*FS0/REF0 VDDHTT Output Features: X1 • 3 - Differential pair push-pull CPU clocks @ X2 3.3V GND • 9 - PCICLK (Including 1 free running) @ 3.3V *ModeA/HTTCLK0 • 3 - Selectable PCICLK/HTTCLK @ 3.3V *ModeB/PCICLK8/HTTCLK1 • 1 - HTTCLK @ 3.3V PCICLK9/HTTCLK2 • 1 - 48MHz @ 3.3V fixed. VDDPCI GND • 1 - 24/48MHz @ 3.3V PCICLK11/HTTCLK3 • 2 - REF @ 3.3V, 14.318MHz. *FS2/PCICLK10 Features: PCICLK0 • Programmable output frequency. PCICLK1 • Programmable output divider ratios. GND • Programmable output rise/fall time. VDDPCI • Programmable output skew. PCICLK2 PCICLK3 • Programmable spread percentage for EMI control. VDDPCI GND • Watchdog timer technology and RESET# output to reset system if system malfunctions. Programmable watch dog safe frequency. Support I2C Index read/write and block read/ write operations. Uses external 14.318MHz crystal. Supports Hyper Transport Technology (HTTCLK). • • • • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ICS950410 Pin Configuration Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset 2X PCICLK4 21 PCICLK5 22 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 AVDD48 27 24_48MHz/Sel24_48#* 2X 2X PCICLK6 23 PCICLK7 24 26 SDATA 25 SCLK 2X 48-SSOP * Internal Pull-Up Resistor 2X This Output has 2X Default Drive and can be programmaed lower via IIC ~ This Output has 1.5x drive Functionality FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0888A—04/22/05 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50 REF1/FS1* GND VDDREF Reset# VDDA GND CPUCLK8T0 CPUCLK8C0 VDDCPU CPUCLK8T1 CPUCLK8C1 GND VDDCPU CPUCLK8T2 CPUCLK8C2 GND Turbo# PD#* 48MHz/FS3** GND ICS950410 Preliminary Product Preview Pin Descriptions PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ~*FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 VDDPCI GND PCICLK11/HTTCLK3 *FS2/PCICLK10 PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 VDDPCI GND 2XPCICLK4 2XPCICLK5 PIN TYPE I/O PWR IN OUT PWR I/O I/O OUT PWR PWR OUT I/O OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT 23 2XPCICLK6 OUT 24 2XPCICLK7 OUT 25 26 SCLK SDATA IN I/O 27 24_48MHz/Sel24_48#* I/O 28 29 30 AVDD48 GND 48MHz/FS3** 31 PD#* 32 Turbo# 33 34 35 36 37 38 39 40 41 42 43 44 GND CPUCLK8C2 CPUCLK8T2 VDDCPU GND CPUCLK8C1 CPUCLK8T1 VDDCPU CPUCLK8C0 CPUCLK8T0 GND VDDA PWR OUT OUT PWR PWR OUT OUT PWR OUT OUT PWR PWR 45 Reset# OUT 46 47 48 VDDREF GND REF1/FS1* PWR PWR I/O PWR PWR I/O IN IN DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Supply for HTT clocks, nominal 3.3V. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Mode selection latch input pin / Hyper Transport output. Mode selection latch input pin / PCI clock output / Hyper Transport output. PCI clock output / Hyper Transport output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output / Hyper Transport output. Frequency select latch input pin / 3.3V PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V Ground pin. Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Real time input pin to change frequency to a pre-programmed under or over clock entries located in IIC Rom table. Ground pin. Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Ground pin. Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin. 3.3V power for the PLL core. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. Ref, XTAL power supply, nominal 3.3V Ground pin. 14.318 MHz reference clock / Frequency select latch input pin. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength 0888A—04/22/05 2 ICS950410 Preliminary Product Preview General Description The ICS950410 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS950410 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC REF (1:0) PLL1 Spread Spectrum CPU DIVDER CPUCLKC (2:0) CPUCLKT (2:0) PD# SDATA SCLK PCI DIVDER Control Logic FS (3:0) MODE (A,B) SEL24_48# PCICLK (7:0, 10) Config. PCICLK(11,9,8)/HTTCLK (3:1) HTT DIVDER Reg. HTTCLK0 Turbo# Power Groups Pin Number Description VDD GND 2 5 Xtal, POR PCICLK, HTTCLK O/p 9 10 16,19 15,20 PCICLK Outputs 29 27,30,33 48 MHz, Fix Analog 35,38 34,39 CPU Outputs 43 42 Analog, CPU PLL, MCLK 46 47 REF, Digital Core 0888A—04/22/05 3 ICS950410 Preliminary Product Preview Table1: Frequency Selection Table Bit4 FS4 0 0 0 0 0 0 0 Bit3 FS3 0 0 0 0 0 0 0 Bit2 FS2 0 0 0 0 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 Bit0 FS0 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 0 0 1 1 0 1 0 0 0 1 0 0 0 150.00 60.00 30.00 1 180.00 60.00 0 1 0 30.00 1 0 210.00 70.00 0 1 35.00 0 1 1 240.00 60.00 30.00 0 0 1 1 0 0 270.00 67.50 33.75 1 1 0 1 233.33 66.67 33.33 0 1 1 1 0 266.67 66.67 33.33 0 1 1 1 1 300.00 75.00 37.50 1 0 0 0 0 100.00 66.67 33.33 1 0 0 0 1 133.33 66.67 33.33 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 166.66 200.00 103.00 137.33 171.66 206.00 154.49 185.38 216.31 247.20 278.10 240.34 274.68 308.97 66.66 66.67 68.67 68.66 68.66 68.67 61.79 61.79 72.10 61.80 69.53 68.67 68.67 77.24 33.33 33.33 34.33 34.33 34.33 34.33 30.90 30.90 36.05 30.90 34.76 34.33 34.34 38.62 Mode Functionality Tables ModeA 0 ModeB 0 Pin7 HTTCLK1 Pin8 HTTCLK2 Pin11 PCICLK11 0 1 HTTCLK1 HTTCLK2 HTTCLK3 1 0 PCICLK8 PCICLK9 PCICLK11 1 1 HTTCLK1 PCICLK9 PCICLK11 0888A—04/22/05 4 ICS950410 Preliminary Product Preview General I2C serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0888A—04/22/05 5 Not acknowledge stoP bit ICS950410 Preliminary Product Preview 2 I C Table: Frequency Select Register Byte 0 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type 0 1 PWD SS_EN SEL24_48MHz FS Source Select FS4 FS3 FS2 FS1 FS0 Spread Enable Output Select FS Source Select Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 RW RW RW RW RW RW RW RW OFF 48MHz latch ON 24MHz I2C 1 Latch 0 0 Latch Latch Latch Latch Name Control Function Type 0 1 PWD CPUCLK8T/C2 HTTCLK0 PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 PCICLK11/HTTCLK3 PCICLK10 PCICLK0 PCICLK1 Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 24_48MHz 48MHz Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD CPUCLK8T/C_1 CPUCLK8T/C_0 Reserved REF0/REF1 PCI_Str1 PCI_Str0 PCI_Str1 PCI_Str0 Output Control Output Control Reserved Output Control PCI9,8 Strength Control only PCI11 Strength Control only RW RW RW RW RW RW RW RW Disable Disable Disable 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive Enable Enable Enable 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 1 1 1 1 0 1 0 1 See Table1: Frequency Selection Table 2 I C Table: Output Control Register Byte 1 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 1 6 7 8 11 12 13 14 7 6 5 4 3 2 1 0 2 I C Table: Output Control Register Byte 2 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 17 18 21 22 23 24 28 31 7 6 5 4 3 2 1 0 2 I C Table: Output Control Register Byte 3 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # 37,36 41,40 45,48 - 0888A—04/22/05 6 ICS950410 Preliminary Product Preview 2 I C Table: Output Control Register Byte 4 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type 0 1 PWD PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0 All other PCICLK Strength Control PCICLK (7:6) Strength Control PCICLK (5) Strength Control PCICLK (4) Strength Control RW RW RW RW RW RW RW RW 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 0 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved X X X X X X X X Name Control Function Type 0 1 PWD Byte Count Programming b(7:0) RW RW RW RW RW RW RW RW Control Function Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 1 2 I C Table: Reserved Register Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 2 I C Table: Byte Count Register Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. 0 0 0 0 0 1 1 0 2 I C Table: Byte Count and Vendor ID Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name REV_ID3 REV_ID2 REV_ID1 REV_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Revision ID Vendor ID 0888A—04/22/05 7 ICS950410 Preliminary Product Preview 2 I C Table: Skew Control Register Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit Pin # PCI/HTTSkw3 PCI/HTTSkw2 PCI/HTTSkw1 PCI/HTTSkw0 PCISkw3 PCISkw2 PCISkw1 PCISkw0 - 7 6 5 4 3 2 1 0 Name Control Function CPU-PCI/HTT 7 Step Skew Control (ps) CPU-PCI 7 Step Skew Control (ps) Type RW RW RW RW RW RW RW RW 0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 1 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A PWD 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900 1 1 0 0 1 1 0 0 2 I C Table: WD Time Control & Async Frequency Selection Register Byte 9 Pin # Name Bit 7 - ASEL Bit 6 - AEN Bit 5 Bit 4 - REF1 Strength Reserved Bit 3 - WDTCtrl Bit 2 Bit 1 Bit 0 - WD2 WD1 WD0 Control Function Async Frequency Select AGP/PCI/ Freq Source Select REF1 strength control Reserved Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type 0 1 PWD RW 66MHz 75.4MHz 0 RW FIX PLL CPU PLL 1 RW RW 1x - 2x - 1 1 RW 290ms Base 1160ms Base 0 RW RW RW These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. 1 1 1 2 I C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Bit 7 - M/NEN Bit Bit Bit Bit Bit Bit Bit - WDEN WDStatus WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 6 5 4 3 2 1 0 Control Function M/N Programming Enable Watchdog Enable WD Alarm Status Watch Dog Safe Freq Programming bits Type 0 1 PWD RW Disable Enable 0 RW R RW RW RW RW RW Disable Normal Enable Alarm 0 0 0 0 0 0 0 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). 2 I C Table: VCO Frequency Control Register Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 N Divider Prog bit 8 N Divider Prog bit 9 Type 0 1 RW The decimal representation of N Divider in Byte 11 and 12 RW RW The decimal representation of M and N RW Divier in Byte 11 and 12 will configure the M Divider Programming RW VCO frequency. Default at power up = bits (5:0) latch-in or Byte 0 Rom table. RW RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW 0888A—04/22/05 8 PWD X X X X X X X X ICS950410 Preliminary Product Preview 2 I C Table: VCO Frequency Control Register Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function Type 0 1 RW RW The decimal representation of M and N RW Divier in Byte 11 and 12 will configure the N Divider Programming RW VCO frequency. Default at power up = bit (7:0) latch-in or Byte 0 Rom table. RW RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW RW PWD X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type Spread Spectrum Programming b(7:0) RW RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 14 Name Control Function Type 0 1 PWD Bit 7 Bit 6 - Reserved SSP14 Reserved R RW - - 0 X Bit Bit Bit Bit Bit Bit - SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 5 4 3 2 1 0 Pin # Spread Spectrum Programming b(14:8) 0888A—04/22/05 9 RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. X X X X X X ICS950410 Preliminary Product Preview Absolute Maximum Rating 1 PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature VDD_A - VDD_In - Ts Ambient Operating Temp MIN TYP MAX UNITS Notes VDD + 0.5V V 1 GND - 0.5 VDD + 0.5V V 1 - -65 150 ° C 1 Tambient - 0 70 °C 1 Case Temperature Tcase - 115 °C 1 Input ESD protection HBM ESD prot - V 1 2000 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS Notes Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 -5 uA 1 -200 uA 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Operating Current IDD3.3OP VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 IDD3.3OP Full Active, CL = Full load; 350 mA 1 all outputs driven 400 mA 1 all diff pairs driven 70 mA 1 Powerdown Current IDD3.3PD Input Frequency Fi Pin Inductance Lpin CIN Input Capacitance COUT CINX X1 & X2 pins all differential pairs tri-stated mA 1 MHz 2 7 nH 1 Logic Inputs 5 pF 1 Output pin capacitance 6 pF 1 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 14.31818 Tfall_Pd# Trise_Pd# PD# rise time of TSTAB Modulation Frequency Tdrive_PD# SMBus Voltage 12 VDD = 3.3 V From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of Clk Stabilization TYP 30 2.7 VDD @ IPULLUP Low-level Output Voltage VOL Current sinking at IPULLUP VOL = 0.4 V (Max VIL - 0.15) to SCLK/SDATA TRI2C (Min VIH + 0.15) Clock/Data Rise Time (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 5 ns 1 5 ns 1 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 4 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 0888A—04/22/05 10 ICS950410 Preliminary Product Preview Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS* MIN Output Impedance RDSP VO = VDD*(0.5) 12 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 TYP MAX UNITS NOTES 55 Ω 1 V 1 V 1 0.55 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V mA 1 mA 1 mA 1 38 mA 1 4 V/ns 1 2 ns 1 -33 30 VOL @ MAX = 0.4 V Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 MAX 100 UNITS ppm NOTES *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 3 Spread Spectrum is off Electrical Characteristics - 48MHz/USB48MHz/24_48MHz PARAMETER Long Accuracy SYMBOL ppm CONDITIONS* see Tperiod min-max values MIN -100 Clock period Tperiod 48.00MHz output nominal 20.8313 20.8354 ns 2 Output Impedance RDSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.55 V 1 Output High Current IOH mA 1 mA 1 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V TYP -33 30 1,2 mA 1 38 mA 1 Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Edge Rate tslewr/f_USB USB48 Rising/Falling edge rate 1 2 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 VOL @ MAX = 0.4 V Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. 0888A—04/22/05 11 ICS950410 Preliminary Product Preview Electrical Characteristics - CPUCLKK8T/C K8 3.3V Push Pull Differential Pair PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS NOTES Rising Edge Rate At CPU's test load. 0 V +/- 400 mV (diffential measurment) 2 10 V/ns 1 Falling Edge Rate δV/δt δV/δt TYP 2 10 V/ns 1 At CPU's test load. (singleended measurement) Differential Voltage VDIFF 0.4 2.3 V 1 Change in VDIFF_DC Magnitude ∆ VDIFF -150 150 mV 1 Common Mode Voltage Change in Common Mode Voltage VCM 1.05 1.45 V 1 ∆ VCM -200 200 mV 1 Jitter, Cycle to cycle tjcyc-cyc 0 200 ps 1 Jitter, Accumulated tja Measurement from differential wavefrom Duty Cycle dt3 Measurement from differential wavefrom Output Impedance RON Average value during switching transition. Used for determining series termination value. -1000 1000 45 55 % 1 15 55 Ω 1 250 ps 1 MAX UNITS NOTES 55 Ω 1 V 1 V 1 Measurement from differential wavefrom *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% Group Skew tskew 1,2,3 1 Guaranteed by design and characterization, not 100% tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz 3 Spread Spectrum is off Electrical Characteristics - HTTCLK PARAMETER SYMBOL CONDITIONS* MIN Output Impedance ZO VO = VX 12 Output High Voltage VOH1 IOH = -1 mA 2.4 Output Low Voltage VOL1 IOL = 1 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 Edge Rate tslewr/f 1 Rise Time tr VOL = 0.8 V Rise/Fall edge rate between 20% 60% VOL = 0.4 V, VOH = 2.4 V Fall Time tf VOH = 2.4 V, VOL = 0.4 V Duty Cycle dt1 VT = 50% Group Skew tskew Jitter, Cycle-to-cycle tjcyc-cyc2B TYP 0.4 -15 mA 1 mA 1 4 V/ns 1 0.5 2 ns 1 0.5 2 ns 1 45 55 % 1 VT = 1.5 V 150 ps 1 VT = 1.5 V 250 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1 Guaranteed by design and characterization, not 100% tested in production. 0888A—04/22/05 12 10 ICS950410 Preliminary Product Preview Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8270 69.8550 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA VOH @MIN = 1.0 V, TYP V 1 0.4 V 1 -29 -23 mA 1 29 27 mA 1 Output High Current IOH Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 1 Skew tsk1 VT = 1.5 V Duty Cycle dt1 VT = 1.5 V Jitter tjcyc-cyc VT = 1.5 V VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 45 2 ns 500 ps 1 55 % 1 1000 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0888A—04/22/05 13 ICS950410 Preliminary Product Preview Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS950410 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0888A—04/22/05 14 ICS950410 Preliminary Product Preview c N L E1 INDEX AREA SYMBOL E A A1 b c D E E1 e h L N α 1 2 a h x 45° D A A1 -Ce SEATING PLANE N .10 (.004) C 48 b In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS950410yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0888A—04/22/05 15 MAX .630 ICS950410 Preliminary Product Preview Revision History Rev. A Issue Date Description 4/22/2005 Page # 1. Updated Byte 11/12 M/N programming description 2. Updated Ordering Information from "Lead Free" to Annealed Lead Free". 3. Preliminary Release. 0888A—04/22/05 16 8-9,15 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. 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