ICS951411BGLF

ICS951411 Integrated Circuit Systems, Inc. System Clock Chip for ATI RS400 P4TM-based Systems Recommended Application: ATI RS400 systems using Intel P4TM processors Features/Benefits: • 2- Programmable Clock Request pins for SRC clocks • Supports CK410 or CK409 frequency table mapping • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Output Features: • 6 - Pairs of SRC/PCI-Express clocks • 2 - Pairs of ATIG (SRC/PCI Express*) clocks • 3 - Pairs of Intel P4 clocks • 3 - 14.318 MHz REF clocks • 1 - 48MHz USB clock • 1 - 33 MHz PCI clock seed Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter 2.0V to enter test mode. 2. Cycle power to disable test mode 0891E—03/07/05 10 HW TEST_SEL/REF2 HW PIN 2.0V OUTPUT NORMAL HI-Z PWD 0 0 0 0 1 0 0 1 ICS951411 Integrated Circuit Systems, Inc. Absolute Max Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V ° C °C °C 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage Input Low Voltage Input High Current VIH VIL IIH 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 2 VSS - 0.3 -5 VIH_FS 3.3 V +/-5% 0.7 VSS - 0.3 TYP MAX VDD + 0.3 UNITS Notes V V uA 1 1 1 -5 uA 1 -200 uA 1 VDD + 0.3 V 1 0.35 V 1 400 70 12 7 5 6 5 mA mA mA MHz nH pF pF pF 1 1 1 3 1 1 1 1 1.8 ms 1,2 33 kHz 1 300 us 1 Tfall_Pd# 5 Trise_Pd# 5 VDD 2.7 5.5 SMBus Voltage @ IPULLUP VOL 0.4 Low-level Output Voltage Current sinking at IPULLUP 4 VOL = 0.4 V (Max VIL - 0.15) to SCLK/SDATA TRI2C 1000 (Min VIH + 0.15) Clock/Data Rise Time (Min VIH + 0.15) to SCLK/SDATA TFI2C 300 (Max VIL - 0.15) Clock/Data Fall Time 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. ns ns V V 1 2 1 1 mA 1 ns 1 ns 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current VIL_FS 3.3 V +/-5% IDD3.3OP Powerdown Current IDD3.3PD Input Frequency Pin Inductance Fi Lpin CIN COUT CINX all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Input Capacitance Clk Stabilization Modulation Frequency Tdrive_PD# TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of 0891E—03/07/05 11 0.8 5 14.31818 30 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES Ω 1 850 1,3 mV -150 150 1150 -300 250 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 1,3 550 mV 1 1 1 140 mV 1 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 700 700 125 125 mV Measurement from differential 45 55 % wavefrom CPU(1:0), VT = 50% tsk3 100 ps Skew CPU(1:0) to CPU2_ITP, tsk4 150 ps Skew VT = 50% Measurement from differential tjcyc-cyc 125 ps Jitter, Cycle to cycle wavefrom (CPU2_ITP) Measurement from differential tjcyc-cyc 85 ps Jitter, Cycle to cycle wavefrom, (CPU(1:0)) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 0891E—03/07/05 12 1 1 1 1 1 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Zo VO = Vx 3000 VHigh VLow Vovs Vuds Statistical measurement on single ended signal Measurement on single ended signal using 660 -150 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time tr Fall Time tf Rise Time Variation Fall Time Variation d-tr d-tf TYP MAX Ω 850 150 1150 -300 250 Variation of crossing over all edges see Tperiod min-max -300 values 100.00MHz nominal 9.9970 9.9970 100.00MHz spread 100.00MHz 9.8720 nominal/spread VOL = 0.175V, 175 VOH = 0.525V VOH = 0.525V 175 VOL = 0.175V UNITS Notes mV mV 1 1,3 1,3 1 1 350 550 mV 1 12 140 mV 1 300 ppm 1,2 10.0030 10.0533 ns ns 2 2 ns 1,2 700 ps 1 700 ps 1 125 125 ps ps 1 1 30 30 Measurement from 45 55 % 1 differential wavefrom VT = 50% tsk3 250 ps 1 Skew Measurement from tjcyc-cyc Jitter, Cycle to cycle 125 ps 1 differential wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 0891E—03/07/05 13 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm Clock period Tperiod Output High Voltage Output Low Voltage VOH VOL see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V -300 29.9910 29.9910 2.4 Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 1 1 0.5 0.5 45 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter 1 2 tr1 tf1 dt1 tjcyc-cyc TYP MAX 300 30.0090 30.1598 0.55 -33 -33 30 38 4 4 2 2 55 250 UNITS Notes ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps 1,2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Electrical Characteristics - 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL see Tperiod min-max values 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH@ MAX = 3.135 V VOL @MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V -100 20.8313 2.4 Output High Current Output Low Current IOH IOL Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle tr1 tf1 dt1 tjcyc-cyc 1 TYP MAX 100 20.8354 38 2 2 ppm ns V V mA mA mA mA V/ns V/ns 1,2 2 1 1 1 1 1 1 1 1 2 2 55 175 ns ns % ps 1 1 1 1 0.55 -33 -33 30 1 1 1 1 45 UNITS Notes Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 2 0891E—03/07/05 14 ICS951411 Integrated Circuit Systems, Inc. Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL Output High Current IOH Output Low Current IOL Rise Time Fall Time Skew Duty Cycle Jitter tr1 tf1 tsk1 dt1 tjcyc-cyc CONDITIONS MIN see Tperiod min-max values -300 14.318MHz output nominal 69.8270 IOH = -1 mA 2.4 IOL = 1 mA VOH @MIN = 1.0 V, -29 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL 29 @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V VT = 1.5 V 45 VT = 1.5 V 1 TYP MAX 300 69.8550 UNITS Notes 0.4 ppm ns V V 1 1 1 1 -23 mA 1 27 mA 1 2 2 500 55 1000 ns ns ps % ps 1 1,2 2 1,2 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0891E—03/07/05 15 ICS951411 Integrated Circuit Systems, Inc. SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non -coupled 50 ohm trace. 0.5 max L2 length, Route as non -coupled 50 ohm trace. 0.2 max L3 length, Route as non -coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coup led stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Rout e as coupled stripline 100 ohm differential trace. L1 Unit inch inch inch ohm ohm Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Dimension or Value 2 min to 16 max Unit inch 2 1.8 min to 14.4 max inch 2 Dimension or Value 0.25 to 14 max Unit inch 3 0.225 min to 12.6 max inch 3 Figure L2 L4 Rs L1’ L4’ L2’ Rs Fig.1 Figure Rt HSCL Output Buffer Rt L3’ L1 PCI Ex REF_CLK Test Load L3 L2 L4 Rs L1’ Fig.2 L4’ L2’ Rs Rt HSCL Output Buffer L3’ L1 Rt PCI Ex Board Down Device REF_CLK Input L3 L2 L4 Rs L4’ L1’ L2’ Rs Fig.3 Rt HSCL Output Buffer L3’ 0891E—03/07/05 16 Rt L3 PCI Ex Add In Board REF_CLK Input ICS951411 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins The I/O pins designated by (input/output) on the ICS951416 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0891E—03/07/05 17 ICS951411 Integrated Circuit Systems, Inc. c N 56-Lead, 300 mil Body, 25 mil, SSOP L E1 INDEX AREA E 1 2 α h x 45° D A A1 A A1 b c D E E1 e h L N a In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS -C- e SYMBOL SEATING PLANE b .10 (.004) C N 56 D mm. MIN 18.31 D (inch) MAX 18.55 MIN .720 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS951411yFLFT Example: ICS XXXX y F LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0891E—03/07/05 18 MAX .730 ICS951411 Integrated Circuit Systems, Inc. c N L E1 INDEX AREA E 1 2 a D A A2 A1 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 -Ce b SEATING PLANE VARIATIONS N aaa C 56 D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 Reference Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information ICS951411yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0891E—03/07/05 19 MAX .555