ICS951412B
System Clock Chip for ATI RS480 K8-based Systems
Recommended Application:
ATI RS480 systems using AMD K8 processors
Pin Configuration
Features:
•
2 - Programmable Clock Request pins for SRC
clocks
•
Spread Spectrum for EMI reduction
•
Outputs may be disabled via SMBus
•
External crystal load capacitors for maximum
frequency accuracy
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ICS951412
X1
X2
VDD48
USB_48MHz
GND
NC
SCLK
SDATA
**FS2
**CLKREQA#
**CLKREQB#
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
Output Features:
•
3 - 14.318 MHz REF clocks
•
1 - USB_48MHz USB clock
•
1 - HyperTransport 66 MHz clock seed
•
1 - PCI 33 MHz clock seed
•
2 - Pairs of AMD K8 clocks
•
6 - Pairs of SRC/PCI Express* clocks
•
2 - Pairs of ATIG (SRC/PCI Express) clocks
VDDREF
GND
**FS0/REF0
**FS1/REF1
REF2
VDDPCI
PCICLK0
GNDPCI
VDDHTT
HTTCLK0
GNDHTT
CPUCLK8T0
CPUCLK8C0
VDDCPU
GNDCPU
CPUCLK8T1
CPUCLK8C1
VDDA
GNDA
IREF
GNDSRC
VDDSRC
SRCCLKT0
SRCCLKC0
VDDATI
GNDATI
ATIGCLKT0
ATIGCLKC0
Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor
56 Pin SSOP/TSSOP
Functionality
Power Groups
Pin Number
VDD
GND
56
55
Description
FS2
FS1
FS0
Xtal, REF
0
0
0
0
1
CPU
MHz
Hi-Z
HTT
MHz
Hi-Z
PCI
MHz
Hi-Z
51
49
PCICLK output
0
X
X/3
X/6
48
46
HTTCLK output
0
1
0
180.00
60.00
30.00
43
14, 21,
32,35
39
42
15, 20,
26,31,36
38
CPU Outputs
0
1
1
220.00
73.12
36.56
1
0
0
100.00
66.66
33.33
SRC outputs
1
0
1
133.33
66.66
33.33
Analog, CPU PLL
1
1
1
200.00
66.66
33.33
3
5
USB_48MHz output
1232A—06/12/06
*Other names and brands may be claimed as the property of others.
ICS951412B
Pin Descriptions
PIN
#
PIN NAME
PIN
TYPE
1
2
3
4
5
6
7
8
9
X1
X2
VDD48
USB_48MHz
GND
NC
SCLK
SDATA
**FS2
IN
OUT
PWR
OUT
PWR
N/A
IN
I/O
IN
10
**CLKREQA#
IN
11
**CLKREQB#
IN
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
DESCRIPTION
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power pin for the 48MHz output.3.3V
48.00MHz USB clock
Ground pin.
No Connection.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Frequency select pin.
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Ground pin for the SRC outputs
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complementary clock of differential SRC clock pair.
1232A—06/12/06
2
ICS951412B
Pin Descriptions (Continued)
PIN
#
29
30
31
32
33
34
35
36
ATIGCLKC0
ATIGCLKT0
GNDATI
VDDATI
SRCCLKC0
SRCCLKT0
VDDSRC
GNDSRC
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
Complementary clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Ground for ATI Gclocks, nominal 3.3V
Power supply ATI Gclocks, nominal 3.3V
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
37
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
GNDA
VDDA
CPUCLK8C1
CPUCLK8T1
GNDCPU
VDDCPU
CPUCLK8C0
CPUCLK8T0
GNDHTT
HTTCLK0
VDDHTT
GNDPCI
PCICLK0
VDDPCI
REF2
**FS1/REF1
**FS0/REF0
GND
VDDREF
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
OUT
PWR
PWR
OUT
PWR
OUT
I/O
I/O
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin for the CPU outputs
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin for the HTT outputs
3.3V Hyper Transport output
Supply for HTT clocks, nominal 3.3V.
Ground pin for the PCI outputs
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
PIN NAME
Type
Pin Description
1232A—06/12/06
3
ICS951412B
General Description
The ICS951412B is a main clock synthesizer chip that provides all clocks required for ATI RS480-based systems.
An SMBus interface allows full control of the device.
Block Diagram
REF(2:0)
X1
X2
XTAL
OSC.
USB_48MHz
FIXED PLL
DIVIDER
PCICLK0
HTTCLK0
SRCCLK(7:3,0)
MAIN PLL
DIVIDERS
ATIGCLK(1:0)
CPUCLK8(1:0)
FS(2:0)
CLKREQA#
CLKREQB#
SEL75#/100
SDATA
SCLK
CONTROL
LOGIC
IREF
Skew Characteristics
Parameter
Description
Tsk_CPU_CPU
Tsk_CPU_PCI
Tsk_PCI_PCI
Tsk_PCI33-HT66
time independent
skew
not dependent on
V, T changes
Tsk_CPU_HT66
Tsk_CPU_HT66
Tsk_CPU_CPU
Tsk_CPU_PCI
Tsk_PCI_PCI
Tsk_PCI33-HT66
Tsk_CPU_HT66
Tsk_CPU_HT66
time variant skew
varies over
V, T changes
Test Conditons
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
Skew
Window
250
Unit
ps
2000
ps
500
ps
500
ps
2000
ps
500
200
ps
ps
200
ps
200
ps
200
ps
200
ps
200
ps
1232A—06/12/06
4
ICS951412B
General SMBus serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
1232A—06/12/06
5
Not acknowledge
stoP bit
ICS951412B
Table1: CPU Frequency Selection Table
CPU
CPU FS3 CPU CPU CPU CPU
SS_EN
(B0:b3) FS2 FS1 FS0 (MHz)
(B0:b4)
0
0
0
0
0
Hi-Z
0
0
0
0
1
X/6
0
0
0
1
0
180.00
0
0
0
1
1
220.00
0
0
1
0
0
100.00
0
0
1
0
1
133.33
0
0
1
1
0
166.67
0
0
1
1
1
200.00
0
1
0
0
0
186.00
0
1
0
0
1
214.00
0
1
0
1
0
190.00
0
1
0
1
1
210.00
0
1
1
0
0
102.00
0
1
1
0
1
136.00
0
1
1
1
0
170.00
0
1
1
1
1
204.00
1
0
0
0
0
169.58
1
0
0
0
1
229.43
1
0
0
1
0
179.55
1
0
0
1
1
219.45
1
0
1
0
0
99.75
1
0
1
0
1
133.00
1
0
1
1
0
166.25
1
0
1
1
1
199.50
1
1
0
0
0
185.54
1
1
0
0
1
106.73
1
1
0
1
0
189.53
1
1
0
1
1
209.48
1
1
1
0
0
101.75
1
1
1
0
1
135.66
1
1
1
1
0
169.58
1
1
1
1
1
203.49
HTT66 PCI33
(MHz) (MHz)
Hi-Z
X/12
60.00
73.33
66.67
66.67
66.67
66.67
62.00
71.33
63.33
70.00
68.00
68.00
68.00
68.00
56.53
76.48
59.85
73.15
66.50
66.50
66.50
66.50
61.85
71.16
63.18
69.83
67.83
67.83
67.83
67.83
1232A—06/12/06
6
Hi-Z
X/24
30.00
36.67
33.33
33.33
33.33
33.33
31.00
35.67
31.67
35.00
34.00
34.00
34.00
34.00
28.26
38.24
29.93
36.58
33.25
33.25
33.25
33.25
30.92
35.58
31.59
34.91
33.92
33.91
33.92
33.92
Spread
%
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
ICS951412B
Table2: SRC & ATIG Frequency Selection Table
Byte 5
Bit4
Bit3 Bit2 Bit1 Bit0 SRC(7:3,0),
Spread
ATIG(1:0)
SRC
%
SRC SRC SRC SRC
(MHz)
Spread
FS3 FS2 FS1 FS0
Enable
0
0
0
0
0
0
100.00
0
0
0
0
0
1
100.00
0
0
0
0
1
0
100.00
0
0
0
0
1
1
100.00
0
0
0
1
0
0
101.00
0
0
0
1
0
1
101.00
0
0
0
1
1
0
101.00
0
0
0
1
1
1
101.00
0
0
1
0
0
0
102.00
0
0
1
0
0
1
102.00
0
0
1
0
1
0
102.00
0
0
1
0
1
1
102.00
0
0
1
1
0
0
104.00
0
0
1
1
0
1
104.00
0
0
1
1
1
0
104.00
0
0
1
1
1
1
104.00
-0.5%
1
0
0
0
0
99.75
-0.5%
1
0
0
0
1
99.75
-0.5%
1
0
0
1
0
99.75
-0.5%
1
0
0
1
1
99.75
-0.5%
1
0
1
0
0
100.74
-0.5%
1
0
1
0
1
100.74
-0.5%
1
0
1
1
0
100.74
-0.5%
1
0
1
1
1
100.74
-0.5%
1
1
0
0
0
101.74
-0.5%
1
1
0
0
1
101.74
-0.5%
1
1
0
1
0
101.74
-0.5%
1
1
0
1
1
101.74
-0.5%
1
1
1
0
0
103.74
-0.5%
1
1
1
0
1
103.74
-0.5%
1
1
1
1
0
103.74
-0.5%
1
1
1
1
1
103.74
1232A—06/12/06
7
ICS951412B
SMBus Table: Frequency Select Register
Pin #
Name
Control Function
Byte 0
Latched Input or SMBus
FS Source
Bit 7
Frequency Select
CPU SS_EN
CPU Spread Enable
Bit 6
Reserved
Reserved
Bit 5
CPU FS4
Freq Select Bit 4
Bit 4
CPU FS3
Freq Select Bit 3
Bit 3
Type
0
1
PWD
RW
Latched Inputs
SMBus
0
RW
RW
RW
RW
OFF
Reserved
ON
Reserved
0
X
0
0
Bit 2
-
CPU FS2
Freq Select Bit 2
RW
Bit 1
-
CPU FS1
Freq Select Bit 1
RW
Bit 0
-
CPU FS0
Freq Select Bit 0
RW
See Table 1: CPU Frequency
Selection
Latched
Latched
Latched
Note: Byte 0 Bit 6, Byte 0 Bit 4 and Byte 5 Bit 4 must be set to '1' to fully enable spread.
SMBus Table: Output Control Register
Byte 1
Pin #
Name
50
PCICLK0
Bit 7
47
HTTCLK0
Bit 6
4
USB_48MHz
Bit 5
54
REF0
Bit 4
53
REF1
Bit 3
52
REF2
Bit 2
45,44
CPUCLK8(0)
Bit 1
41,40
CPUCLK8(1)
Bit 0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: CLKREQB# Output Control Register
Byte 2
Pin #
Name
Control Function
Type
REQBSRC7
CLKREQB# Controls SRC7 RW
12,13
Bit 7
REQBSRC6
CLKREQB# Controls SRC6 RW
16,17
Bit 6
REQBSRC5
CLKREQB# Controls SRC5 RW
18,19
Bit 5
REQBSRC4
CLKREQB# Controls SRC4 RW
22,23
Bit 4
REQBSRC3
CLKREQB# Controls SRC3 RW
24,25
Bit 3
Reserved
Reserved
RW
Bit 2
Reserved
Reserved
RW
Bit 1
REQBSRC0
CLKREQB# Controls SRC0 RW
34,33
Bit 0
1232A—06/12/06
8
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
0
Does not control
Does not control
Does not control
Does not control
Does not control
Reserved
Reserved
Does not control
1
Controls
Controls
Controls
Controls
Controls
Reserved
Reserved
Controls
PWD
0
0
0
0
0
X
X
0
ICS951412B
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
Byte 3
Pin #
Name
Control Function
Type
12,13
SRCCLK7
RW
Bit 7
Master Output control.
16,17
SRCCLK6
RW
Bit 6
Enables or disables output, RW
18,19
SRCCLK5
Bit 5
regardless of CLKREQ#
22,23
SRCCLK4
RW
Bit 4
inputs.
24,25
SRCCLK3
RW
Bit 3
34,33
SRCCLK0
RW
Bit 2
24,25
REQASRC3
CLKREQA# Controls SRC3 RW
Bit 1
34,33
REQASRC0
CLKREQA# Controls SRC0 RW
Bit 0
0
Disable
Disable
Disable
Disable
Disable
Disable
Does not control
Does not control
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
Byte 4
Pin #
Name
Control Function
Type
REQASRC7
CLKREQA# Controls SRC7 RW
12,13
Bit 7
REQASRC6
CLKREQA# Controls SRC6 RW
16,17
Bit 6
REQASRC5
CLKREQA# Controls SRC5 RW
18,19
Bit 5
REQASRC4
CLKREQA# Controls SRC4 RW
22,23
Bit 4
Does
Does
Does
Does
Bit 3
27,28
ATIGCLK1
Bit 2
30,29
ATIGCLK0
Bit 1
Bit 0
4
Reserved
USB_48Str
RW
Output Enable
These outputs cannot be
controlled by CLKREQ# pins. RW
Reserved
48MHz Strength Control
RW
RW
1
Enable
Enable
Enable
Enable
Enable
Enable
Controls
Controls
PWD
1
1
1
1
1
1
0
0
1
Controls
Controls
Controls
Controls
PWD
0
0
0
0
Disabled
Enabled
1
Disabled
Enabled
1
Reserved
2X
0
0
1
2X
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
0
not
not
not
not
control
control
control
control
Reserved
1X
Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
Behavior of the device is undefined under these conditions.
SMBus Table: Output Drive and ATIG Frequency Control Register
Byte 5
Pin #
Name
Control Function
Type
REF2Str
REF2 Strength Control
RW
52
Bit 7
Reserved
Reserved
RW
Bit 6
Reserved
Reserved
RW
Bit 5
SRC SSEN
SRC Spread Enable
RW
Bit 4
SRCFS3
Freq Select Bit 3
RW
Bit 3
SRCFS2
Freq Select Bit 2
RW
Bit 2
SRCFS1
Freq Select Bit 1
RW
Bit 1
SRCFS0
Freq Select Bit 0
RW
Bit 0
1232A—06/12/06
9
0
1X
Reserved
Reserved
See Table 2:
SRC Frequency Selection
ICS951412B
SMBus Table: Device ID Register
Byte 6
Pin #
Name
DevID 7
Bit 7
DevID 6
Bit 6
DevID 5
Bit 5
DevID 4
Bit 4
DevID 3
Bit 3
DevID 2
Bit 2
DevID 1
Bit 1
DevID 0
Bit 0
SMBus Table: Vendor ID Register
Byte 7
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: Byte Count Register
Byte 8
Pin #
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
1
0
0
1
0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
X
X
X
X
0
0
0
1
Revision ID
VENDOR ID
(0001 = ICS)
Control Function
Byte Count Programming
b(7:0)
Bytes 9 to 21 are reserved
1232A—06/12/06
10
0
1
Type
RW
RW
Writing to this register will
RW
configure how many bytes
RW
RW will be read back, default is 9
bytes.
RW
RW
RW
PWD
0
0
0
0
1
0
0
1
ICS951412B
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
V IH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
V SS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
V IN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
all outputs driven
VDD = 3.3 V
-5
5
uA
1
-5
uA
1
-200
uA
1
7
5
6
5
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
3
ms
1,2
33
5.5
0.4
kHz
V
V
mA
1
1
1
1
IIL1
Input Low Current
IIL2
Operating Current
3
Input Frequency
Pin Inductance1
Input Capacitance1
Clk Stabilization1,2
Modulation Frequency
SMBus Voltage
Low-level Output Voltage
Current sinking at VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time3
SCLK/SDATA
Clock/Data Fall Time3
IDD3.3OP
Fi
Lpin
CIN
COUT
CINX
TSTAB
V DD
V OL
Logic Inputs
Output pin capacitance
X1 & X2 pins
From V DD Power-Up or de-assertion
of PD# to 1st clock
Triangular Modulation
TYP
300
14.31818
30
2.7
@ I PULLUP
I PULLUP
MAX
4
UNITS NOTES
TRI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
TFI2C
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
2
1232A—06/12/06
11
ICS951412B
Electrical Characteristics - K8 Push Pull Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
Rising Edge Rate
δV/δt
Falling Edge Rate
δV/δt
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
measurement)
Differential Voltage
Change in VDIFF_DC
Magnitude
VDIFF
VCM
Change in Common
Mode Voltage
∆VCM
Jitter, Cycle to cycle
tjcyc-cyc
2
10
V/ns
1
2
10
V/ns
1
V
1
mV
1
V
1
200
mV
1
100 200
ps
1
0.4
∆VDIFF
Common Mode Voltage
MIN TYP MAX UNITS NOTES
-150
Measured at the AMD64 processor's
test load. (single-ended measurement)
150
1.05 1.25 1.45
-200
Measurement from differential
wavefrom. Maximum difference of cycle
time between 2 adjacent cycles.
1.25 2.3
0
Measured using the JIT2 software
package with a Tek 7404 scope.
TIE (Time Interval Error) measurement
tja
-1000
1000
Jitter, Accumulated
technique:
Sample resolution = 50 ps,
Sample Duration = 10 µs
Measurement from differential
dt3
Duty Cycle
45
53
wavefrom
Average value during switching
R
35
55
Output Impedance
transition. Used for determining series 15
ON
termination value.
Measurement from differential
tsrc-skew
250
Group Skew
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz
3
Spread Spectrum is off
1232A—06/12/06
12
1,2,3
%
1
Ω
1
ps
1
ICS951412B
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Vovs
Vuds
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Tabsmin
tr
tf
d-tr
d-tf
MAX
UNITS NOTES
Ω
850
1
1,3
mV
-150
150
1150
-300
250
Variation of crossing over all
edges
see Tperiod min-max values
75.00 MHz nominal
75.00 MHz spread
100.00 MHz nominal
100.00 MHz spread
116.67 MHz nominal
116.67 MHz spread
133.33 MHz nominal
133.33 MHz spread
@100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
-300
8.5684
8.5684
9.9970
9.9970
13.3303
13.3303
7.4972
7.4972
9.8720
175
175
1,3
mV
1
1
350
550
mV
1
12
140
mV
1
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1
1
1
1
300
8.5744
8.6244
10.0000 10.0030
10.0530
13.3333 13.3363
13.3863
7.5002 7.5032
7.5532
8.5714
30
30
700
700
125
125
Measurement from differential
45
55
%
1
wavefrom
Measurement from differential
tsrc-skew
Group Skew
250
ps
wavefrom
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
100
ps
1
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
1232A—06/12/06
13
ICS951412B
Electrical Characteristics - PCI33, HTT66 Clocks
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
PCI33 Clock period
Tperiod
HTT66 Clock period
Tperiod
Output High Voltage
Output Low Voltage
VOH
VOL
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
66.67MHz output nominal
66.67MHz output spread
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
-300
29.9910
29.9910
14.9955
14.9955
2.4
Output High Current
IOH
Output Low Current
IOL
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Jitter, Cycle to cycle
δV/δt
δV/δt
tr1
tf1
dt1
tsk1
tjcyc-cyc
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1
-33
-50
47
58
1
1
0.5
0.5
45
TYP
MAX
300
30.0090
30.1598
15.0045
15.0799
0.55
-46
-80
64
91
4
4
2
2
55
500
180
UNITS NOTES
ppm
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
ps
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF
is at 14.31818MHz
2
1232A—06/12/06
14
1,2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
ICS951412B
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
see Tperiod min-max values
48.00MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
-200
20.8257
2.4
Output High Current
IOH
Output Low Current
IOL
Edge Rate
Edge Rate
δV/ δt
δV/ δt
Rise Time
Fall Time
Duty Cycle
Jitter, Cycle to cycle
tr1
tf1
dt1
tjcyc-cyc
1
TYP
-33
-50
47
58
1
1
1
1
45
1.43
1.33
50
MAX
UNITS
Notes
200
20.8340
0.55
-46
-80
64
91
2
2
ppm
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
1,2
2
1
1
1
1
1
1
1
1
2
2
55
150
ns
ns
%
ps
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF
is at 14.31818MHz
1232A—06/12/06
15
ICS951412B
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Long Accuracy
ppm
Tperiod
see Tperiod min-max values
-300
300
ppm
1
Clock period
69.8270
69.8550
ns
2
Output High Voltage
VOH
14.318MHz output nominal
IOH = -1 mA
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
Output High Current
IOH
1
2.4
UNITS NOTES
V OH @MIN = 1.0 V
-29
-41
mA
V OH@MAX = 3.135 V
-45
-71
mA
1
V OL @MIN = 1.95 V
39
54
mA
1
V OL @MAX = 0.4 V
49
77
mA
1
4
V/ns
1
Output Low Current
IOL
Edge Rate
δV/ δt
Rising edge rate
1
Edge Rate
δV/ δt
4
V/ns
1
tr1
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
1
Rise Time
1
2
ns
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
1
Skew
tsk1
VT = 1.5 V
500
ps
1
Duty Cycle
dt1
VT = 1.5 V
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
300
ps
1
1
45
50
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF
is at 14.31818MHz
1232A—06/12/06
16
ICS951412B
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, Route as non
-coupled 50 ohm trace.
0.5 max
L2 length, Route as non
-coupled 50 ohm trace.
0.2 max
L3 length, Route as non
-coupled 50 ohm trace.
0.2 max
Rs
33
Rt
49.9
Down Device Differential Routing
L4 length, Route as coupled
microstrip 100 ohm
differential trace.
L4 length, Route as coup
led stripline 100 ohm
differential trace.
Differential Routing to PCI Express Connector
L4 length, Route as coupled
microstrip 100 ohm
differential trace.
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
L1
Unit
inch
inch
inch
ohm
ohm
Figure
2, 3
2, 3
2, 3
2, 3
2, 3
Dimension or Value
2 min to 16 max
Unit
inch
2
1.8 min to 14.4 max
inch
2
Dimension or Value
0.25 to 14 max
Unit
inch
3
0.225 min to 12.6
max
inch
3
Figure
L2
L4
Rs
L1’
L4’
L2’
Rs
Fig.1
Figure
Rt
HSCL Output
Buffer
Rt
L3’
L1
PCI Ex
REF_CLK
Test Load
L3
L2
L4
Rs
L1’
Fig.2
L4’
L2’
Rs
Rt
HSCL Output
Buffer
L3’
L1
Rt
PCI Ex Board
Down Device
REF_CLK Input
L3
L2
L4
Rs
L4’
L1’
L2’
Rs
Fig.3
Rt
HSCL Output
Buffer
L3’
1232A—06/12/06
17
Rt
L3
PCI Ex
Add In Board
REF_CLK Input
ICS951412B
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the
ICS951412B serve as dual signal functions to the device.
During initial power-up, they act as input pins. The logic
level (voltage) that is present on these pins at this time
is read and stored into a 5-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for
these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
1232A—06/12/06
18
ICS951412B
56-Lead, 300 mil Body, 25 mil, SSOP
c
N
SYMBOL
L
E1
INDEX
AREA
E
1 2
α
h x 45°
D
N
A1
-Cb
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
A
e
A
A1
b
c
D
E
E1
e
h
L
N
a
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
SEATING
PLANE
.10 (.004) C
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS951412BFLFT
Example:
ICS XXXX B F - LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
F = SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
1232A—06/12/06
19
MIN
.720
MAX
.730
ICS951412B
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
c
N
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
VARIATIONS
A1
-Ce
b
N
SEATING
PLANE
56
D mm.
MIN
13.90
D (inch)
MAX
14.10
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0039
Ordering Information
ICS951412BGLFT
Example:
ICS XXXX B G - LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
G = TSSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
1232A—06/12/06
20
MIN
.547
MAX
.555
ICS951412B
Revision History
Rev.
A
Issue Date Description
Page #
6/12/2006 Initial Release
-
1232A—06/12/06
21
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