ICS951413
Integrated
Circuit
Systems, Inc.
Programmable System Clock Chip for ATI RS400 P4TM-based Systems
Recommended Application:
ATI RS400 systems using Intel P4TM processors
Output Features:
•
6 - Pairs of SRC/PCI Express* clocks
•
2 - Pairs of programmable SRC/PCI Express (ATIG)
clocks
•
3 - Pairs of Intel P4 clocks
•
3 - 14.318 MHz REF clocks
•
1 - 48MHz USB clock
•
1 - 33 MHz PCI clock seed
Features/Benefits:
•
2 - Programmable Clock Request pins for SRC clocks
•
Supports CK410 or CK409 frequency table mapping
•
Spread Spectrum for EMI reduction
•
Outputs may be disabled via SMBus
•
External crystal load capacitors for maximum
frequency accuracy
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter 2.0V to enter test mode.
2. Cycle power to disable test mode
0929D—10/30/06
8
HW
TEST_SEL/REF2
HW PIN
2.0V
OUTPUT
NORMAL
HI-Z
ICS951413
Integrated
Circuit
Systems, Inc.
SMBus Table: Frequency Select Register
Pin #
Name
Control Function
Byte 0
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NOTE:
FS Source
Latched Input or SMBus
Frequency Select
Type
0
1
PWD
RW
Latched
Inputs
SMBus
0
CPU FS3
CPU Freq Select Bit3
RW
OFF
ON
(SS_EN)
(Spread Enable)
Reserved
Reserved
RW Reserved
Reserved
CK410#
CPU Freq Select Bit 4 RW
See Table 1: CPU
Reserved
Reserved
RW
Frequency
Selection
CPU FS_C
CPU Freq Select Bit 2 RW
Table
CPU FS_B
CPU Freq Select Bit 1 RW
CPU FS_A
CPU Freq Select Bit 0 RW
Byte 5 Bit 4 must also set to "1" in order to enable spread for SRC and ATIG clocks
-
SMBus Table: Output Control Register
Byte 1
Pin #
Name
50
PCICLK0
Bit 7
41,40
CPUCLK2
Bit 6
4
USB_48MHz
Bit 5
54
REF0
Bit 4
53
REF1
Bit 3
52
REF2
Bit 2
47,46
CPUCLK0
Bit 1
CPUCLK1
43,42
Bit 0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
SMBus Table: CLKREQB# Output Control Register
0
1
Pin #
Name
Control Function
Type
Byte 2
CLKREQB# Controls
Does not
12,13
REQBSRC7
RW
Controls
Bit 7
SRC7
control
CLKREQB# Controls
Does not
16,17
REQBSRC6
RW
Controls
Bit 6
SRC6
control
CLKREQB# Controls
Does not
18,19
REQBSRC5
RW
Controls
Bit 5
SRC5
control
CLKREQB# Controls
Does not
22,23
REQBSRC4
RW
Controls
Bit 4
SRC4
control
CLKREQB# Controls
Does not
24,25
REQBSRC3
RW
Controls
Bit 3
SRC3
control
0 = CPU is free-run
47,46
CPU0_Stop_En 1 = CPU is stopped by RW
Free-Run
Stoppable
Bit 2
CPU_STOP#
Reserved
RW Reserved
Reserved
Bit 1
CLKREQB# Controls
Does not
34,33
REQBSRC0
RW
Controls
Bit 0
SRC0
control
NOTE: CPU0_Stop_En (Byte2, bit 2) only exists in devices with REV ID = 2 or higher
0929D—10/30/06
9
0
X
Latched
0
Latched
Latched
Latched
PWD
1
1
1
1
1
1
1
1
PWD
0
0
0
0
0
1
X
0
ICS951413
Integrated
Circuit
Systems, Inc.
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
Byte 3
Pin #
Name
Control Function
Type
12,13
SRCCLK7
RW
Bit 7
Master
Output
control.
16,17
SRCCLK6
RW
Bit 6
Enables or disables
18,19
SRCCLK5
RW
Bit 5
output, regardless of
22,23
SRCCLK4
RW
Bit 4
CLKREQ# inputs.
24,25
SRCCLK3
RW
Bit 3
34,33
SRCCLK0
RW
Bit 2
CLKREQA# Controls
24,25
REQASRC3
RW
Bit 1
SRC3
CLKREQA# Controls
34,33
REQASRC0
RW
Bit 0
SRC0
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
Byte 4
Pin #
Name
Control Function
Type
CLKREQA# Controls
12,13
REQASRC7
RW
Bit 7
SRC7
CLKREQA# Controls
16,17
REQASRC6
RW
Bit 6
SRC6
CLKREQA# Controls
18,19
REQASRC5
RW
Bit 5
SRC5
CLKREQA# Controls
22,23
REQASRC4
RW
Bit 4
SRC4
Output Enable
27,28
ATIGCLK1
RW
Bit 3
These outputs cannot
be controlled by
30,29
ATIGCLK0
RW
Bit 2
CLKREQ# pins.
Differential
CPU, SRC,
Hi-Z or driven when
Output Disable
RW
Bit 1
ATIG
disabled
Mode
4
USB_48Str
48MHz Strength Control RW
Bit 0
0
Disable
Disable
Disable
Disable
Disable
Disable
Does not
control
Does not
control
1
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
Controls
0
Controls
0
1
PWD
Controls
0
Controls
0
Controls
0
Controls
0
Disabled
Enabled
1
Disabled
Enabled
1
Driven
Hi-Z
0
1X
2X
1
0
Does not
control
Does not
control
Does not
control
Does not
control
NOTE: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
Behavior of the device is undefined under these conditions.
SMBus Table: Output Drive and ATIG Frequency Control Register
Byte 5
Pin #
Name
Control Function
Type
REF2Str
REF2 Strength Control RW
52
Bit 7
Bit 6
41,40
CPU2_Stop_En
Bit 5
43,42
CPU1_Stop_En
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NOTE:
0 = CPU is free-run
1 = CPU is stopped by
CPU_STOP#
SRCFS4
(SS_EN)
SRCFS3
SRCFS2
SRCFS1
SRCFS0
CPU(1:2)_Stop_En (Byte5, bit 6:5)
-
0
1X
1
2X
PWD
1
RW
Free-Run
Stoppable
1
RW
Free-Run
Stoppable
1
Freq Select Bit 4
RW
(SS_EN)
See Table 2 SRC
Freq Select Bit 3
RW
Frequency Selection
Freq Select Bit 2
RW
Freq Select Bit 1
RW
Freq Select Bit 0
RW
only exist in devices with REV ID = 2 or higher
0929D—10/30/06
10
0
0
0
0
0
ICS951413
Integrated
Circuit
Systems, Inc.
SMBus Table: Device ID Register
Byte 6
Pin #
Name
DevID 7
Bit 7
DevID 6
Bit 6
DevID 5
Bit 5
DevID 4
Bit 4
DevID 3
Bit 3
DevID 2
Bit 2
DevID 1
Bit 1
DevID 0
Bit 0
SMBus Table: Vendor ID Register
Byte 7
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: Byte Count
Byte 8
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
1
0
0
1
1
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
X
X
X
X
0
0
0
1
Revision ID
Starts at 0 hex for A
revsion.
VENDOR ID
(0001 = ICS)
Control Function
Byte Count
Programming b(7:0)
0
1
Type
RW
RW
RW Writing to this register
RW will configure how many
RW bytes will be read back,
default is 9 bytes.
RW
RW
RW
SMBus Table: WD TimeR Control Register
0
1
Byte 9
Pin #
Name
Control Function
Type
Watchdog Hard Alarm
WDH_EN
RW
Disable
Enable
Bit 7
Enable
Watchdog Soft Alarm
WDS_EN
RW
Disable
Enable
Bit 6
Enable
WD Hard Status WD Hard Alarm Status
R
Normal
Alarm
Bit 5
WD Soft Status
WD Soft Alarm Status
R
Normal
Alarm
Bit 4
Watch Dog Time base
1160ms
WDTCtrl
RW 290ms Base
Bit 3
Control
Base
These bits represent
WD2
WD Timer Bit 2
RW
Bit 2
X*290ms (or 1.16S) the
watchdog timer waits
WD1
WD Timer Bit 1
RW
Bit 1
before it goes to alarm
mode. Default is 7 X
WD0
WD Timer Bit 0
RW
Bit 0
290ms = 2s.
0929D—10/30/06
11
PWD
0
0
0
0
1
0
0
1
PWD
0
0
X
X
0
1
1
1
ICS951413
Integrated
Circuit
Systems, Inc.
SMBus Table: M/N Programming & WD Safe Frequency Control Register
0
1
Pin #
Name
Control Function
Type
Byte 10
PLLS M/N
M/N_EN
RW
Disable
Enable
Bit 7
Programming Enable
Reserved
Reserved
RW
Bit 6
WD Safe Freq
Latch
WD Safe Freq Source RW B10b(4:0)
Bit 5
Source
Inputs
WD
SF4
RW
Bit 4
Writing to these bit will
WD SF3
RW
Bit 3
configure the safe
Watch Dog Safe Freq
WD SF2
RW
Bit 2
frequency as Byte0 bit
Programming bits
WD SF1
RW
Bit 1
(4:0).
WD SF0
RW
Bit 0
SMBus Table: CPU Frequency Control Register
Pin #
Name
Control Function
Byte 11
N Div8
N Divider Prog bit 8
Bit 7
Bit 6
-
N Div9
Bit 5
-
M Div5
N Divider Prog bit 9
Type
RW
Type
0
1
RW
RW
RW These Spread Spectrum
bits in Byte 13 and 14
RW
RW will program the spread
pecentage of CPU
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
Bit 3
-
M Div3
RW
Bit 2
-
M Div2
RW
Bit 1
-
M Div1
Bit 0
-
M Div0
RW
SMBus Table: CPU Frequency Control Register
Pin #
Name
Control Function
Byte 12
N Div7
Bit 7
Type
RW
RW
RW
Bit 6
-
N Div6
Bit 5
-
N Div5
Bit 4
-
N Div4
Bit 3
-
N Div3
Bit 2
-
N Div2
RW
Bit 1
-
N Div1
RW
Bit 0
-
N Div0
RW
RW
RW
0929D—10/30/06
12
0
0
0
0
0
PWD
X
M Div4
SMBus Table: CPU Spread Spectrum Control Register
Pin #
Name
Control Function
Byte 13
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
Spread Spectrum
SSP4
Bit 4
Programming bit(7:0)
SSP3
Bit 3
SSP2
Bit 2
SSP1
Bit 1
SSP0
Bit 0
0
0
1
The decimal
representation of M and
N Divier in Byte 11 and
12 will configure the
CPU VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
RW
-
N Divider Programming
Byte12 bit(7:0) and
Byte11 bit(7:6)
0
PWD
X
Bit 4
bit (5:0)
0
0
1
The decimal
representation of M and
N Divier in Byte 11 and
12 will configure the
CPU VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
RW
M Divider Programming
PWD
RW
RW
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ICS951413
Integrated
Circuit
Systems, Inc.
SMBus Table: CPU Spread Spectrum Control Register
Byte 14
Pin #
Name
Control Function
Reserved
Reserved
Bit 7
SSP14
Bit 6
SSP13
Bit 5
SSP12
Bit 4
Spread Spectrum
SSP11
Bit 3
Programming bit(14:8)
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
Type
0
1
R
RW
RW
These Spread Spectrum
RW
bits in Byte 13 and 14
RW
will program the spread
RW
pecentage of CPU
RW
RW
PWD
0
X
X
X
X
X
X
X
SMBus Table: SRC Frequency Control Register
Byte 15
Pin #
Name
Control Function
N Div8
N Divider Prog bit 8
Bit 7
Type
RW
0
1
The decimal
representation of M and
N Divier in Byte 15 and
16 will configure the
SRC VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
PWD
X
0
1
The decimal
representation of M and
N Divier in Byte 15 and
16 will configure the
SRC VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
PWD
X
Type
0
1
RW
RW
RW These Spread Spectrum
bits in Byte 17 and 18
RW
RW will program the spread
pecentage of SRC
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
Bit 6
-
N Div9
Bit 5
-
M Div5
RW
Bit 4
-
M Div4
RW
Bit 3
-
M Div3
Bit 2
-
M Div2
Bit 1
-
M Div1
RW
Bit 0
-
M Div0
RW
SMBus Table: SRC Frequency Control Register
Pin #
Name
Control Function
Byte 16
N
Div7
Bit 7
Type
RW
N Divider Prog bit 9
M Divider Programming
bits
RW
RW
RW
Bit 6
-
N Div6
RW
Bit 5
-
N Div5
RW
Bit 4
-
N Div4
Bit 3
-
N Div3
Bit 2
-
N Div2
RW
Bit 1
-
N Div1
RW
Bit 0
-
N Div0
RW
N Divider Programming
b(7:0)
SMBus Table: SRC Spread Spectrum Control Register
Pin #
Name
Control Function
Byte 17
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
Spread Spectrum
SSP4
Bit 4
Programming b(7:0)
SSP3
Bit 3
SSP2
Bit 2
SSP1
Bit 1
SSP0
Bit 0
0929D—10/30/06
13
RW
RW
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ICS951413
Integrated
Circuit
Systems, Inc.
SMBus Table: SRC Spread Spectrum Control Register
Pin #
Name
Control Function
Byte 18
Reserved
Reserved
Bit 7
SSP14
Bit 6
SSP13
Bit 5
SSP12
Bit 4
Spread Spectrum
SSP11
Bit 3
Programming b(14:8)
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
0
1
Type
R
RW
RW
These Spread Spectrum
RW
bits in Byte 17 and 18
RW
will program the spread
RW
pecentage of SRC
RW
RW
PWD
0
X
X
X
X
X
X
X
SMBus Table: Programmable Output Divider Register
Byte 19
Pin #
Name
Control Function
CPUDiv3
Bit 7
CPU Divider Ratio
CPUDiv2
Bit 6
Programming Bits
CPUDiv1
Bit 5
CPUDiv0
Bit 4
PCIDiv3
Bit 3
PCI Divider Ratio
PCIDiv2
Bit 2
Programming Bits
PCIDiv1
Bit 1
PCIDiv0
Bit 0
0
1
Type
RW
See Table 3: CPU
RW
Divider Ratios
RW
RW
RW
RW See Table 4: PCI Divider
Ratios
RW
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: Programmable Output Divider Register
Byte 20
Pin #
Name
Control Function
SRC_Div3
Bit 7
SRC_ Divider Ratio
SRC_Div2
Bit 6
Programming Bits
SRC_Div1
Bit 5
SRC_Div0
Bit 4
ATIG_Div3
Bit 3
ATIG_ Divider Ratio
ATIG_Div2
Bit 2
Programming Bits
ATIG_Div1
Bit 1
ATIG_Div0
Bit 0
0
1
Type
RW
RW
RW
RW See Table 5: ATIG and
SRC Divider Ratios
RW
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
SMBusTable: Test Byte Register
Test
Byte 21
`
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Test Function
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
0929D—10/30/06
14
Test Result
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
ICS951413
Integrated
Circuit
Systems, Inc.
Absolute Max
Symbol
VDD_A
VDD_In
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
Min
GND - 0.5
-65
0
Max
VDD + 0.5V
VDD + 0.5V
Units
V
V
°
150
70
115
C
°C
°C
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pullup resistors
VIN = 0 V; Inputs with pull-up
resistors
VSS - 0.3
-5
0.8
5
V
uA
1
1
-5
uA
1
-200
uA
1
VIH_FS
3.3 V +/-5%
0.7
VDD + 0.3
V
1
VSS - 0.3
0.35
V
1
400
70
12
7
5
6
5
mA
mA
mA
MHz
nH
pF
pF
pF
1
1
1
3
1
1
1
1
1.8
ms
1,2
33
kHz
1
300
us
1
5
5
5.5
0.4
ns
ns
V
V
1
2
1
1
mA
1
1000
ns
1
300
ns
1
IIL1
Input Low Current
IIL2
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
Operating Current
VIL_FS
3.3 V +/-5%
IDD3.3OP
Powerdown Current
IDD3.3PD
Input Frequency
Pin Inductance
Fi
Lpin
CIN
COUT
CINX
all outputs driven
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
Input Capacitance
Clk Stabilization
TSTAB
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
VDD
VOL
MIN
TFI2C
MAX
14.31818
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
30
2.7
@ IPULLUP
IPULLUP
TRI2C
TYP
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
2
0929D—10/30/06
15
UNITS Notes
ICS951413
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
CONDITIONS
MIN
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
MAX
UNITS
NOTES
Ω
1
850
1,3
mV
-150
150
1150
-300
250
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
1,3
550
mV
1
1
1
140
mV
1
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
700
700
125
125
mV
Measurement from differential
45
55
%
wavefrom
CPU(1:0), VT = 50%
tsk3
100
ps
Skew
CPU(1:0) to CPU2_ITP,
tsk4
Skew
150
ps
VT = 50%
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
125
ps
wavefrom (CPU2_ITP)
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
85
ps
wavefrom, (CPU(1:0))
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
0929D—10/30/06
16
1
1
1
1
1
ICS951413
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Zo
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Statistical measurement
on single ended signal
Measurement on single
ended signal using
660
-150
Crossing Voltage (abs)
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
tr
Fall Time
tf
Rise Time Variation
Fall Time Variation
d-tr
d-tf
TYP
MAX
Ω
850
150
1150
-300
250
Variation of crossing over
all edges
see Tperiod min-max
-300
values
100.00MHz nominal
9.9970
100.00MHz spread
9.9970
100.00MHz
9.8720
nominal/spread
VOL = 0.175V,
175
VOH = 0.525V
VOH = 0.525V
175
VOL = 0.175V
UNITS Notes
mV
mV
1
1,3
1,3
1
1
350
550
mV
1
12
140
mV
1
300
ppm
1,2
10.0030
10.0533
ns
ns
2
2
ns
1,2
700
ps
1
700
ps
1
125
125
ps
ps
1
1
30
30
Measurement from
45
55
%
1
differential wavefrom
VT = 50%
tsk3
250
ps
1
Skew
Measurement from
tjcyc-cyc
Jitter, Cycle to cycle
125
ps
1
differential wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
0929D—10/30/06
17
ICS951413
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
Clock period
Tperiod
Output High Voltage
Output Low Voltage
VOH
VOL
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
-300
29.9910
29.9910
2.4
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
1
1
0.5
0.5
45
Output High Current
IOH
Output Low Current
IOL
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Jitter
tr1
tf1
dt1
tjcyc-cyc
TYP
MAX
300
30.0090
30.1598
0.55
-33
-33
30
38
4
4
2
2
55
250
UNITS Notes
ppm
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
1,2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
see Tperiod min-max values
48.00MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
-100
20.8313
2.4
Output High Current
Output Low Current
IOH
IOL
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Jitter, Cycle to cycle
1
2
tr1
tf1
dt1
tjcyc-cyc
TYP
MAX
100
20.8354
38
2
2
ppm
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
1,2
2
1
1
1
1
1
1
1
1
2
2
55
175
ns
ns
%
ps
1
1
1
1
0.55
-33
-33
30
1
1
1
1
45
UNITS Notes
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0929D—10/30/06
18
ICS951413
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
Output High Current
IOH
Output Low Current
IOL
Rise Time
Fall Time
Skew
Duty Cycle
tr1
tf1
tsk1
dt1
Jitter
tjcyc-cyc
CONDITIONS
MIN
see Tperiod min-max values
-300
14.318MHz output nominal
69.8270
IOH = -1 mA
2.4
IOL = 1 mA
VOH @MIN = 1.0 V,
-29
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL
29
@MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
1
VOH = 2.4 V, VOL = 0.4 V
1
VT = 1.5 V
VT = 1.5 V
45
VT = 1.5 V
1
TYP
MAX
300
69.8550
UNITS Notes
0.4
ppm
ns
V
V
1
1
1
1
-23
mA
1
27
mA
1
2
2
500
55
ns
ns
ps
%
1
1,2
2
1,2
1000
ps
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0929D—10/30/06
19
ICS951413
Integrated
Circuit
Systems, Inc.
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, Route as non
-coupled 50 ohm trace.
0.5 max
L2 length, Route as non
-coupled 50 ohm trace.
0.2 max
L3 length, Route as non
-coupled 50 ohm trace.
0.2 max
Rs
33
Rt
49.9
Down Device Differential Routing
L4 length, Route as coupled
microstrip 100 ohm
differential trace.
L4 length, Route as coup
led stripline 100 ohm
differential trace.
Differential Routing to PCI Express Connector
L4 length, Route as coupled
microstrip 100 ohm
differential trace.
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
L1
Unit
inch
inch
inch
ohm
ohm
Figure
2, 3
2, 3
2, 3
2, 3
2, 3
Dimension or Value
2 min to 16 max
Unit
inch
2
1.8 min to 14.4 max
inch
2
Dimension or Value
0.25 to 14 max
Unit
inch
3
0.225 min to 12.6
max
inch
3
Figure
L2
L4
Rs
L1’
L4’
L2’
Rs
Fig.1
Figure
Rt
HSCL Output
Buffer
Rt
L3’
L1
PCI Ex
REF_CLK
Test Load
L3
L2
L4
Rs
L1’
Fig.2
L4’
L2’
Rs
Rt
HSCL Output
Buffer
L3’
L1
Rt
PCI Ex Board
Down Device
REF_CLK Input
L3
L2
L4
Rs
L4’
L1’
L2’
Rs
Fig.3
Rt
HSCL Output
Buffer
L3’
0929D—10/30/06
20
Rt
L3
PCI Ex
Add In Board
REF_CLK Input
ICS951413
Integrated
Circuit
Systems, Inc.
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS951416
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an output
function. In this mode the pins produce the specified buffered
clocks to external loads.
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0929D—10/30/06
21
ICS951413
Integrated
Circuit
Systems, Inc.
c
N
56-Lead, 300 mil Body, 25 mil, SSOP
L
E1
INDEX
AREA
E
1 2
α
h x 45°
D
A
A1
A
A1
b
c
D
E
E1
e
h
L
N
a
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
-C-
e
SYMBOL
SEATING
PLANE
b
.10 (.004) C
N
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
MIN
.720
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS951413yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0929D—10/30/06
22
MAX
.730
ICS951413
Integrated
Circuit
Systems, Inc.
c
N
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
A1
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
.236
.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
0°
8°
0°
8°
aaa
-0.10
-.004
-Ce
b
SEATING
PLANE
VARIATIONS
N
aaa C
56
D mm.
MIN
MAX
13.90
14.10
D (inch)
MIN
.547
Reference Doc.: JEDEC Publicat ion 95, M O-153
10-0039
Ordering Information
ICS951413yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0929D—10/30/06
23
MAX
.555
ICS951413
Integrated
Circuit
Systems, Inc.
Revision History
Rev.
D
Issue Date Description
10/30/2006 Fixed Comments on Bytes 11-12, 15-16 Text Cutoff.
0929D—10/30/06
24
Page #
12-13