DATASHEET
System Clock for Embedded AMDTM based Systems
Recommended Application:
AMD M690T/780E systems
•
•
•
•
•
•
•
2 - Greyhound compatible K8 CPU pair
4 - low-power differential SRC pairs
2 - low-power differential SouthBridge SRC pairs
3 - low-power differential ATIG pairs
1 - Selectable 100MHz low-power differential/ 66 MHz
single-ended HTT clock
2 - 48MHz USB clock
3 - 14.318MHz Reference clock
•
•
•
•
CPU outputs cycle-to-cycle jitter < 150ps
SRC outputs cycle-to-cycle jitter < 125ps
ATIG outputs cycle-to-cycle jitter < 125ps
+/- 300ppm frequency accuracy on CPU, SRC & ATIG
clocks
•
•
•
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
External crystal load capacitors for maximum
frequency accuracy
PCI Express Generation 2.0 compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9EPRS475
•
48MHz_1
48MHz_0
GND48
SMBCLK
SMBDAT
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
GNDSRC
VDDSRC
SRC1C_LPRS
SRC1T_LPRS
VDDSRC
GNDSRC
SRC0C_LPRS
SRC0T_LPRS
SB_SRC1C_LPRS
SB_SRC1T_LPRS
GNDSB_SRC
VDDSB_SRC
SB_SRC0C_LPRS
SB_SRC0T_LPRS
GNDATIG
ATIG2C_LPRS
ATIG2T_LPRS
GNDATIG
VDDATIG
9EPRS475
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD48
X2
X1
GNDREF
VDDREF
REF0/SEL_HTT66
REF1
REF2
VDDHTT
HTT0T_LPRS/66M
HTT0C_LPRS/66M
GNDHTT
RESTORE#
PD#
CPUKG0T_LPRS
CPUKG0C_LPRS
VDDCPU
GNDCPU
CPUKG1T_LPRS
CPUKG1C_LPRS
VDDA
GNDA
GND
VDD
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
56-Pin TSSOP
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
1
9EPRS475
System Clock for Embedded AMDTM based Systems
Pin Description
PIN #
1
2
3
4
5
TYPE
DESCRIPTION
48MHz_1
48MHz_0
GND48
SMBCLK
SMBDAT
PIN NAME
OUT
OUT
GND
IN
I/O
6
SRC3C_LPRS
OUT
7
SRC3T_LPRS
OUT
8
SRC2C_LPRS
OUT
9
SRC2T_LPRS
OUT
10
11
GNDSRC
VDDSRC
GND
PWR
12
SRC1C_LPRS
OUT
13
SRC1T_LPRS
OUT
14
15
VDDSRC
GNDSRC
PWR
GND
16
SRC0C_LPRS
OUT
17
SRC0T_LPRS
OUT
18
SB_SRC1C_LPRS
OUT
19
SB_SRC1T_LPRS
OUT
20
21
GNDSB_SRC
VDDSB_SRC
GND
PWR
22
SB_SRC0C_LPRS
OUT
23
SB_SRC0T_LPRS
OUT
24
GNDATIG
GND
25
ATIG2C_LPRS
OUT
26
ATIG2T_LPRS
OUT
27
28
GNDATIG
VDDATIG
GND
PWR
29
ATIG1C_LPRS
OUT
30
ATIG1T_LPRS
OUT
48MHz clock output.
48MHz clock output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Ground pin for the SRC outputs
Supply for SRC core, 3.3V nominal
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Supply for SRC core, 3.3V nominal
Ground pin for the SRC outputs
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to
GND and no 33 ohm series resistor needed
True clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
Ground pin for the SB_SRC outputs
Supply for SRC core, 3.3V nominal
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to
GND and no 33 ohm series resistor needed
True clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
Ground pin for the ATIG outputs
Complementary clock of low-power differential push-pull ATIG pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
Ground pin for the ATIG outputs
Power supply for ATIG core, nominal 3.3V
Complementary clock of low-power differential push-pull ATIG pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
2
9EPRS475
System Clock for Embedded AMDTM based Systems
Pin Description (Continued)
PIN #
PIN NAME
TYPE
ATIG0C_LPRS
OUT
32
ATIG0T_LPRS
OUT
33
34
35
36
VDD
GND
GNDA
VDDA
PWR
GND
GND
PWR
CPUKG1C_LPRS
OUT
38
CPUKG1T_LPRS
OUT
39
40
GNDCPU
VDDCPU
GND
PWR
CPUKG0C_LPRS
OUT
CPUKG0T_LPRS
OUT
31
37
41
42
PD#
IN
44
RESTORE#
I/O
45
GNDHTT
PWR
46
HTT0C_LPRS/66M
OUT
HTT0T_LPRS/66M
OUT
VDDHTT
REF2
REF1
PWR
OUT
OUT
43
47
48
49
50
REF0/SEL_HTT66
51
52
53
54
55
56
VDDREF
GNDREF
X1
X2
VDD48
I/O
PWR
GND
IN
OUT
PWR
DESCRIPTION
Complementary clock of low-power differential push-pull ATIG pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
Power supply, nominal 3.3V
Ground pin
Ground for the Analog Core
3.3V Power for the Analog Core
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated
series resistor.(no 33 ohm series resistor needed)
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
resistor. (no 33 ohm series resistor needed)
Ground pin for the CPU outputs
Supply for CPU core, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated
series resistor. (no 33 ohm series resistor needed)
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
resistor.(no 33 ohm series resistor needed)
Enter /Exit Power Down.
0 = Power Down, 1 = normal operation.
Open Drain I/O. As an input it restores the PLL's to power up default state. As an output, this signal
is driven low when the internal watchdog hardware timer expires. It is cleared when the internal
watchdog hardware timer is reset or disabled. The input is falling edge triggered.
0 = Restore Settings, 1 = normal operation.
Ground pin for the HTT outputs
Complementary signal of low-power differential push-pull hypertransport clock with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended
66MHz hyper transport clock
True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz
hyper transport clock
Supply for HTT clocks, nominal 3.3V.
14.318 MHz reference clock, 3.3V
14.318 MHz 3.3V reference clock
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock
Frequency.
0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock
Ref, XTAL power supply, nominal 3.3V
Ground pin for the REF outputs.
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
3
9EPRS475
System Clock for Embedded AMDTM based Systems
General Description
The ICS9EPRS475 is a main clock synthesizer chip that provides all clocks required for AMD embedded
systems. An SMBus interface allows full control of the device.
Block Diagram
X1
X2
REF
14.318MHz
OSC
48MHz
Fixed PLL
EXACT 48MHz
SS PLL
SB_SRC
(-0.5% DWN SP)
800MHz
100MHz
SS PLL
SRC/SB_SRC/ATIG
100MHz
SRC ZDB PLL
400 to 900 MHz
PWD @
600MHz/6
100MHz
SB_SRC
SRC
ATIG
SEL_HTT66
HTT_100T/66
HTT 100MHz
SS PLL
HTT 66MHz
HTT_100C/66
CPUKG
200MHz
PD#
SEL_HTT66
SMBCLK
SMBDAT
RESTORE#
Control
Logic
MODE
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
4
9EPRS475
System Clock for Embedded AMDTM based Systems
IDT® System Clock for Embedded AMDTM based Systems
66.67
68.89
71.11
73.33
75.56
77.78
80.00
82.22
84.44
86.67
88.89
91.11
93.33
95.56
97.78
100.00
100.00
103.13
106.25
109.38
112.50
115.63
118.75
121.88
125.00
128.13
131.25
134.38
137.50
140.63
143.75
146.88
CPU
Spread
CPU
Output
%
OverClock %
Divider
-0.5%
SB_SRC
(MHz)
Off
-0.50%
-0.50%
Table1: CPU and HTT Frequency Selection Table
Byte 3
HTT
HTT or
SingleSB_SRC
CPU
Bit5
Bit4
Bit3 Bit1 Bit0
ended
Differential
(MHz)
CPU
CPU
CPU CPU CPU
SEL_HTT66 = SEL_HTT66 =
1
0
FS4
FS3
FS2 FS1 FS0
0
0
0
0
0
133.33
44.44
66.67
0
0
0
0
1
137.78
45.93
68.89
0
0
0
1
0
142.22
47.41
71.11
0
0
0
1
1
146.67
48.89
73.33
0
0
1
0
0
151.11
50.37
75.56
0
0
1
0
1
155.56
51.85
77.78
0
0
1
1
0
160.00
53.33
80.00
0
0
1
1
1
164.44
54.81
82.22
0
1
0
0
0
168.89
56.30
84.44
0
1
0
0
1
173.33
57.78
86.67
0
1
0
1
0
177.78
59.26
88.89
0
1
0
1
1
182.22
60.74
91.11
0
1
1
0
0
186.67
62.22
93.33
0
1
1
0
1
191.11
63.70
95.56
0
1
1
1
0
195.56
65.19
97.78
0
1
1
1
1
200.00
66.67
100.00
1
0
0
0
0
200.00
66.67
100.00
1
0
0
0
1
206.25
68.75
103.13
1
0
0
1
0
212.50
70.83
106.25
1
0
0
1
1
218.75
72.92
109.38
1
0
1
0
0
225.00
75.00
112.50
1
0
1
0
1
231.25
77.08
115.63
1
0
1
1
0
237.50
79.17
118.75
1
0
1
1
1
243.75
81.25
121.88
1
1
0
0
0
250.00
83.33
125.00
1
1
0
0
1
256.25
85.42
128.13
1
1
0
1
0
262.50
87.50
131.25
1
1
0
1
1
268.75
89.58
134.38
1
1
1
0
0
275.00
91.67
137.50
1
1
1
0
1
281.25
93.75
140.63
1
1
1
1
0
287.50
95.83
143.75
1
1
1
1
1
293.75
97.92
146.88
-33%
-31%
-29%
-27%
-24%
-22%
-20%
-18%
-16%
-13%
-11%
-9%
-7%
-4%
-2%
0%
0%
3%
6%
9%
13%
16%
19%
22%
25%
28%
31%
34%
38%
41%
44%
47%
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCO
(MHz)
400.00
413.33
426.67
440.00
453.33
466.67
480.00
493.33
506.67
520.00
533.33
546.67
560.00
573.33
586.67
600.00
600.00
618.75
637.50
656.25
675.00
693.75
712.50
731.25
750.00
768.75
787.50
806.25
825.00
843.75
862.50
881.25
1615B—04/26/10
5
9EPRS475
System Clock for Embedded AMDTM based Systems
-0.48 max
-0.48 max
Bit4
SB
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTE:
Table 2: SRC Frequency Selection Table
Byte 4
SB_SRC
SRC
ATIG(3:0)
Spread
Bit3
Bit2
Bit1
Bit0
(1:0)
OverClo
(MHz)
(MHz)
%
SB
SB
SB
SB
(MHz)
ck %
FS3
FS2
FS1
FS0
0
0
0
0
87.00
87.00
87.00
-13%
0
0
0
1
87.87
87.87
87.87
-12%
0
0
1
0
88.73
88.73
88.73
-11%
0
0
1
1
89.60
89.60
89.60
-10%
0
1
0
0
90.47
90.47
90.47
-10%
0
1
0
1
91.33
91.33
91.33
-9%
0
1
1
0
92.20
92.20
92.20
-8%
0
1
1
1
93.07
93.07
93.07
-7%
1
0
0
0
93.93
93.93
93.93
-6%
1
0
0
1
94.80
94.80
94.80
-5%
1
0
1
0
95.67
95.67
95.67
-4%
1
0
1
1
95.67
95.67
95.67
-4%
1
1
0
0
97.40
97.40
97.40
-3%
1
1
0
1
98.27
98.27
98.27
-2%
1
1
1
0
99.13
99.13
99.13
-1%
Off
1
1
1
1
100.00
100.00
100.00
0%
0
0
0
0
100.00
100.00
100.00
0%
0
0
0
1
100.87
100.87
100.87
1%
0
0
1
0
101.73
101.73
101.73
2%
0
0
1
1
102.60
102.60
102.60
3%
0
1
0
0
103.47
103.47
103.47
3%
0
1
0
1
104.33
104.33
104.33
4%
0
1
1
0
105.20
105.20
105.20
5%
0
1
1
1
106.07
106.07
106.07
6%
1
0
0
0
106.93
106.93
106.93
7%
1
0
0
1
107.80
107.80
107.80
8%
1
0
1
0
108.67
108.67
108.67
9%
1
0
1
1
109.53
109.53
109.53
10%
1
1
0
0
110.40
110.40
110.40
10%
1
1
0
1
111.27
111.27
111.27
11%
1
1
1
0
112.13
112.13
112.13
12%
1
1
1
1
113.00
113.00
113.00
13%
All frequencies assume that the SRC / SB_SRC / ATIG are at 0% Overclocking.
IDT® System Clock for Embedded AMDTM based Systems
SRC
Output
Divider
VCO
(MHz)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
870.00
878.70
887.30
896.00
904.70
913.30
922.00
930.70
939.30
948.00
956.70
956.70
974.00
982.70
991.30
1000.00
1000.00
1008.70
1017.30
1026.00
1034.70
1043.30
1052.00
1060.70
1069.30
1078.00
1086.70
1095.30
1104.00
1112.70
1121.30
1130.00
1615B—04/26/10
6
9EPRS475
System Clock for Embedded AMDTM based Systems
General SMBus serial interface information for the ICS9EPRS475
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® System Clock for Embedded AMDTM based Systems
Not acknowledge
stoP bit
1615B—04/26/10
7
9EPRS475
System Clock for Embedded AMDTM based Systems
SMBus Table: Latched Input Readback Output Enable Control Register
Byte
0
Name
Description
X.3
0
1
Default
Bit 7
SEL_HTT66 readback
Hypertransport Select
R
100MHz Differential HTT
clock
66 MHz 3.3V Singleended HTT clock
Latch
Bit 5
REF0_OE
Output Enable
RW
Low
Enabled
1
Bit 4
REF1_OE
Output Enable
RW
Low
Enabled
1
Bit 3
REF2_OE
Output Enable
RW
Low
Enabled
1
Bit 2
48MHz_1_OE
Output Enable
RW
Low
Enabled
1
Bit 1
48MHz_0_OE
RW
Low
Enabled
1
Bit 0
SS_Enable
Output Enable
Spread Spectrum Enable
(CPU, HTT)
RW
Spread Off
Spread On
0
Byte
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
Byte
2
CPU1_OE
CPU0_OE
SRC3_OE
SRC2_OE
HTT100_OE
SRC1_OE
Output enable
Output enable
Output Enable
Output Enable
Output Enable
Output Enable
SRC0_OE
Output Enable
Bit 5
SRC_PLL_SS_Enable
ATIG2_OE
ATIG1_OE
ATIG0_OE
48MHz_1_Strength
48MHz_0_Strength
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Default
RW
RW
RW
RW
RW
RW
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Enable
Enable
Enabled
Enabled
Enabled
Enabled
RW
Low/Low
Enabled
1
1
1
1
1
1
1
1
SMBus Table: Output Enable and 48MHz Strength Control Register
Name
Control Function
Type
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
Type
Reserved
SB_SRC1_OE
SB_SRC0_OE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
SMBus Table:Output Enable Control Register
Name
Control Function
Bit 7
Bit 6
3
0
Reserved
Bit 6
Output Enable
Output Enable
Spread Spectrum Enable (SRC,
SB_SRC, ATIG)
Output Enable
Output Enable
Output Enable
48MHz_1 Drive Strength Sel.
48MHz_0 Drive Strength Sel.
SMBus Table: CPU/HTT Frequency Control Register
Name
Control Function
CPU_FS4
CPU_FS3
CPU_FS2
CPU_FS1
CPU_FS0
Reserved
Reserved
Reserved
CPU Frequency Select MSB
CPU Frequency Select
CPU Frequency Select
CPU Frequency Select
CPU Frequency Select LSB
SMBus Table: SRC Frequency Control Register
Name
Control Function
REF0_Strength
REF1_Strength
REF2_Strength
SRC_FS4
SRC_FS3
SRC_FS2
SRC_FS1
SRC_FS0
REF0_Drive Strength Sel
REF1_Drive Strength Sel
REF2_Drive Strength Sel
SRC Frequency Select MSB
SRC Frequency Select
SRC Frequency Select
SRC Frequency Select
SRC Frequency Select LSB
IDT® System Clock for Embedded AMDTM based Systems
0
1
Default
RW
RW
Low/Low
Low/Low
Enabled
Enabled
1
1
RW
Spread Off
Spread On
0
RW
RW
RW
RW
RW
Low/Low
Low/Low
Low/Low
1 Load
1 Load
Enabled
Enabled
Enabled
2 Load
2 Load
1
1
1
1
1
Type
0
1
Default
RW
RW
RW
RW
RW
See CPU Frequency Select Table
Default value corresponds to 200MHz.
Note that Selected HTT frequency tracks the
CPU frequency.
0
0
0
0
1
1
1
1
Type
0
1
Default
RW
RW
RW
RW
RW
RW
RW
RW
1 Load
1 Load
1 Load
2 Load
2 Load
2 Load
1
1
1
0
1
1
1
1
See SRC Frequency Select Table
Note: SB_SRC and ATIG Clocks are
synchronous to these outputs. Changing this
frequency will alter the SB_SRC and ATIG
frequency by the same percentage.
1615B—04/26/10
8
9EPRS475
System Clock for Embedded AMDTM based Systems
Byte
Byte
5
0
1
Default
0
0
0
0
Bit 3
Reserved
1
Bit 2
Reserved
1
Bit 1
Reserved
1
Bit 0
Reserved
1
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
Type
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
SMBus Table: Reserved
Name
9
SMBus Table: Reserved
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HTT66M_OE_1
HTT66M_OE_0
Output Enable
Output Enable
SMBus Table: Device ID register
Name
Control Function
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
Device ID
REVISION ID
VENDOR ID
SMBus Table: WatchDog Timer Control Register
Name
Control Function
HWD_EN
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
WD Hard Status
WDTCtrl
HWD3
HWD2
HWD1
Bit 0
HWD0
Low/Low
Low/Low
Enable
Enable
Type
0
1
Default
R
R
R
R
R
R
R
R
SMBus Table: Vendor & Revision ID Register
Name
Control Function
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
RW
RW
0
0
0
0
1
1
1
1
WD Hard Alarm Timer Bit 0
0
1
Default
R
R
R
R
R
R
R
R
-
-
0
0
1
0
0
0
0
1
0
1
Default
RW
R
RW
RW
RW
RW
RW
IDT® System Clock for Embedded AMDTM based Systems
70 hex
Type
Type
Watchdog Hard Alarm Enable
Reserved
WD Hard Alarm Status
Watch Dog Alarm Time base Control
WD Hard Alarm Timer Bit 3
WD Hard Alarm Timer Bit 2
WD Hard Alarm Timer Bit 1
0
1
1
1
0
0
0
0
Disable and Reload
Enable Timer
Hartd Alarm Timer Clear
Normal
290ms Base
Alarm
1160ms Base
These bits represent the number of Watch Dog
Time Base Units that pass before the Watch
Alarm expires. Default is 7 x 290 ms = 2s
0
0
X
0
0
1
1
1
1615B—04/26/10
9
9EPRS475
System Clock for Embedded AMDTM based Systems
Byte
10
SMBus Table: Reserved
Name
Control Function
Byte
11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
12
SMBus Table: Byte Count Register
Name
Control Function
BC5
BC4
BC3
BC2
BC1
BC0
Bit 7
Bit 6
CPU M/N En
SRC M/N En
Bit 5
SKIP_N_INC
Bit 2
IO_VOUT2
Bit 1
IO_VOUT1
Bit 0
IO_VOUT0
13
14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
CPU PLL M/N Prog. Enable
SRC M/N Prog.Enable
Skip N Incrementing during CPU PLL
M/N Programming
Reserved
Reserved
IO Output Voltage Select (Most
Significant Bit)
IO Output Voltage Select
IO Output Voltage Select (Least
Significant Bit)
SMBus Table: Reserved Register
Name
Control Function
RW
RW
RW
RW
RW
RW
0
1
Determines the number of bytes that are read
back from the device. Default is 0F hex.
CPU NDiv0
SB_SRCDiv3
SB_SRCDiv2
SB_SRCDiv1
SB_SRCDiv0
0
0
0
0
1
1
1
1
1
Default
M/N Prog. Disabled
M/N Prog. Disabled
M/N Prog. Enabled
M/N Prog. Enabled
0
0
RW
N-Increment
Bypass N-Increment
0
0
0
RW
RW
1
See Table 5: V_IO Selection
(Default is 0.8V)
RW
Type
0
1
0
1
Default
0
0
0
0
0
0
0
0
Type
LSB N Divider Programming
RW
Reserved
Reserved
Reserved
RW
SB_SRC Divider Ratio Programming
RW
Bits from CPU PLL
RW
RW
IDT® System Clock for Embedded AMDTM based Systems
Default
RW
RW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Reserved Register
Name
Control Function
Default
1
1
1
0
1
1
1
1
Type
Reserved
Reserved
Byte Count bit 5 (MSB)
Byte Count bit 4
Byte Count bit 3
Byte Count bit 2
Byte Count bit 1
Byte Count bit 0 (LSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
0
SMBus Table: M/N Programming Enable and I/O Vout Control Register
Name
Control Function
Type
0
Bit 4
Bit 3
Byte
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Byte 27 has the N Divider LSB (bit 0) for CPU
0000:/2 ; 0100:/4
0001:/3 ; 0101:/6
0010:/5 ; 0110:/10
0011:/9 ; 0111:/18
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/36 ; 1111:/72
Default
X
0
0
0
X
X
X
X
1615B—04/26/10
10
9EPRS475
System Clock for Embedded AMDTM based Systems
Byte
15
Bit 7
Byte
Type
0
1
Default
RW
Normal mode
All ouputs are REF/N
0
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
Reserved
0
Bit 2
Reserved
0
Bit 1
Reserved
0
Bit 0
Reserved
0
16
17
18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
Selects Test Mode
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
Test_Md_Sel
Bit 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
SMBus Table:Test Mode Register
Name
Control Function
19
SMBus Table: CPU PLL Frequency Control Register
Name
Control Function
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 2
N Divider Prog bit 1
RW
RW
RW
RW
RW
RW
RW
RW
M Divider Programming bits
SMBus Table: CPU PLL Frequency Control Register
Name
Control Function
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
N Divider Programming b(10:3)
SMBus Table: CPU PLL Spread Spectrum Control Register
Name
Control Function
Type
SB_SRC_Ssel
ATIG_Ssel
SRC_Ssel
SB_SRC_Ssel
Reserved
Reserved
Reserved
Reserved
SB_SRC PLL Source Selection (MSB)
ATIGCLK PLL Source Selection
SRC PLL Source Selection
SB_SRC PLL Source Selection (LSB)
SMBus Table: Reserved
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® System Clock for Embedded AMDTM based Systems
0
1
The decimal representation of M and N Divider in
Byte 16 and 17 will configure the VCO frequency.
Default at power up = Byte 0 Rom table. See M/N
Caculation Tables for VCO frequency formulas.
0
1
The decimal representation of M and N Divider in
Byte 16 and 17 will configure the VCO frequency.
Default at power up = Byte 0 Rom table. See M/N
Caculation Tables for VCO frequency formulas.
0
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
1
Default
RW
RW
RW
RW
10 - N/A
SRC PLL
SRC PLL
00 - SRC PLL
11 - CPU PLL
FIX PLL
FIX PLL
01 - FIX PLL
1
0
0
0
0
0
0
0
Type
0
1
Default
0
0
0
0
0
0
0
0
1615B—04/26/10
11
9EPRS475
System Clock for Embedded AMDTM based Systems
Byte
20
Bit 7
SMBUS Table: SRC spread enable
Name
Control Function
SRC_PLL_SS_Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
21
SMBUS Table: Reserved
Name
Control Function
22
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
23
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
24
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
0
1
Spread Off
Spread On
SMBUS Table: Reserved
Name
ATIGDiv3
ATIGDiv2
ATIGDiv1
ATIGDiv0
SB_SRCDiv3
SB_SRCDiv2
SB_SRCDiv1
SB_SRCDiv0
Control Function
ATIG Divider Ratio Programming Bits
SB_SRC Divider Ratio Programming
Bits from SRC Fixed / PLL
0
1
0
1
Default
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2 ; 0100:/4
N/A ; 0101:/6
N/A ; 0110:/10
N/A ; 0111:/14
0000:/2 ; 0100:/4
0001:/3 ; 0101:/6
0010:/5 ; 0110:/10
0011:/7 ; 0111:/14
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/28 ; 1111:/56
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/28 ; 1111:/56
X
X
X
X
X
X
X
X
0
1
Default
SMBUS Table: SRC Spread Spectrum Control Register
Name
Control Function
Type
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
RW
RW
RW
RW
RW
RW
RW
RW
Spread Spectrum Programming
bit(15:8)
IDT® System Clock for Embedded AMDTM based Systems
Default
Type
RW
RW
RW
RW
RW
RW
RW
RW
Spread Spectrum Programming
bit(7:0)
0
0
0
0
0
0
0
0
0
SMBUS Table: SRC Spread Spectrum Control Register
Name
Control Function
Type
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Default
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
Type
Spread Spectrum Enable (SRC,
RW
SB_SRC, ATIG)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
These bits set the SRC, the ATIG and SB_SRC
spread pecentages.Please contact ICS for the
appropriate values.
0
1
These bits set the SRC, the ATIG and SB_SRC
spread pecentages.Please contact ICS for the
appropriate values.
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
1615B—04/26/10
12
9EPRS475
System Clock for Embedded AMDTM based Systems
Byte
25
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
26
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
27
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
28
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
29
SMBUS Table: SRC Frequency Control Register
Name
Control Function
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Type
N Divider Prog bit 2
N Divider Prog bit 1
RW
RW
RW
RW
RW
RW
RW
RW
M Divider Programming
bit (5:0)
SMBUS Table: SRC Frequency Control Register
Name
Control Function
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
Type
RW
RW
RW
RW
RW
RW
RW
RW
N Divider Programming Byte16
bit(7:0) and Byte15 bit(7:6)
SMBUS Table: CPU Output Divider Control Register
Name
Control Function
HTTDiv3
HTTDiv2
HTTDiv1
HTTDiv0
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
HTT Divider Ratio Programming Bits
CPU Divider Ratio Programming Bits
Spread Spectrum Programming b(7:0)
1
NOTE: Changing this frequency will also alter the
ATIG and SB_SRC frequencies by a similar
amount.
0
1
The decimal representation of M and N Divider in
Byte 20 and 21 configure the SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
NOTE: Changing this frequency will also alter the
ATIG and SB_SRC frequencies by a similar
amount.
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
Type
0
1
Default
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2 ; 0100:/4
N/A ; 0101:/6
N/A ; 0110:/10
N/A ; 0111:/18
0000:/2 ; 0100:/4
0001:/3 ; 0101:/6
0010:/5 ; 0110:/10
0011:/9 ; 0111:/18
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/36 ; 1111:/72
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/36 ; 1111:/72
X
X
X
X
X
X
X
X
0
1
Default
SMBUS Table: CPU PLL Spread Spectrum Control Register
Name
Control Function
Type
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
0
The decimal representation of M and N Divider in
Byte 20 and 21 configure the SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
RW
RW
RW
RW
RW
RW
RW
RW
SMBUS Table: CPU PLL Spread Spectrum Control Register
Name
Control Function
Type
These bits set the CPU/HTT spread
pecentage.Please contact ICS for the appropriate
values.
0
1
RW
RW
RW
X
X
X
X
X
X
X
X
Default
Bit 7
Bit 6
Bit 5
SSP15
SSP14
SSP13
Bit 4
SSP12
Bit 3
Bit 2
SSP11
SSP10
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
RW
Spread Spectrum Programming
b(15:8)
RW
RW
IDT® System Clock for Embedded AMDTM based Systems
X
X
X
These bits set the CPU/HTT spread
pecentage.Please contact ICS for the appropriate
values.
X
X
X
1615B—04/26/10
13
9EPRS475
System Clock for Embedded AMDTM based Systems
Byte
30
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte
31
SMBUS Table: SRC Output Divider Control Register
Name
Control Function
SRC NDiv0
SRCDiv3
SRCDiv2
SRCDiv1
SRCDiv0
Type
RW
LSB N Divider Programming
Reserved
Reserved
Reserved
RW
RW
SRC Divider Ratio Programming Bits
RW
RW
SMBUS Table: Reserved Register
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® System Clock for Embedded AMDTM based Systems
0
1
Byte 30 has the N Divider LSB (bit 0) for SRC
Default
0000:/2 ; 0100:/4
N/A ; 0101:/6
N/A; 0110:/10
N/A; 0111:/14
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/28 ; 1111:/56
X
X
X
X
X
X
X
X
0
1
Default
X
X
X
X
X
X
X
X
1615B—04/26/10
14
9EPRS475
System Clock for Embedded AMDTM based Systems
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage
VDDxxx
-
Storage Temperature
Ts
-
-65
Ambient Operating Temp
Tambient
-
0
Case Temperature
Tcase
-
ESD prot
-
Input ESD protection HBM
1
MIN
TYP
MAX
UNITS
3.3
GND + 3.9V
V
1
°
C
1
70
°C
1
115
°C
1
V
1
Notes
150
2000
Notes
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
3.3V Core Supply Voltage
VDDxxx
-
3.135
3.3
3.465
V
1
Input High Voltage
VIH
VDD = 3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
VDD = 3.3 V +/-5%
0.8
V
1
Input High Current
IIH
5
uA
1
-5
uA
1
-200
uA
1
IIL1
Input Low Current
IIL2
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
VSS 0.3
-5
VIH_FS
VDD = 3.3 V +/-5%
0.7
VDD + 0.3
V
1
VIL_FS
VDD = 3.3 V +/-5%
VSS 0.3
0.35
V
1
115
mA
1
mA
1
Operating Current
IDD3.3OP
Powerdown Current
IDD3.3PD
3.3V VDD current, all outputs
driven
all diff pairs low/low
Input Frequency
Fi
VDD = 3.3 V +/-5%
Pin Inductance
Lpin
CIN
Logic Inputs
5
pF
1
Input Capacitance
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
From VDD Power-Up or deassertion of PD to 1st clock
Triangular Modulation
CPU output enable after
PD de-assertion
PD fall time of
5
pF
1
1.8
ms
1
33
kHz
1
300
us
1
5
ns
1
Clk Stabilization
TSTAB
Modulation Frequency
Tdrive_PD
Tfall_PD
7
Trise_PD
SMBus Voltage
12
14.31818
30
PD rise time of
2.7
VDDSMB
Low-level Output Voltage
VOLSMB
Current sinking at
IPULLUPSMB
VOL = 0.4 V
SMBCLK/SMBDAT
TRSMB
Clock/Data Rise Time
SMBCLK/SMBDAT
TFSMB
Clock/Data Fall Time
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
@ IPULLUP
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
MHz
2
nH
1
5
ns
1
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
6
1
Guaranteed by design and characterization, not 100% tested in production.
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL
outputs.
2
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
15
9EPRS475
System Clock for Embedded AMDTM based Systems
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT
PARAMETER
SYMBOL
CONDITIONS
Crossing Point Variation
ΔVCROSS
Single-ended Measurement
MIN
Frequency
f
Spread Specturm On
Long Term Accuracy
ppm
TYP
MAX
UNITS NOTES
140
mV
198.8
200
MHz
1,2,5
1,3
Spread Specturm Off
-300
+300
ppm
1,11
Rising Edge Slew Rate
SRISE
Differential Measurement
0.5
10
V/ns
1,4
Falling Edge Slew Rate
SFALL
Differential Measurement
0.5
10
V/ns
1,4
Slew Rate Variation
CPU, DIF HTT Jitter - Cycle to
Cycle
Accumulated Jitter
Peak to Peak Differential
Voltage
Differential Voltage
tSLVAR
Single-ended Measurement
20
%
1
CPUJ C2C
Differential Measurement
150
ps
1,6
tJACC
See Notes
1
ns
1,7
VD(PK-PK)
Differential Measurement
400
2400
mV
1,8
VD
Differential Measurement
200
1200
mV
1,9
Duty Cycle
DCYC
Differential Measurement
45
55
%
1
Amplitude Variation
ΔV D
Change in VD DC cycle to cycle
-75
75
mV
1,10
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
Notes on Electrical Characteristics:
Guaranteed by design and characterization, not 100% tested in production.
Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is
not important due to the blocking cap.
Minimum Frequency is a result of 0.5% down spread spectrum
Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate
spec when crossing through this region.
5
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK
meets CLK#.
6
Max difference of tCYCLE between any two adjacent cycles.
7
Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval.
8
VD(PK-PK) is the overall magnitude of the differential signal.
9
VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross
0V VD. VD(max) is the largest amplitude allowed.
10
The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the signal.
11
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
16
9EPRS475
System Clock for Embedded AMDTM based Systems
AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC, ATIG
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
0.6
4
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
0.6
4
V/ns
1,2
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
Crossing Point Voltage
VXABS
Single-ended Measurement
300
Crossing Point Variation
VXABSVAR
Single-ended Measurement
mV
1
550
mV
1,3,4
140
mV
1,3,5
Duty Cycle
DCYC
Differential Measurement
55
%
1
SRC Jitter - Cycle to Cycle
SRCJ C2C
Differential Measurement
125
ps
1
SRC[3:0] Skew
SRCSKEW
Differential Measurement
100
ps
1
SB_SRC[1:0] Skew
SRCSKEW
Differential Measurement
100
ps
1
45
Notes on Electrical Characteristics:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
5
6
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - Single-ended HTT 66MHz Clock
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
33.33MHz output nominal
29.9910
30.0090
ns
2
33.33MHz output spread
29.9910
30.1598
ns
2
66.67MHz output nominal
14.9955
15.0045
ns
2
66.67MHz output spread
14.9955
15.0799
ns
2
IOH = -1 mA
2.4
V
1
PCI33 Clock period
Tperiod
HTT66 Clock period
Tperiod
Output High Voltage
VOH
Output Low Voltage
VOL
Output High Current
IOH
Output Low Current
IOL
Edge Rate
δV/δt
Edge Rate
δV/δt
TYP
IOL = 1 mA
0.55
V OH @MIN = 1.0 V
V
1
mA
1
mA
1
mA
1
38
mA
1
1
4
V/ns
1
1
4
V/ns
1
55
%
1
180
ps
1
-33
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
Duty Cycle
dt1
VOL @ MAX = 0.4 V
Rising edge rate
(VOL = 0.4 V, VOH = 2.4 V)
Falling edge rate
(VOL = 0.4 V, VOH = 2.4 V)
VT = 1.5 V
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
-33
30
45
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
17
9EPRS475
System Clock for Embedded AMDTM based Systems
Electrical Characteristics - USB - 48MHz
PARAMETER
SYMBOL
CONDITIONS*
MIN
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Tperiod
Clock Low Time
Tlow
Clock High Time
MAX
UNITS
NOTES
-100
100
ppm
1,2
48.00MHz output nominal
20.8229
20.8344
ns
2
Measure from < 0.6V
9.3750
11.4580
ns
2
Thigh
Measure from > 2.0V
9.3750
11.4580
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
V
1
mA
1
mA
1
Output High Current
Output Low Current
IOL
Edge Rate
δV/δt
Edge Rate
δV/δt
Duty Cycle
dt1
Group Skew
tskew
Jitter, Cycle to cycle
tjcyc-cyc
0.55
V OH @MIN = 1.0 V
IOH
TYP
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
(VOL = 0.4 V, VOH = 2.4 V)
Falling edge rate
(VOL = 0.4 V, VOH = 2.4 V)
VT = 1.5 V
-33
30
mA
1
38
mA
1
1.3
4
V/ns
1
1.3
4
V/ns
1
1
45
VT = 1.5 V
VT = 1.5 V
55
%
250
ps
1
130
ps
1,2
MAX
UNITS
Notes
300
ppm
1,2
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
-300
TYP
Clock period
Tperiod
14.318MHz output nominal
69.8270
69.8550
ns
2
Clock Low Time
Tlow
Measure from < 0.6V
30.9290
37.9130
ns
2
37.9130
ns
2
V
1
0.4
V
1
Clock High Time
Thigh
Measure from > 2.0V
30.9290
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-29
-23
mA
1
Output Low Current
IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
29
27
mA
1
Edge Rate
δV/δt
1.3
2
V/ns
1
Edge Rate
δV/δt
1.3
2
V/ns
1
250
ps
1
55
%
1
300
ps
1
Skew
tsk1
Rising edge rate
(VOL = 0.4 V, VOH = 2.4 V)
Falling edge rate
(VOL = 0.4 V, VOH = 2.4 V)
VT = 1.5 V
Duty Cycle
dt1
VT = 1.5 V
Jitter
tjcyc-cyc
VT = 1.5 V
45
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
18
9EPRS475
System Clock for Embedded AMDTM based Systems
c
N
L
E1
E
INDEX
AREA
1 2
α
D
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
aaa
-0.10
-.004
A
A2
VARIATIONS
A1
N
-Ce
SEATING
PLANE
b
aaa C
56
D mm.
MIN
MAX
13.90
14.10
D (inch)
MIN
.547
MAX
.555
Reference Doc.: JEDEC Publication 95, M O-153
10-0039
Ordering Information
Part/Order Number
9EPRS475CGLF
9EPRS475CGLFT
Shipping Packaging
Tubes
Tape and Reel
Package
56-pin TSSOP
56-pin TSSOP
Temperature
0 to 70° C
0 to 70° C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS com pliant.
“C” is the device revision designator (w ill not correlate w ith the datasheet revision)
Due to package size constraints, actual top-side m arking may differ from the full orderable part num ber.
IDT® System Clock for Embedded AMDTM based Systems
1615B—04/26/10
19
9EPRS475
System Clock for Embedded AMDTM based Systems
Revision History
Rev.
0.1
A
Issue Date
7/31/2009
8/19/2009
RW
B
4/26/2010
RW
Description
Initial Release
Released to final.
1. Update part ordering information from "B" to "C"
2. Updated document template.
Page #
-
Various
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
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