DATASHEET
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Description
Features/Benefits
The ICS9FG104D is a Frequency Timing Generator that provides 4
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA.
The part synthesizes several output frequencies from either a
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be
driven by a reference input clock instead of a crystal. It provides
outputs with cycle-to-cycle jitter of less than 50 ps and output-tooutput skew of less than 35 ps. The ICS9FG104D also provides a
copy of the reference clock. Frequency selection can be
accomplished via strap pins or SMBus control.
•
•
•
•
•
•
ICS9FG104D
Generates common frequencies from 14.318 MHz or
25 MHz
Crystal or reference input
4 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications
•
•
•
•
Output cycle-to-cycle jitter < 50 ps
Output to output skew < 35 ps
+/-300 ppm frequency accuracy on output clocks
+/-50 ppm at any frequency w/spread off
Functional Block Diagram
XIN/CLKIN
R EF OU T
OSC
X2
2
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
CONTROL
LOGIC
SDATA
SCLK
IREF
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
1
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Functionality Table
ICS9FG104D
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.00
0
1
1
0
333.00
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.00
1
1
1
0
333.00
1
1
1
1
400.00
VDDA
GNDA
IREF
vFS0
vFS1
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
^SEL14M_25M#
vSPREAD
DIF_STOP#
^ Pin has internal 120K pull up
v Pin has internal 120K pull down
28-pin SSOP/TSSOP
Power Groups
Pin Number
VDD
GND
3
4
9,21
10,20
28
27
Description
REFOUT, Digital Inputs
DIF Outputs
IREF, Analog VDD, GND for PLL Core
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
2
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN #
1
2
3
4
5
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
6
vFS2
7
8
9
10
11
12
13
14
15
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
16
vSPREAD
IN
17
^SEL14M_25M#
IN
18
19
20
21
22
23
DIF_1#
DIF_1
GND
VDD
DIF_0#
DIF_0
24
vFS1
IN
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
25
vFS0
IN
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
OUT
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin
has a 120Kohm pull down resistor.
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
3
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol
Parameter
VDDxx
3.3V Supply Voltage
Ts
Storage Temperature
Tambient Ambient Operating Temp•(Commerical Grade)
Tambient Ambient Operating Temp•(Industrial Grade)
Tcase
Case Temperature
ESD prot
Input ESD protection•human body model
Min
Max
4.6
150
+70
+85
115
-65
0
-40
2000
Units
V
°
C
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = TA M B IENT ; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
Input Low Voltage
Input High Current
VIH
VIL
I IH
IIL1
Input Low Current
IIL2
I DD3.3OP
Operating Supply Current
I DD3.3STOP
Input Frequency 3
Fi
Pin Inductance1
Input/Output
Capacitance1
Lpin
CIN
COUT
TSTABcom
Clk Stabilization1,2
TSTABind
Modulation Frequency
Modulation Frequency
f MOD
f MOD
DIF output enable
t DIFOE
Input Rise and Fall times
tR/t F
CONDITIONS
MIN
TYP
VDD + 0.3
3.3 V +/-5%
2
V
- 0.3
3.3 V +/-5%
SS
VIN = VDD
-5
VIN = 0 V; Inputs with no pull-5
up resistors
VIN = 0 V; Inputs with pull-up
resistors
Full Active, CL = Full load;
f = 400 MHz
Full Active, CL = Full load;
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
SEL14M_25M# = 0
SEL14M_25M# = 1
Logic Inputs
Output pin capacitance
From VDD Power-Up to 1st
clock (Commercial)
From VDD Power-Up to 1st
clock (Industrial)
SEL14M_25M# = 0
SEL14M_25M# = 1
DIF output enable after
DIF_Stop# de-assertion
MAX
0.8
5
-200
V
V
uA
1
1
1
uA
1
uA
1
125
150
mA
1
110
125
mA
1
120
60
27.5
15.75
7
5
6
mA
mA
MHz
MHz
nH
pF
pF
1
1
3
3
1
1
1
1.8
ms
1,2
1.8
ms
1,2
kHz
kHz
1,3,4
1,3,4
15
ns
1
5
ns
1
106
48
22.5
25.00
12.886 14.31818
1.5
32.541
32.467
20% to 80% of VDD
UNITS NOTES
1
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF pin and tuned to 0 PPM to meet
ppm frequency accuracy on PLL outputs.
2
4
These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency
will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale.
For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 =
108MHz.
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
4
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = TA M B IENT ; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, I REF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
1
Output Impedance
Zo
V O = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
Crossing Voltage (var)
d-Vcross
Crossing variation over all edges
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew, output to output
Jitter, Cycle to cycle
tr
tf
d-t r
d-t f
dt3
tsk3
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, V OH = 0.525V
VOH = 0.525V VOL = 0.175V
t jcyc-cyc
Measured Differentially
V T = 50%
Measured Differentially
TYP
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
150
1150
-300
250
1
550
mV
1
1
1
140
mV
1
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
%
ps
ps
1,2,5
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
-300
300
2.49988 2.5000 2.5001
2.4993
2.5133
2.99985 3.0000 3.0002
2.9991
3.016
3.74981 3.7500 3.7502
3.7489
3.77
4.9998 5.0000 5.0003
4.9985
5.0266
5.9997 6.0000 6.0003
5.9982
6.0320
7.4996 7.5000 7.5004
7.4978
5.4000
9.9995 10.0000 10.0005
9.9970
10.0533
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
700
175
700
125
125
45
55
35
50
mV
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is tuned to 0
3
Figures are for down spread.
4
This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
5
+/- 50 ppm at any frequency with spread off
2
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
5
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - REF-14.318/25 MHz
TA = TA M B IENT ; V DD = 3.3 V +/-5%;RS=33Ω CL = 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Long Accuracy
ppm
Clock period
Tperiod
Output High Voltage
Output Low Voltage
VOH
VOL
Output High Current
I OH
Output Low Current
I OL
Rise Time
Fall Time
tr1
tf1
see Tperiod min-max values
14.318MHz output nominal
25.000MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V,
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
V OL @MAX = 0.4 V
V OL = 0.4 V, V OH = 2.4 V
V OH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt1
VT = 1.5 V
Jitter
Jitter
tjcyc-cycCOM
tjcyc-cycIND
VT = 1.5 V (commerical)
VT = 1.5 V (commerical)
MIN
TYP
MAX
0
69.8413
40.0000
UNITS Notes
0.4
ppm
ns
ns
V
V
1,2
1,2
1,2
1
1
-29
-23
mA
1
29
27
mA
1
2.4
1
1
1.6
1.6
2.5
2.5
ns
ns
1
1,2
45
52.5
55
%
1,2
150
400
200
600
ps
ps
1
1
Typ
Max
Units
Notes
40
86
1,2
1.2
3
2.2
3.1
0.25/0.2
0.5
2.2
3
1.8
2.5
ps (p-p)
ps
(RMS)
ps
(RMS)
ps
(RMS)
ps
(RMS)
ps
(RMS)
1
Guaranteed by design and characterization, not 100% tested in production.
Trim capacitors must be used to tune the REF to the exact Crystal Frequency.
2
Electrical Characteristics - Differential Phase Jitter Parameters
PARAMETER
Symbol
Conditions
tjphasePLL
PCIe Gen 1
PCIe Gen 2
10kHz < f < 1.5MHz
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
tjphaseLo
tjphaseHigh
Jitter, Phase
tjphQPI
tjphFBD3.2G
tjphFBD4.8G
QPI 133MHz 4.8G/6.4Gb,12UI
FBD specs
(11 to 33MHz)
FBD specs
(11 to 33MHz)
Min
1,2
1,2
1,3
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
See http://www.pcisig.com for compelte specs
3
First number is 4.8G link speed, second number is 6.4G link speed. From Intel Clock Jit tool 1.5.1
2
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
6
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG104D
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address DC(h)
WR
WRite
Controller (host) will send start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address DC(h)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
Repeat starT
Slave Address DD(h)
RD
ReaD
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Not acknowledge
stoP bit
1541C—12/16/10
7
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Pin #
17
Bit 6
Name
FS31
Control Function
Type
RW
0
1
6
FS21
RW
Bit 5
Bit 4
24
25
FS11
FS01
RW
RW
Bit 3
16
Spread Enable1
RW
Bit 2
-
Enable Software Control of Frequency, Spread Enable
(Spread Type always Software Control)
RW
Bit 1
DIF_STOP# drive mode
RW
Driven
Hi-Z
0
Bit 0
SPREAD TYPE
RW
Down
Center
0
0
1
Default
See Frequency Selection Table,
Page 1
Off
On
Hardware Select Software Select
Default
Pin 17
Pin 6
Pin 24
Pin 25
Pin 16
0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Pin #
Bit 7
-
Bit 6
-
DIF_3 EN
Output Enable
RW
Disable
Enable
Bit 5
-
DIF_2 EN
Output Enable
RW
Disable
Enable
Bit 4
-
Bit 3
-
Bit 2
-
DIF_1 EN
Output Enable
RW
Disable
Enable
1
Bit 1
-
DIF_0 EN
Output Enable
RW
Disable
Enable
1
Bit 0
-
Name
Control Function
Type
Reserved
1
1
1
1
Reserved
1
Reserved
Reserved
1
SMBus Table: Output Stop Control Register
Byte 2
Pin #
Bit 7
-
Bit 6
-
DIF_3 STOP EN
Bit 5
-
DIF_2 STOP EN
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
DIF_1 STOP EN
Free Run/ Stop Enable
RW
Free-run
Stop-able
Bit 1
-
DIF_0 STOP EN
Free Run/ Stop Enable
RW
Free-run
Stop-able
Bit 0
-
Name
Control Function
Type
0
1
Free Run/ Stop Enable
RW
Free-run
Stop-able
0
Free Run/ Stop Enable
RW
Free-run
Stop-able
0
Reserved
Reserved
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Default
0
0
0
0
0
0
1541C—12/16/10
8
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Frequency Select Readback Register
Byte 3
Pin #
Name
Control Function
Type
State of pin 17
R
0
1
Default
1
Bit 7
27
SEL14M_25M#
(FS3)
Bit 6
6
FS21
State of pin 6
R
Bit 5
44
FS11
State of pin 24
R
Bit 4
45
FS01
State of pin 25
R
Bit 3
16
SPREAD1
State of pin 26
R
Pin 17
See Frequency Selection Table,
Page 1
Pin 6
Pin 24
Pin 25
Off
On
Pin 16
Bit 2
Reserved
0
Bit 1
Reserved
0
Bit 0
Reserved
0
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Type
0
1
Default
Bit 7
-
RID3
R
-
-
X
Bit 6
-
RID2
R
-
-
X
Bit 5
-
RID1
R
-
-
X
Bit 4
-
RID0
R
-
-
X
Bit 3
-
VID3
R
-
-
0
Bit 2
-
VID2
R
-
-
0
Bit 1
-
VID1
R
-
-
0
Bit 0
-
VID0
R
-
-
1
Control Function
REVISION ID
VENDOR ID
SMBus Table: DEVICE ID
Byte 5
Pin #
Name
Type
0
1
Default
Bit 7
-
DID7
R
-
-
0
Bit 6
-
DID6
R
-
-
0
Bit 5
-
DID5
R
-
-
0
Bit 4
-
DID4
R
-
-
0
Bit 3
-
DID3
R
-
-
1
Bit 2
-
DID2
R
-
-
0
Bit 1
-
DID1
R
-
-
0
Bit 0
-
DID0
R
-
-
0
Type
0
1
Default
Control Function
Device ID = 08 hex
SMBus Table: Byte Count Register
Byte 6
Pin #
Name
Control Function
Bit 7
-
BC7
RW
-
-
0
Bit 6
-
BC6
RW
-
-
0
Bit 5
-
BC5
RW
-
-
0
Bit 4
-
BC4
RW
-
-
0
Bit 3
-
BC3
RW
-
-
0
Bit 2
-
BC2
RW
-
-
1
Bit 1
-
BC1
RW
-
-
1
Bit 0
-
BC0
RW
-
-
1
Writing to this register will
configure how many bytes will
be read back, default is 07 = 7
bytes.
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
9
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Reserved Register
Byte 7
Pin #
Bit 7
-
Reserved
0
Bit 6
-
Reserved
0
Bit 5
-
Reserved
0
Bit 4
-
Reserved
0
Bit 3
-
Reserved
0
Bit 2
-
Reserved
0
Bit 1
-
Reserved
0
Bit 0
-
Reserved
0
Name
Control Function
Type
0
1
Default
SMBus Table: Reserved Register
Byte 8
Pin #
Bit 7
-
Reserved
0
Bit 6
-
Reserved
0
Bit 5
-
Reserved
0
Bit 4
-
Reserved
0
Bit 3
-
Reserved
0
Bit 2
-
Reserved
0
Bit 1
-
Reserved
0
Bit 0
-
Reserved
0
Name
Control Function
Type
0
1
Default
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
-
M/N_Enable
M/N Prog. Enable
RW
Disable
Enable
0
REFOUT_En
REFOUT Enable
RW
Disable
Enable
Bit 6
-
Bit 5
5
Reserved
Bit 4
-
Reserved
0
Bit 3
-
Reserved
0
Bit 2
-
Reserved
0
Bit 1
-
Reserved
0
Bit 0
-
Reserved
0
1
1
SMBus Table: PLL Frequency Control Register
Byte 10
Pin #
Name
Control Function
Type
Bit 7
-
PLL N Div8
N Divider Prog bit 8
RW
Bit 6
-
PLL N Div9
N Divider Prog bit 9
RW
Bit 5
-
PLL M Div5
Bit 4
-
PLL M Div4
Bit 3
-
PLL M Div3
Bit 2
-
PLL M Div2
Bit 1
-
PLL M Div1
RW
Bit 0
-
PLL M Div0
RW
RW
RW
M Divider Programming
bit (5:0)
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
RW
RW
0
1
Default
X
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= fXTAL x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
X
X
X
X
X
X
X
1541C—12/16/10
10
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: PLL Frequency Control Register
Byte 11
Pin #
Name
Bit 7
-
PLL N Div7
RW
Bit 6
-
PLL N Div6
RW
Bit 5
-
PLL N Div5
RW
Bit 4
-
PLL N Div4
Bit 3
-
PLL N Div3
Bit 2
-
PLL N Div2
RW
Bit 1
-
PLL N Div1
RW
Bit 0
-
PLL N Div0
RW
Control Function
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
Type
RW
RW
0
1
Default
X
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= fXTAL x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
X
X
X
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 12
Pin #
Name
Bit 7
-
PLL SSP7
RW
X
Bit 6
-
PLL SSP6
RW
X
Bit 5
-
PLL SSP5
RW
Bit 4
-
PLL SSP4
Bit 3
-
PLL SSP3
Bit 2
-
PLL SSP2
RW
X
Bit 1
-
PLL SSP1
RW
X
Bit 0
-
PLL SSP0
RW
X
Control Function
Spread Spectrum
Programming bit(7:0)
Type
RW
RW
0
1
Default
X
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 13
Pin #
Bit 7
-
Bit 6
-
PLL SSP14
RW
X
Bit 5
-
PLL SSP13
RW
X
Bit 4
-
PLL SSP12
RW
Bit 3
-
PLL SSP11
Bit 2
-
PLL SSP10
Bit 1
-
PLL SSP9
RW
X
Bit 0
-
PLL SSP8
RW
X
Name
Control Function
Type
0
1
Reserved
Spread Spectrum
Programming bit(14:8)
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Default
0
RW
RW
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
X
X
X
1541C—12/16/10
11
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
12
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Rs
Rt
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
HCSL Output Buffer
Rt
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
HCSL Output Buffer
Rs
Rt
Rt
L3'
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
PCI Express
Add-in Board
REF_CLK Input
L3
1541C—12/16/10
13
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
HCSL Output Buffer
R2a
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
PCIe Device
REF_CLK Input
1541C—12/16/10
14
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
28-Pin SSOP Package Drawing and Dimensions
209 mil SSOP
c
N
SYMBOL
L
E1
A
A1
A2
b
c
D
E
E1
e
L
N
α
E
INDEX
AREA
1 2
α
h x 45°
D
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-2.00
0.05
-1.65
1.85
0.22
0.38
0.09
0.25
SEE VARIATIONS
7.40
8.20
5.00
5.60
0.65 BASIC
0.55
0.95
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
-.079
.002
-.065
.073
.009
.015
.0035
.010
SEE VARIATIONS
.291
.323
.197
.220
0.0256 BASIC
.022
.037
SEE VARIATIONS
0°
8°
VARIATIONS
N
A
28
-Cb
D (inch)
MAX
10.50
MIN
.390
MAX
.413
Reference Doc.: JEDEC Publication 95, MO-150
A1
e
D mm.
MIN
9.90
10-0033
SEATING
PLANE
.10 (.004) C
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
15
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
28-Pin TSSOP Package Drawing and Dimensions
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
c
N
SYMBOL
L
E1
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
INDEX
AREA
1 2
α
D
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
A
A2
N
28
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
MAX
.386
A1
- Ce
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
SEATING
PLANE
b
aaa C
Ordering Information
Part/Order Number
Shipping Packaging
Package
Temperature
9FG104DFLF
9FG104DFLFT
9FG104DFILF
9FG104DFILFT
9FG104DGLF
9FG104DGLFT
9FG104DGILF
9FG104DGILFT
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin TSSOP
28-pin TSSOP
28-pin TSSOP
28-pin TSSOP
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
16
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Revision History
Rev.
0.1
0.2
A
B
C
Issue Date Description
1. Created Rev D data sheet from original non revision specific version.
12/18/2008 2. Updated phase noise characterisitcs for Rev D.
3. Corrected footnote reference to ppm on CPU Electrical Characteristics
1. Updated PPM footnotes
4/1/2009 2. Modified input frequency ranges for each setting of the SEL14M_25M#
input.
1. Corrected/Added Tstab for Industrial Temperature Range
2. Corrected/Added REF cyc-cyc jitter for Industrial Temperature Range
5/14/2009 3. Move to final
1. Corrected PIN TYPE on pin 24. Changed pull up pull down designators to
11/8/2010 ^ and v respectively
12/16/2010 Updated VDD Supply Voltage specs
Page #
Various
4, 6
2, 3
4
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
TM
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
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