DATASHEET
DATASHEET
2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
Description
Features
The 2308B is a high-speed phase-lock loop (PLL) clock
multiplier. It is designed to address high-speed clock
distribution and multiplication applications. The zero delay
is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10
to 133MHz.
• Phase-Lock Loop Clock Distribution for Applications
ranging from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the
outputs to the clock input
The 2308B has two banks of four outputs each that are
controlled via two select addresses. By proper selection of
input addresses, both banks can be put in tri-state mode. In
test mode, the PLL is turned off, and the input clock directly
drives the outputs for system testing purposes. In the
absence of an input clock, the 2308B enters power down,
and the outputs are tri-stated. In this mode, the device will
draw less than 25µA.
• Output Skew < 200 ps
• Low jitter < 200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see Available Options for
2308B table)
•
•
•
•
The 2308B is available in six unique configurations for both
prescaling and multiplication of the Input REF Clock. (see
Available Options for 2308B table.)
The PLL is closed externally to provide more flexibility by
allowing the user to control the delay between the input
clock and the outputs.
No external RC network required
Operates at 3.3 V VDD
Available in 16-SOIC and 16-TSSOP packages
Available in commercial and industrial temperature
ranges
Block Diagram
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Applications
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Function Table1 Select Input Decoding
S2
S1
CLKA
CLKB
Output
Source
PLL Shut
Down
L
L
Tri-state
Tri-state
PLL
Y
L
H
Driven
Tri-state
PLL
N
H
L
Driven
Driven
REF
Y
H
H
Driven
Driven
PLL
N
Note 1: H = HIGH voltage level; L = LOW voltage level
Pin Descriptions
Pin Number
1
Pin Name
1
Pin Description
Input Reference Clock, 5 Volt Tolerant Input.
REF
CLKA1
2
Clock Output for Bank A.
3
CLKA2
2
Clock Output for Bank A.
4
VDD
5
GND
2
6
7
8
9
3.3 V Supply.
Ground.
CLKB1
2
Clock Output for Bank B.
CLKB2
2
Clock Output for Bank B.
3
Select Input, Bit 2.
S2
3
Select Input, Bit 1.
S1
CLKB3
2
Clock Output for Bank B.
11
CLKB4
2
Clock Output for Bank B.
12
GND
13
VDD
10
Ground.
3.3 V Supply.
CLKA3
2
Clock Output for Bank A.
15
CLKA4
2
Clock Output for Bank A.
16
FBK
14
PLL Feedback Input.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-up on these inputs.
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Available Options for 2308B
Device
Feedback From
Bank A Frequency
Bank B Frequency
2308B-1
Bank A or Bank B
Reference
Reference
2308B-1H
Bank A or Bank B
Reference
Reference
2308B-2
Bank A
Reference
Reference/2
2308B-2
Bank B
2 x Reference
Reference
2308B-2H
Bank A
Reference
Reference/2
2308B-2H
Bank B
2 x Reference
Reference
2308B-3
Bank A
2 x Reference
Reference or Reference1
2308B-3
Bank B
4 x Reference
2 x Reference
2308B-4
Bank A or Bank B
2 x Reference
2 x Reference
2308B-5H
Bank A or Bank B
Reference/2
Reference/2
Note 1: Output phase is indeterminant (0° or 180° from input clock).
Absolute Maximum Ratings1
Symbol
Max.
Unit
Supply Voltage Range
-0.5 V to +4.6
V
VI2
Input Voltage Range (REF)
-0.5 V to +5.5
V
VI
Input Voltage Range (except REF)
-0.5 to VDD + 0.5
V
VDD
Rating
IIK (VI < 0)
Input Clamp Current
-50
mA
IOK (VO < 0 or VO > VDD)
Terminal Voltage with Respect to
GND (inputs VIH 2.5, VIL 2.5)
±50
mA
IO (VO = 0 to VDD)
Continuous Output Current
±50
mA
Continuous Current
VDD or GND
±100
mA
TA = 55 °C (in still air only)3
Maximum Power Dissipation
0.7
W
TSTG
Storage Temperature Range
-65 to +150
C
Operating Temperature
Commercial range
0 to +70
C
Operating Temperature
Industrial range
-40 to +85
C
Notes:
1. Stresses above the ratings listed below can cause permanent damage to the 2308B. These ratings, which are standard
values for commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750
mils.
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Zero Delay and Skew Control
To close the feedback loop of the 2308B, the FBK pin can be driven from any of the eight available output pins. The
output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs) can adjust the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are required, use the Output Load Difference Chart to calculate
loading differences between the feedback output and remaining outputs. Ensure the outputs are loaded equally, for
zero output-output skew.
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Operating Conditions–Commercial
Symbol
VDD
Parameter
Conditions
Min.
Max.
Units
Supply Voltage
3
3.6
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance below 100 MHz
–
30
pF
Load Capacitance from 100 MHz to 133 MHz
–
15
pF
–
7
pF
CIN
Input
Capacitance1
Note 1: Applies to both REF and FBK.
DC Electrical Characteristics–Commercial
Parameter
Symbol
Input High Voltage Level
VIH
Input Low Voltage Level
VIL
Input Low Current
IIL
Input High Current
IIH
Conditions
Min.
Typ.
Max.
2
Units
V
0.8
V
VIN = 0V
50
A
VIN = VDD
100
A
Output High Voltage
VOH
IOH = -8 mA (-1, -2, -3, -4)
IOH = -12 mA (-1H, -2H, -5H)
Output Low Voltage
VOL
IOL = 8 mA (-1, -2, -3, -4)
IOL = 12 mA (-1H, -2H, -5H)
0.4
V
Power Down Current
IDD_PD
REF = 0MHz (S2 = S1 = H)
12
A
Supply Current
IDD
©2021 Renesas Electronics Corporation
Unloaded Outputs
Select Inputs at VDD or
GND
2.4
V
100 MHz CLKA (-1, -2, -3, -4)
45
100 MHz CLKA (-1H, -2H, -5H)
70
66 MHz CLKA (-1, -2, -3, -4)
32
66 MHz CLKA (-1H, -2H, -5H)
50
33 MHz CLKA (-1, -2, -3, -4)
18
33 MHz CLKA (-1H, -2H, -5H)
30
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MAY 21, 2021
2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Switching Characteristics–Commercial
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Output Frequency
t1
30 pF Load, all devices
10
100
MHz
Output Frequency
t1
20 pF Load, -1H, -2H, -5H Devices1
10
133.3
MHz
Output Frequency
t1
15pF Load, -1, -2, -3, -4 devices
10
133.3
MHz
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -2H, -5H)
Measured at 1.4V, FOUT = 66.66MHz, 30pF
Load
40
50
60
%
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -2H, -5H)
Measured at 1.4V, FOUT = 50MHz, 15pF
Load
45
50
55
%
Rise Time (-1, -2, -3, -4)
t3
Measured between 0.8V and 2V, 30pF Load
2.2
ns
Rise Time (-1, -2, -3, -4)
t3
Measured between 0.8V and 2V, 15pF Load
1.5
ns
Rise Time (-1H, -2H, -5H)
t3
Measured between 0.8V and 2V, 30pF Load
1.5
ns
Fall Time (-1, -2, -3, -4)
t4
Measured between 0.8V and 2V, 30pF Load
2.2
ns
Fall Time (-1, -2, -3, -4)
t4
Measured between 0.8V and 2V, 15pF Load
1.5
ns
Fall Time (-1H, -5H)
t4
Measured between 0.8V and 2V, 30pF Load
1.25
ns
Output to Output Skew on same Bank
(-1, -2, -3, -4)
t5
All outputs equally loaded
200
ps
Output to Output Skew (-1H, -2H, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output Bank B (-1, -4,
-2H, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output Bank B Skew
(-2, -3)
All outputs equally loaded
400
ps
Delay, REF Rising Edge to FBK Rising
Edge
t6
Measured at VDD/2
±250
ps
Device to Device Skew
t7
Measured at VDD/2 on the FBK pins of
devices
700
ps
Output Slew Rate
t8
Measured between 0.8V and 2V on -1H, -2H,
-5H device using Test Circuit 2
Cycle to Cycle Jitter
(-1, -1H, -4, -5H)
tJ
Measured at 66.67MHz, loaded outputs,
15pF Load
200
Measured at 66.67MHz, loaded outputs,
30pF Load
200
Measured at 133.3MHz, loaded outputs,
15pF Load
100
Measured at 66.67MHz, loaded outputs,
30pF Load
400
Measured at 66.67MHz, loaded outputs,
15pF Load
400
Cycle to Cycle Jitter
(-2, -2H, -3)
PLL Lock Time
tJ
tLOCK
1
Stable Power Supply, valid clocks presented
on REF and FBK pins
V/ns
1
ps
ps
ms
Note 1: 2308B-5H has maximum input frequency of 133.33MHz and maximum output of 66.67MHz.
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Operating Conditions–Industrial
Symbol
VDD
Parameter
Conditions
Supply Voltage
Max.
Units
3
3.6
V
-40
+85
°C
Load Capacitance below 100MHz
–
30
pF
Load Capacitance from 100MHz to 133MHz
–
15
pF
–
7
pF
TA
Operating Temperature (Ambient Temperature)
CL
CIN
Min.
Input
Capacitance1
Note 1: Applies to both REF and FBK.
DC Electrical Characteristics–Industrial
Parameter
Symbol
Input High Voltage Level
VIH
Input Low Voltage Level
VIL
Input Low Current
IIL
Input High Current
IIH
Conditions
Min.
Typ.
Max.
2
Units
V
0.8
V
VIN = 0V
50
A
VIN = VDD
100
A
Output High Voltage
VOH
IOH = -8 mA (-1, -2, -3, -4)
IOH = -12 mA (-1H, -2H, -5H)
Output Low Voltage
VOL
IOL = 8 mA (-1, -2, -3, -4)
IOL = 12 mA (-1H, -2H, -5H)
0.4
V
Power Down Current
IDD_PD
REF = 0MHz (S2 = S1 = H)
25
A
Supply Current
IDD
©2021 Renesas Electronics Corporation
Unloaded Outputs
Select Inputs at VDD or
GND
2.4
V
100 MHz CLKA (-1, -2, -3, -4)
45
100 MHz CLKA (-1H, -2H, -5H)
70
66 MHz CLKA (-1, -2, -3, -4)
32
66 MHz CLKA (-1H, -2H, -5H)
50
33 MHz CLKA (-1, -2, -3, -4)
18
33 MHz CLKA (-1H, -2H, -5H)
30
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MAY 21, 2021
2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Switching Characteristics–Industrial
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Output Frequency
t1
30 pF Load, all devices
10
100
MHz
Output Frequency
t1
20 pF Load, -1H, -2H, -5H Devices1
10
133.3
MHz
Output Frequency
t1
15pF Load, -1, -2, -3, -4 devices
10
133.3
MHz
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -2H, -5H)
Measured at 1.4V, FOUT = 66.66 MHz, 30 pF
Load
40
50
60
%
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -2H, -5H)
Measured at 1.4V, FOUT = 50 MHz, 15 pF
Load
45
50
55
%
Rise Time (-1, -2, -3, -4)
t3
Measured between 0.8V and 2V, 30pF Load
2.2
ns
Rise Time (-1, -2, -3, -4)
t3
Measured between 0.8V and 2V, 15pF Load
1.5
ns
Rise Time (-1H, -2H, -5H)
t3
Measured between 0.8V and 2V, 30pF Load
1.5
ns
Fall Time (-1, -2, -3, -4)
t4
Measured between 0.8V and 2V, 30pF Load
2.2
ns
Fall Time (-1, -2, -3, -4)
t4
Measured between 0.8V and 2V, 15pF Load
1.5
ns
Fall Time (-1H, -5H)
t4
Measured between 0.8V and 2V, 30pF Load
1.25
ns
Output to Output Skew on same Bank
(-1, -2, -3, -4)
t5
All outputs equally loaded
200
ps
Output to Output Skew (-1H, -2H, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output Bank B (-1, -4,
-2H, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output Bank B Skew
(-2, -3)
All outputs equally loaded
400
ps
Delay, REF Rising Edge to FBK Rising
Edge
t6
Measured at VDD/2
±250
ps
Device to Device Skew
t7
Measured at VDD/2 on the FBK pins of
devices
700
ps
Output Slew Rate
t8
Measured between 0.8V and 2V on -1H, -2H,
-5H device using Test Circuit 2
Cycle to Cycle Jitter
(-1, -1H, -4, -5H)
tJ
Measured at 66.67MHz, loaded outputs,
15pF Load
200
Measured at 66.67MHz, loaded outputs,
30pF Load
200
Measured at 133.3MHz, loaded outputs,
15pF Load
100
Measured at 66.67MHz, loaded outputs,
30pF Load
400
Measured at 66.67MHz, loaded outputs,
15pF Load
400
Cycle to Cycle Jitter
(-2, -2H, -3)
PLL Lock Time
tJ
tLOCK
1
Stable Power Supply, valid clocks presented
on REF and FBK pins
V/ns
1
ps
ps
ms
Note 1: 2308B-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Switching Waveforms
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Typical Duty Cycle1 and IDD Trends2 for 2308B-1, 2, 3, and 4
©2021 Renesas Electronics Corporation
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MAY 21, 2021
2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Typical Duty Cycle1 and IDD Trends2 for 2308B-1H, 2H, and 5H
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Test Circuits
Thermal Characteristics 16-TSSOP
Parameter
Symbol
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Min.
Typ.
Max. Units
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
37
C/W
JC
Thermal Characteristics 16-SOIC
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
JA
Still air
120
C/W
JA
1 m/s air flow
115
C/W
JA
3 m/s air flow
105
C/W
58
C/W
JC
Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas website (see
Ordering Information for POD links). The package information is the most current data available and is subject to change
without revision of this document.
©2021 Renesas Electronics Corporation
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Ordering Information
Part / Order Number Shipping Packaging
2308B-1DC
2308B-1DCI
2308B-1DCG
2308B-1DCGI
2308B-1DC8
2308B-1DCI8
2308B-1DCG8
2308B-1DCGI8
2308B-1HDC
2308B-1HDCI
2308B-1HDCG
2308B-1HDCGI
2308B-1HDC8
2308B-1HDCI8
2308B-1HDCG8
2308B-1HDCGI8
2308B-1HPG
2308B-1HPGI
2308B-1HPGG
2308B-1HPGGI
2308B-1HPG8
2308B-1HPGI8
2308B-1HPGG8
2308B-1HPGGI8
2308B-2DC
2308B-2DCI
2308B-2DCG
2308B-2DCGI
2308B-2DC8
2308B-2DCI8
2308B-2DCG8
2308B-2DCGI8
2308B-3DCG
2308B-3DCGI
2308B-3DCG8
2308B-3DCGI8
2308B-4DC
2308B-4DCI
2308B-4DCG
2308B-4DCGI
2308B-4DC8
2308B-4DCI8
2308B-4DCG8
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tubes
Tubes
Tape and Reel
Tape and Reel
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
©2021 Renesas Electronics Corporation
Package
Temperature
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
16-SOIC
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
13
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2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
Part / Order Number Shipping Packaging
2308B-4DCGI8
2308B-5HPG
2308B-5HPGI
2308B-5HPGG
2308B-5HPGGI
2308B-5HPG8
2308B-5HPGI8
2308B-5HPGG8
2308B-5HPGGI8
Tape and Reel
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
CLOCK MULTIPLIER
Package
Temperature
16-SOIC
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
16-TSSOP
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
0 to +70C
-40 to +85C
The 2308B-1, -2, -3, and -4 are Zero Delay Clock Buffers with Standard Drive.
The 2308B-1H, -2H, and -5H are Zero Delay Clock Buffers with High Drive.
Parts ordered with a “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
Revision History
Date
Description of Change
May 21, 2021
• Removed all IDT prefixes.
• Rebranded to Renesas.
• Updated Package Outline Drawings section.
• Updated Ordering Information table.
March 5, 2009
Updated part ordering to include 2308B-3DCG and -3DCGI.
November 3, 2008 Initial release.
©2021 Renesas Electronics Corporation
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16-SOIC Package Outline Drawing
0.150" Body Width, 0.050" Pitch
DCG16D1, PSC-4774-01, Rev 00, Page 1
© Integrated Device Technology, Inc.
16-SOIC Package Outline Drawing
0.150" Body Width, 0.050" Pitch
DCG16D1, PSC-4774-01, Rev 00, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Date Created
Rev No.
July 27, 2018
Rev 00
Description
Initial Release
16-TSSOP Package Outline Drawing
4.4mm Body, 0.65mm Pitch
PGG16T1, PSC-4749-01, Rev 00, Page 1
16-TSSOP Package Outline Drawing
4.4mm Body, 0.65mm Pitch
PGG16T1, PSC-4749-01, Rev 00, Page 2
Package Revision History
Date Created
Rev No.
Jan 26, 2018
Rev 00
Description
Revised from PSC-4056-02 PGG16
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