HIGH-SPEED 1.8V
32K x 16
ASYNCHRONOUS
DUAL-PORT
STATIC RAM
Features:
◆
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 12/15ns (max.)
– Industrial: 15ns (max.)
Low-power operation
– IDT70P27L
Active: 306mW (typ.)
Standby: 360µW (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
Dual chip enables allow for depth expansion without
external logic
IDT70P27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
◆
◆
◆
◆
◆
◆
◆
◆
IDT70P27L
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (1.7V < VDD < 1.95V) power
supply
Available in 100-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W L
UBL
R/WR
UBR
CE0L
CE0R
CE1L
CE1R
OEL
OER
LBL
LBR
I/O 8-15L
I/O8-15R
I/O
Control
I/O0-7L
BUSYL
I/O
Control
A14L
(1,2)
,
BUSYR
Address
Decoder
A0L
32Kx16
MEMORY
ARRAY
70P27
A14L
A0L
CE0L
CE1L
OEL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
R/WL
Address
Decoder
A14R
A0R
A14R
A0R
CE0R
CE1R
OER
R/WR
SEM L
INT L
I/O 0-7R
(1,2)
(2)
M/S
NOTES:
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
(2)
SEMR
(2)
INTR
5694 drw 01
JANUARY 2009
6.01
1
©2009 Integrated Device Technology, Inc.
DSC 5694/2
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
Description:
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 306mW of power. The IDT70P27
is packaged in a 100-pin Thin Quad Flatpack (TQFP).
The IDT70P27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
Pin Configurations(1,2,3)
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
INTL
BUSYL
VSS
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
09/29/06
INDEX
A9L
A10L
A11L
A12L
A13L
A14L
NC
NC
NC
LBL
UBL
CE0L
CE1L
SEML
VDD
R/WL
OEL
VSS
VSS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
11
12
13
14
IDT70P27PF
PN100-1(4)
100-PIN TQFP
TOP VIEW(5)
66
65
64
63
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R
A10R
A11R
A12R
A13R
A14R
NC
NC
NC
LBR
UBR
CE0R
CE1R
SEMR
VSS
R/WR
OER
VSS
VSS
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O9L
I/O8L
VDD
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
VSS
I/O1L
I/O0L
VSS
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
VDD
I/O7R
I/O8R
I/O9R
NC
5694 drw 02
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VDD
Power (1.8V)
Vss
Ground (0V)
5694 tbl 01
3
Commercial and Industrial Temperature Range
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
Truth Table I – Chip Enable(1,2,3)
CE
CE0
CE 1
V IL
VIH
< 0.2V
>VDD -0.2V
Port Selected (CMOS Active)
V IH
X
Port Deselected (TTL Inactive)
X
VIL
Port Deselected (TTL Inactive)
>V DD -0.2V
X
Port Deselected (CMOS Inactive)
X
VDD + 0.3V.
Recommended DC Operating
Conditions(1)
Symbol
VDD
Supply Voltage
VSS
Ground
VIH
VIL
Capacitance(1)
CIN
Parameter
Input Capacitance
(2)
COUT
Output Capacitance
Input High Voltage
Input Low Voltage
Min.
Typ.
Max.
Unit
1.7
1.8
1.95
V
0
0
0
0.7VDD
____
VDD+0.3V
____
0.3VDD
(1)
-0.3
V
(2)
V
V
5694 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
(TA = +25°C, f = 1.0mhz)TQFP ONLY
Symbol
Parameter
Conditions
Max.
Unit
VIN = 0V
9
pF
V OUT = 0V
10
pF
5694 tbl 08
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. COUT also reference CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1.7V < VDD < 1.95V)
70P27L
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
V DD = 1.95V, V IN = 0V to V DD
___
5
µA
|ILO|
Output Leakage Current
CE = VIH, V OUT = 0V to VDD
___
5
µA
IOL = 2mA
___
0.45
V
VDD - 0.45
___
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOH = -2mA
5694 tbl 09
5
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(4) (1.7V < VDD < 1.95V)
70P27L12
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70P27L15
Com'l & Ind
Typ.
Max.
Typ.
Max.
Unit
mA
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
COM'L
L
175
230
170
225
IND'L
L
____
____
170
235
Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L
L
12
20
10
18
IND'L
L
____
____
44
65
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
L
125
150
115
145
IND'L
L
____
____
115
155
COM'L
L
0.2
5
0.2
5
IND'L
L
____
____
0.2
6
COM'L
L
125
150
115
140
L
____
____
115
145
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Both Ports CEL and
CER > VDD - 0.2V
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
IND'L
mA
mA
mA
mA
5694 tbl 10b
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
2. f = 0 means no address or control lines change.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Refer to Chip Enable Truth Table.
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
1.8V
GND to 1.8V
0.9V
Output Reference Levels
0.9V
Output Load
590Ω
3ns Max.
Input Timing Reference Levels
1.8V
DATAOUT
BUSY
INT
590Ω
DATAOUT
435Ω
30pF
435Ω
5pF*
Figures 1 and 2
5694 tbl 11
,
5694 drw 04
Figure 1. AC Output Test Load
6
Figure 2. Output Test Load
(for t LZ, tHZ, tWZ, tOW)
*Including scope and jig
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
70P27L12
Com'l Only
Symbol
Parameter
70P27L15
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
____
15
____
ns
tAA
Address Access Time
____
12
____
15
ns
tACE
Chip Enable Access Time (3)
____
12
____
15
ns
tABE
Byte Enable Access Time (3)
____
12
____
15
ns
tAOE
Output Enable Access Time
____
9
____
10
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time (1,2)
3
____
3
____
ns
tHZ
Output High-Z Time (1,2)
____
10
____
12
ns
tPU
Chip Enable to Power Up Time (2,4)
0
____
0
____
ns
____
12
____
15
ns
8
____
10
____
ns
____
12
____
15
ns
(2,4)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access Time
5694 tbl 12a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. Refer to Chip Enable Truth Table.
7
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
Waveform of Read Cycles(5)
tRC
ADDR
(4)
CE
tAA
tACE(4)
(6)
tAOE(4)
OE
tABE(4)
UB, LB
R/W
tOH
tLZ(1)
(4)
DATAOUT
VALID DATA
tHZ(2)
BUSYOUT
,
tBDD
(3,4)
5694 drw 05
Timing of Power-Up Power-Down
CE
(6)
tPU
tPD
ICC
50%
50%
ISB
,
5694 drw 06
NOTES:
1. Timing depends on which signal is asserted last: CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD .
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
8
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
70P27L12
Com'l Only
Symbol
Parameter
70P27L15
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
12
____
15
____
ns
tEW
Chip Enable to End-of-Write
(3)
9
____
12
____
ns
tAW
Address Valid to End-of-Write
9
____
12
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
ns
tWP
Write Pulse Width
9
____
12
____
ns
0
____
0
____
ns
8
____
10
____
ns
____
8
____
10
ns
0
____
0
____
ns
____
8
____
10
ns
0
____
0
____
ns
5
____
5
____
ns
5
____
5
____
WRITE CYCLE
tWC
tWR
tDW
Write Cycle Time
Write Recovery Time
Data Valid to End-of-Write
(1,2)
tHZ
Output High-Z Time
tDH
Data Hold Time
tWZ
Write Enable to Output in High-Z (1,2)
tOW
Output Active from End-of-Write
tSWRD
SEM Flag Write to Read Time
tSPS
SEM Flag Contention Window
(4)
(1,2,4)
ns
5694 tbl 13a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM CE= VIL and SEM = V IH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable
Truth Table.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
9
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
(1,5,8)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
UB or LB
(9,10)
(9)
tAS(6)
tWP
(3)
(2)
tWR
R/W
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
,
5694 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM
(9,10)
tAS(6)
tWR(3)
tEW(2)
(9)
UB or LB
R/W
tDW
tDH
DATAIN
,
5694 drw 08
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP ) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
10
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
(1)
Timing Waveform of Semaphore Read after Write Timing, Either Side
tSAA
A0-A2
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM
tDW
I/O
DATAOUT(2)
VALID
DATA IN VALID
tAS
tWP
tOH
tSOP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
,
Read Cycle
5694 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATA OUT VALID" represents all I/O's (I/O0-I/O15 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
“A”
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
“B”
MATCH
R/W"B"
SEM"B"
,
5694 drw 10
NOTES:
1. DOR = D OL = VIL, CER = CE L = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
11
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70P27L12
Com'l Only
Symbol
Parameter
70P27L15
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
12
____
15
ns
12
____
15
ns
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
tBDA
BUSY Disable Time from Address Not Matched
____
tBAC
BUSY Access Time from Chip Enable Low
____
12
____
15
ns
tBDC
BUSY Disable Time from Chip Enable High
____
12
____
15
ns
5
____
5
____
ns
____
12
____
17
ns
12
____
12
____
ns
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data
tWH
Write Hold After BUSY(5)
(2)
(3)
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
12
____
ns
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
20
____
30
tDDD
Write Data Valid to Read Data Delay (1)
____
20
____
25
ns
5694 tbl 14a
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
12
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
(2,5)
(4)
Timing Waveform of Write with Port-to-Port Read and BUSY
(M/S = VIH)
tWC
ADDR"A"
MATCH
tWP
R/W "A"
tDW
DATAIN "A"
tDH
VALID
tAPS
(1)
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
,
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL (refer to Chip Enable Truth Table).
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input. Then for this example BUSY "A"= VIH and BUSY "B"= input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform Write with BUSY (M/S = VIL)
tWP
R/W"A"
tWB
(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
,
5694 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
3. tWB is only for the "Slave" version.
13
,
5694 drw 11
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
(1,3)
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
tBDC
BUSY"B"
,
5694 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
tAPS(2)
MATCHING ADDRESS "N"
ADDR"B"
tBAA
tBDA
BUSY"B"
,
5694 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P27L12
Com'l Only
Symbol
Parameter
70P27L15
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
0
____
0
____
ns
ns
ns
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
0
____
0
____
tINS
Interrupt Set Time
____
12
____
15
tINR
Interrupt Reset Time
____
20
____
25
ns
5694 tbl 15a
14
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
(1,5)
Commercial and Industrial Temperature Range
Waveform of Interrupt Timing
tWC
ADDR"A"
INTERRUPT SET ADDRESS
tAS
(2)
(3)
tWR
(4)
CE"A"
R/W"A"
tINS (3)
INT"B"
5694 drw 15
,
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
tAS
(2)
(3)
CE"B"
OE"B"
tINR
(3)
INT"B"
,
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
5694 drw 16
Truth Table IV — Interrupt Flag(1,4)
Left Port
Right Port
R/WL
CEL
OEL
A14L-A0L
INTL
R/WR
CER
OER
A14R-A0R
INTR
Function
L
L
X
7FFF
X
X
X
X
X
L(2)
Set Right INTR Flag
(3)
Reset Right INTR Flag
X
X
X
X
X
X
L
L
7FFF
H
X
X
X
X
L(3)
L
L
X
7FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
X
L
L
7FFE
H
5694 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
15
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
(4)
Truth Table V — Address BUSY Arbritration
Inputs
Outputs
CEL
CER
A0L-A14L
A0R-A14R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
5694 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70P27 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
5694 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P27.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0 - A 2.
Functional Description
The IDT70P27 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70P27 has an automatic power down feature
controlled by CE0 and CE1. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per the Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right
port interrupt flag (INTR) is asserted when the left port writes to memory
location 7FFF (HEX) and to clear the interrupt flag (INTR), the
right port must read the memory location 7FFF. The message (16 bits) at
7FFE or 7FFF is user-defined since it is an addressable SRAM location.
If the interrupt func-tion is not used, address locations 7FFE and 7FFF are
not used as mail boxes, but as part of the random access memory. Refer
to Truth Table IV for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
16
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Semaphores
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 70P27 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
A15
CE0
MASTER
Dual Port RAM
BUSYL
BUSYL
BUSYR
CE0
SLAVE
Dual Port RAM
BUSYL
BUSYR
CE1
MASTER
Dual Port RAM
CE1
SLAVE
Dual Port RAM
BUSYL
BUSYL
BUSYR
BUSYR
BUSYR
,
5694 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70P27 RAMs.
When expanding an IDT70P27 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master, use
the busy signal as a write inhibit signal. Thus on the IDT70P27 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = VIH), and
the BUSY pin is an input if the part is used as a slave (M/S pin = VIL) as
shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Commercial and Industrial Temperature Range
The IDT70P27 is a fast Dual-Port 32K x 16 CMOS Static RAM with
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where CE and SEM are both HIGH.
Systems which can best use the IDT70P27 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70P27's hardware semaphores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70P27 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
17
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70P27 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as a
one, a fact which the processor will verify by the subsequent read (see
Table VI). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during the subsequent read. Had a sequence of READ/WRITE been
Commercial and Industrial Temperature Range
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
WRITE
SEMAPHORE
READ
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
D
D0
WRITE
SEMAPHORE
READ
Figure 4. IDT70P27 Semaphore Logic
5694 drw 18
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low and the other
side high. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay low until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
18
IDT 70P27L
High-Speed 1.8V 32K x 16 Asynchronous Dual-Port Static RAM
Commercial and Industrial Temperature Range
Ordering Information
XXXXX
A
999
A
Device
Type
Power
Speed
Package
A
A
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
100-pin TQFP (PN100-1)
12
15
Commercial Only
Commercial & Industrial
L
Low Power
70P27
512K (32K x 16)1.8V Dual-Port RAM
Speed in nanoseconds
5694 drw 19
NOTES:
1. Industrial temperature range is available on selected TQFP packages in low power. For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
04/02/08:
01/19/09:
Initial Release
Page 19 Removed "IDT" from orderable part number
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19
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