Advance
Information
IDT71P71204
IDT71P71104
IDT71P71804
IDT71P71604
18Mb Pipelined
DDR™II SRAM
Burst of 2
Features
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Description
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
One Read or One Write request per clock cycle
DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
The IDT DDRIITM Burst of two SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at single
data rate speeds, allowing the user to fan out addresses and ease
system design while maintaining maximum performance on data transfers.
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the DDRII has an output “echo” clock,
CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and BWx or NWx), the
address, and the first word of the data burst during a write operation.
Functional Block Diagram
DATA
REG
(Note 1)
K
K
C
18M
MEMORY
ARRAY
(Note1)
(Note4)
OUTPUT SELECT
(Note3)
CTRL
LOGIC
(Note2)
OUTPUT REG
LD
R /W
BWx
ADD
REG
SENSE AMPS
SA
SA 0
WRITE/READ DECODE
WRITE DRIVER
(Note2)
CLK
GEN
(Note1)
DQ
CQ
CQ
SELECT OUTPUT CONTROL
C
6112 drw 16
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6112/00
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
The K clock is used to clock in the control signals (BWx or NWx), and the
second word of the data burst during a write operation. The K and K
clocks are also used internally by the SRAM. In the event that the user
disables the C and C clocks, the K and K clocks will also be used to clock
the data out of the output register and generate the echo clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the DDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the DDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the C clock.
The C and second data word of the burst will also correspond.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C and C
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing that
the echo clock will remain closely correlated with the data, within the
tolerances designated.
signals can be used to prevent writing any byte or individual nibbles,
or combined to prevent writing one word of the burst. The x18 and
x36 DDRll devices have the ability to address to the individual word
level using the SA0 address, but the burst will continue in a linear
sequence and wrap back on itself. The address will not increment to
the next higher burst address location, but instead will return to it’s
own lower words within the burst location. Similarly when reading x18
and x36 DDRll devices, the read burst will begin at the designated
address, but if the burst is started at any other position than the first
word of the burst, the burst will wrap back on itself and read the first
locations before completing.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and C clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BW or NW) inputs. On the following rising edge of K, the second half of the data write burst will be
accepted at the device input with the designated (BW or NW) inputs.
DDRII devices internally store two words of the burst as a single,
wide word and will retain their order in the burst. The x8 and x9
DDRII devices do not have the ability to address to the single word
level or reverse the burst order; however the byte and nibble write
6.42
2
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Input/Output
Synchronous
Data I/O s ignals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data
outputs are driven during a valid read operation. The outputs are aligned with the rising edge of both C and C
during normal operation. When operating in a single clo ck mode (C and C tied high), the outputs are aligned
with the rising edge of both K and K. When a Read operation is not initiated or LD is high (deselected) during
the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read operation in
progress completes.
2M x 8 -- DQ[7:0]
2M x 9 -- DQ[8:0]
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
BW0, BW1,
BW2, BW3
Input
Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising
edge of K clocks d uring write operations. Used to select which byte is writte n into the device during the
current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on
the same edge as the d ata. Deselecting a Byte Write Select will cause the corre sponding b yte of data to be
ignored and not written in to the device.
2M x 9 -- BW0 controls DQ[8:0]
1M x 18 -- BW0 controls DQ[8:0] and BW1 controls DQ[17:9]
512K x 36 -- BW0 controls DQ[8:0], BW1 controls DQ[17:9], BW2 controls DQ[26:18] and BW3 controls DQ[35:27]
NW0, NW1
Input
Synchronous
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is
written into the device during the current portion of the write operations. Nibbles not written remain unaltered.
All the nibble writes are s ampled on the same edge as the data. Dese lecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written in to the device.
SA
Input
Synchronous
Address Inputs. Address es are sampled on the rising edge of K cloc k during active read or write operations.
SA0
Input
Synchronous
Burst count address bit on x18 and x36 DDRll devices. This bit allows reversing the burs t order in read or
write operations, or addressing to the individual word of a burst.
LD
Input
Synchronous
Load Control Logic: Sampled on the rising edge of K. If LD is low, a two word burst read or write operation
will initiate as designated by the R/ W inp ut. If LD is high during the rising edge of K, operations in progress
will complete, but new operations will not be initiated.
R/W
Input
Synchronous
Read or Write Control Log ic. If LD is low during the rising edge of K, the R/W indicates whether a new
operation should be a read or write. If R/ W is high, a read op eration will be initiated, if R/ W is low, a write
operation will be initiated. If the LD input is high during the rising e dge of K, the R/ W input will be ignored.
C
Input Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data fro m the device. C
and C can be used toge ther to deskew the flight times of various devices on the board back to the controller.
See application example for further details.
C
Input Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C
and C can be used toge ther to deskew the flight times of various devices on the board back to the controller.
See application example for further details.
K
Input Clock
Positive Input Clock. The rising ed ge of K is used to capture synchronous inputs to the device and to drive
out data through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Input Clock
Negative Input Clock. K is used to capture synchronous inputs being presented to the device and to drive out
data through DQ[X:0] when in single clock mode.
DQ[X:0]
K
CQ, CQ
Output Clock
ZQ
Input
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals are free running and do not stop when
the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. DQ[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and
ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode.
This pin cannot be connec ted directly to GND or left unconnected.
6112 tbl 02a
6.42
3
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with
the DLL turned off will be different from those listed in this data sheet. There will be an
increased propagation delay from the incidence of C and C to DQ, or K and K to DQ as
configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
Doff
Input
TDO
Output
TDO pin for JTAG
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG. An internal resistor will pull TDI to V DD when the pin is unconnected.
TMS
Input
TMS pin for JTAG. An internal resistor will pull TMS to V DD when the pin is unconnected.
NC
No Connect No connects inside the package. Can be tied to any voltage level
VREF
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs and
outputs as well as AC measurement points.
VDD
Power
Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power
supply.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
VDDQ
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply
for HSTL or scaled to the desired output voltage.
6112 tbl 02b
6.42
4
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration 2M x 8
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (2)
SA
R/W
NW1
K
NC
LD
SA
VSS/
SA (1)
CQ
B
NC
NC
NC
SA
NC
K
NW0
SA
NC
NC
DQ3
C
NC
NC
NC
VSS
SA
SA
SA
V SS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
V SS
NC
NC
NC
E
NC
NC
DQ4
V DDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
V DDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
V DDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
V REF
VDDQ
V DDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
V DDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
V DDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
V DDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
V SS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
V SS
NC
NC
NC
P
NC
NC
DQ7
SA
SA
C
SA
SA
NC
NC
NC
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6112 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration 2M x 9
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (2)
SA
R/W
NC
K
NC
LD
SA
VSS/
SA (1)
CQ
B
NC
NC
NC
SA
NC
K
BW
SA
NC
NC
DQ3
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ7
SA
SA
C
SA
SA
NC
NC
DQ8
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6112 tb l 12a
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
6
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration 1M x 18
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (2)
SA
R/W
BW1
K
NC
LD
SA
VSS/
SA (1)
CQ
B
NC
DQ9
NC
SA
NC
K
BW0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA0
SA
V SS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
V SS
NC
NC
NC
E
NC
NC
DQ11
V DDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
V DDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
V DDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
V REF
VDDQ
V DDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
V DDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
V DDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
V DDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
V SS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
V SS
NC
NC
NC
P
NC
NC
DQ17
SA
SA
C
SA
SA
NC
NC
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6112 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to Vss on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
6.42
7
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration 512K x 36
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (3)
NC/
SA (1)
R/W
BW2
K
BW1
LD
SA
VSS/
SA (2)
CQ
B
NC
DQ27
DQ18
SA
BW3
K
BW0
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
SA0
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
P
NC
NC
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6112 tb l 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address.
3. A2 is reserved for the 144Mb expansion address
6.42
8
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Linear Burst Sequence Table (1,2)
Write Descriptions(1,2)
BW0
BW1
BW2
BW3
NW0
NW1
Write Byte 0
L
X
X
X
X
X
Write Byte 1
X
L
X
X
X
Write Byte 2
X
X
L
X
Write Byte 3
X
X
X
Write Nibble 0
X
X
Write Nibble 1
X
X
Signal
SA0
a
b
X
0
0
1
X
X
1
1
0
L
X
X
X
X
L
X
X
X
X
L
6112 tbl 22
NOTE:
1. SA0 is the address presented giving the burst sequence a,b.
2. SA0 is only available on the x18 and x36-bit devices.
6112 tbl 09
NOTES:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on the
rising edge of K and again on K. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding BWx or
NWx is held low. The rising edge of K will sample the first byte/nibble of the
two word burst and the rising edge of K will sample the second byte/nibble of
the two word burst.
2) The availability of the BWx or NWx on designated devices is described in
the pin description table.
3) The DDRII Burst of two SRAM has data forwarding. A read request that is
initiated on the cycle following a write request to the same address will produce
the newly written data.
6.42
9
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Application Example
SRAM #1
SRAM #4
R=250 Ω
R=250 Ω
ZQ
ZQ
Vt
DQ
SA LD R/W
BW0
BW1 C C K K
DQ
SA
R
LD R/W BW0 BW1 C C K K
Vt
Data Bus
R
Address
R
LD
R/W
BWx/NWx
R
R
R
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
Vt
R=50Ω Vt =VREF
6112 drw 20
6.42
10
Vt
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Absolute Maximum Ratings(1) (2)
S ym bol
Value
Unit
S up p ly Vo ltag e o n V DD with
Re s p e ct to G ND
–0.5 to + 2.9
V
V TERM
S up p ly Vo ltag e o n V DDQ with
Re s p e ct to G ND
–0.5 to V DD+ 0.3
V TERM
Vo lta g e o n Inp ut te rm inals with
re s p e c t to G ND
V TERM
Vo ltag e o n O utp ut and I/O
te rm inals with re s p e c t to G ND.
T B IA S
V TERM
Rating
Symbol
Parameter
C IN
Inp ut Cap acitance
V
C CLK
Clo ck Inp ut Capacitance
–0.5 to V DD + 0.3
V
CO
–0.5 to V DDQ + 0.3
V
Te m p e rature Und e r B ias
–55 to + 125
°C
T S TG
S to rag e Te m p e rature
–65 to + 150
°C
IOUT
Co ntinuo us Curre nt into O utp uts
+ 20
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
Recommended DC Operating and
Temperature Conditions
Parameter
Min.
Typ.
Max.
Unit
VDD
Power Supply
Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.9
V
VSS
Ground
0
0
0
V
VREF
Input Reference
Voltage
0.68
V DDQ/2
0.95
V
TA
Ambient
Temperature (1)
0
+70
o
_
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
V DD = 1.8V
V DDQ = 1.5V
Max.
Unit
5
pF
6
pF
7
pF
6112 tb l 06
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
6 112 tb l 0 5
Symbol
Outp ut Cap acitance
Conditions
c
6112 tbl 04
6.42
11
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Param eter
Sym bol
Test Conditions
Min
Max
Unit
Inp ut Le ak ag e Curre nt
IIL
V DD = M ax V IN = V SS to V DD Q
-10
+10
µA
Outp ut Le akag e Curre nt
IOL
Outp ut Dis ab le d
-10
+10
µA
333M H Z
-
TBD
300M H Z
-
TBD
250M H Z
-
TBD
200M Hz
-
TBD
167M Hz
-
TBD
333M H Z
-
TBD
300M H Z
-
TBD
250M H Z
-
TBD
200M Hz
-
TBD
167M Hz
-
TBD
Op e rating Curre nt
(x36,x18,x 9,x 8): DDR
Stand b y Curre nt: NOP
IDD
IS B1
V DD = M ax ,
IO UT = 0mA (o utp uts o p e n),
Cyc le Tim e > tKH K H M in
De vice De se le cte d (in NOP state ),
IO UT = 0mA (o utp uts o p e n),
f=M ax,
All Inp uts V DD -0.2V
Note
mA
1
mA
2
Outp ut Hig h Vo ltag e
V O H1
RQ = 250Ω, IOH = -15m A
V DD Q /2-0.12
V DD Q /2+0.12
V
3,7
Outp ut Lo w Vo ltag e
V OL1
RQ = 250Ω, IOH = 15mA
V DD Q /2-0.12
V DD Q /2+0.12
V
4,7
Outp ut Hig h Vo ltag e
V O H2
IOH = -0.1m A
V DD Q -0.2
V DD Q
V
5
Outp ut Lo w Vo ltag e
V OL2
IOL = 0.1m A
V SS
0.2
V
6
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss , and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
6.42
12
6112 tb l 10 c
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTES
Input High Voltage, DC
VIH (DC)
VREF +0.1
VDDQ +0.3
V
1,2
Input Low Voltage, DC
VIL (DC)
-0.3
VREF -0.1
V
1,3
Input High Voltage, AC
VIH (AC)
VREF +0.2
-
V
4,5
Input Low Voltage, AC
VIL (AC)
-
VREF -0.2
V
4,5
6112 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is V REF + 50mV. The AC VIH/V IL levels are defined separately for measuring timing parameters.
2. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width