IDT71P73604S167BQ

IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604 18Mb Pipelined DDR™II SRAM Burst of 4 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description The IDT DDRIITM Burst of four SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port. This scheme allows maximization on the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at less than single data rate speeds,allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36) Common Read and Write Data Port Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per two clock cycles. DDR (Double Data Rate) Data Bus - Four word bursts data per two clock cycles Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) JTAG Interface 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package Functional Block Diagram DATA REG (Note1) K K C C 18M MEMORY ARRAY (Note4) (Note4) OUTPUT SELECT (Note3) CTRL LOGIC (Note2) OUTPUT REG ADD REG SENSE AMPS LD RW BWx (Note2) WRITE/READ DECODE WRITE DRIVER SA SA0 SA 1 CLK GEN (Note1) DQ CQ CQ SELECT OUTPUT CONTROL 6431 drw 16 Notes 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2 signal lines. 4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36. JULY 2005 1 ©2005 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.“ DSC-6431/00 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Clocking The DDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the QDRII has an output “echo” clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals (LD, R/W and BWx or NWx), the address, and the first and third words of the data burst during a write operation. The K clock is used to clock in the control signals (BWx or NWx), and the second and fourth words of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the DDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the DDRII SRAM, the DLL will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the C clock. The C and second data item of the burst will also correspond. The third and fourth data words will follow on the next clock cycle of the C and C, respectively. Single Clock Mode The DDRII SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the DDRII SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Doff low. With the DLL off, the C and C (or K and K if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. Echo Clock The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. output at the designated time in correspondence with the C and C clocks. Write operations are initiated by holding the Read/Write control input (R/W) low, the load control input (LD) low and presenting the write address to the address port during the rising edge of K, which will latch the address. On the following rising edge of K, the first word of the four word burst must be present on the data input bus DQ[x:O], along with the appropriate byte write or nibble write (BWx or NWx) inputs. On the following rising edge of K, the second word of the data write burst will be accepted at the device input with the designated (BWx or NWx) inputs. The subsequent K and K rising edges will receive the last two words of the four word burst, with their BWx/NWx enables. DDRII devices internally store four words of the burst as a single, wide word and will retain their order in the burst. The x8 and x9 devices do not have the ability to address to the single word level or change the burst order; however the byte and nibble write signals can be used to prevent writing any byte or individual nibbles, or combined to prevent writing one word of the burst. The x18 and x36 DDRll devices have the ability to address to the individual word level using the SA0 and SA1 address bits, but the burst will continue in a linear sequence and wraps around without incrementing the SA bits. When reading or writing x18 and x36 DDRll devices, the burst will begin at the designated address, but if the burst is started at any other position than the first word of the burst, the burst will wrap back on itself and read the first locations before completing. The x18 and x36 DDRII devices can also use the byte write signals to prevent writing any individual byte or word of the burst. Output Enables The DDRII SRAM automatically enables and disables the DQ[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the DQ outputs will come up in a high impedance state. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM to it’s lowest value, the ZQ pin may be tied to VDDQ. Read and Write Operations Read operations are initiated by holding Read/Write control input (R/W) high, the load control input (LD) low and presenting the read address to the address port during the rising edge of K, which will latch the address. The data will then be read and will appear at the device 6.42 2 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Definitions Symbol Pin Function Description Input/Output Synchronous Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven during a valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When operating in a single clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a Read operation is not initiated or LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read operation in progress completes. 2M x 8 -- DQ[7:0] 2M x 9 -- DQ[8:0] 1M x 18 -- DQ[17:0] 512K x 36 -- DQ[35:0] Input Synchronous Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device. 2M x 9 -- BW0 controls DQ[8:0] 1M x 18 -- BW0 controls DQ[8:0] and BW1 controls DQ[17:9] 512K x 36 -- BW0 controls DQ[8:0], BW1 controls DQ[17:9], BW2 controls DQ[26:18] and BW3 controls DQ[35:27] NW0, NW1 Input Synchronous Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the device. 2M x 8 -- NW0 controls D[3:0] and NW1 controls D[7:4]. SA Input Synchronous Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations. SA0, SA1 Input Synchronous Burst count address bits on x18 and x36 DDRll devices. These bits allow changing the burst order in read or write operations, or addressing to the individual word of a burst. See page 9 for all possible burst sequences. LD Input Synchronous Load Control Logic. Sampled on the rising edge of K. If LD is low, a four word burst read or write operation will initiate designated by the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated. R/W Input Synchronous Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation should be a read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is high during the rising edge of K, the R/W input will be ignored. DQ[X:0] BW0, BW1 BW2, BW3 C Input Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through DQ[X:0] when in single clock mode. CQ, CQ Output Clock Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is three stated. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. 6431 tbl 02a 6.42 3 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Definitions continued Symbol Pin Function Description Doff Input DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to DQ, or K and K to DQ as configured. The propagation delay is not a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade. TDO Output TDO pin for JTAG TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. An internal resistor will pull TDI to V DD when the pin is unconnected. TMS Input TMS pin for JTAG. An internal resistor will pull TMS to V DD when the pin is unconnected. NC No Connect No connects inside the package. Can be tied to any voltage level VREF Input Reference Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. VDD Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply. VSS Ground Ground for the device. Should be connected to ground of the system. VDDQ Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage. 6431 tbl 02b 6.42 4 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Configuration IDT71P73204 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (2) SA R/W NW1 K NC LD SA VSS/ SA (1) CQ B NC NC NC SA NC K NW0 SA NC NC C NC NC NC VSS SA NC SA VSS NC NC D NC NC NC VSS VSS VSS V SS VSS NC NC E NC NC DQ4 VDDQ VSS VSS V SS VDDQ NC NC F NC NC NC VDDQ VDD VSS V DD VDDQ NC NC G NC NC DQ5 VDDQ VDD VSS V DD VDDQ NC NC H Doff VREF VDDQ VDDQ VDD VSS V DD VDDQ VDDQ VREF J NC NC NC VDDQ VDD VSS V DD VDDQ NC DQ1 K NC NC NC VDDQ VDD VSS V DD VDDQ NC NC L NC DQ6 NC VDDQ VSS VSS V SS VDDQ NC NC M NC NC NC VSS VSS VSS V SS VSS NC NC N NC NC NC VSS SA SA SA VSS NC NC P NC NC DQ7 SA SA C SA SA NC NC R TDO TCK SA SA SA C SA SA SA TMS 165-ball FBGA Pinout TOP VIEW NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address. 6.42 5 DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 6431 tbl 12 NC NC NC TDI IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Configuration IDT71P73104 (2M x 9) 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (2) SA R/W NC K NC LD SA VSS/ SA (1) CQ B NC NC NC SA NC K BW SA NC NC DQ3 C NC NC NC VSS SA NC SA VSS NC NC NC D NC NC NC VSS VSS VSS V SS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS V SS VDDQ NC NC DQ2 F NC NC NC VDDQ VDD VSS V DD VDDQ NC NC NC G NC NC DQ5 VDDQ VDD VSS V DD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS V DD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS V DD VDDQ NC DQ1 NC K NC NC NC VDDQ VDD VSS V DD VDDQ NC NC NC L NC DQ6 NC VDDQ VSS VSS V SS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS V SS VSS NC NC NC N NC NC NC VSS SA SA SA VSS NC NC NC P NC NC DQ7 SA SA C SA SA NC NC DQ8 R TDO TCK SA SA SA C SA SA SA TMS TDI 165-ball FBGA Pinout TOP VIEW NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address. 6.42 6 6431 tbl 12a IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Configuration IDT71P73804 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ V SS/ SA (2) SA R/W BW1 K NC LD SA Vss/ SA (1) CQ B NC DQ9 NC SA NC K BW0 SA NC NC DQ8 C NC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ V DD V SS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD V SS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ V SS V SS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS SA SA SA VSS NC NC NC P NC NC DQ17 SA SA C SA SA NC NC DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 165-ball FBGA Pinout TOP VIEW 6431 tbl 12b NOTES: 1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to VSS.on the 1M x 18 DDRII Burst of 4 (71P73804) devices. 2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 4 (71P73804) devices. 6.42 7 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Configuration IDT71P73604 (512K x 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (3) NC/ SA (1) R/W BW2 K BW1 LD SA VSS/ SA (2) CQ B NC DQ27 DQ18 SA BW3 K BW0 SA NC NC DQ8 C NC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10 P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 165-ball FBGA Pinout TOP VIEW NOTES: 1. A3 is reserved for the 36Mb expansion address 2. A10 is reserved for the 72Mb expansion address. 3. A2 is reserved for the 144Mb expansion address. 6.42 8 6431 tbl 12c IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Write Descriptions(1,2) BW0 BW1 BW2 BW3 NW0 NW1 Write Byte 0 L X X X X X Write Byte 1 X L X X X X Write Byte 2 X X L X X X Write Byte 3 X X X L X X Write Nibble 0 X X X X L X Write Nibble 1 X X X X X L Signal 6431 tbl 09 NOTES: 1) All byte write (BWx) and nibble write (NWx) signals are sampled on the rising edge of K and again on K. The data that is present on the data bus in the designated byte/nibble will be latched into the input if the corresponding BWx or NWx is held low. The rising edge of K will sample the first and third bytes/nibbles of the four word burst and the rising edge of K will sample the second and fourth bytes/nibbles of the four word burst. 2) The availability of the BWx or NWx on designated devices is described in the pin description table. 3) The DDRII Burst of four SRAM has data forwarding. A read request that is initiated on the cycle following a write request to the same address will produce the newly written data in response to the read request. Linear Burst Sequence Table (1,2) SA [1:0] a b c d 00 00 01 10 11 01 01 10 11 00 10 10 11 00 01 11 11 00 01 10 NOTES: 1. SA [1:0] is the address presented on pins SA1 and SA0 giving the burst sequence a,b,c,d. 2. SA0 and SA1 are only available on the x18 and x36-bit devices. 6.42 9 6431 tbl 22 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Application Example SRAM #1 SRAM #4 R=250 Ω R=250 Ω ZQ ZQ Vt SA LD R/W BW0 DQ BW1 C C K K DQ SA LD R/W BW0 BW1 C C K K R Vt Data Bus R Address R LD R/W BWx/NWx R R R MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK Vt Vt Vt R=50Ω Vt =VREF 6431 drw 20 6.42 10 Vt IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Absolute Maximum Ratings(1)(2) Capacitance (TA = +25°C, f = 1.0MHz)(1) Symbol Rating Value Unit V TERM Supply Voltage on VDD with Respect to GND –0.5 to +2.9 V V TERM Supply Voltage on V DDQ with Respect to GND –0.5 to VDD+0.3 V TERM Voltage on Input terminals with respect to GND –0.5 to VDD+0.3 V V TERM Voltage on Input, Output and I/O terminals with respect to GND –0.5 to VDDQ+0.3 V TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C IOUT Continuous Current into Outputs + 20 mA Symbol CIN CCLK V Recommended DC Operating and Temperature Conditions Parameter Min. Typ. Max. Unit VDD Power Supply Voltage 1.7 1.8 1.9 V VDDQ I/O Supply Voltage 1.4 1.5 1.9 V VSS Ground 0 0 0 V V REF Input Reference Voltage 0.68 V DDQ/2 0.95 V TA Ambient Temperature (1) 0 25 70 NOTE: 1. During production testing, the case temperature equals the ambient temperature. o Conditions Input Capacitance Clock Input Capacitance CO Output Capacitance CDQ DQ I/O Capacitance VDD = 1.8V VDDQ = 1.5V Max. Unit 5 pF 6 pF 7 pF 7 pF NOTE: 6431 tbl 06 1. Tested at characterization and retested after any design or process change that may affect these parameters. 6431 tbl 05 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation. Symbol Parameter c 6431 tbl 04 6.42 11 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V) Parameter Symbol Test Conditions Min Max Input Leakage Current llL VDD = Max VIN = VSS to VDDQ -2 +2 Output Leakage Current lOL Output Disabled -2 +2 250MHz - 800 IDD VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min 200MHz - 700 167MHz - 600 250MHz - 650 200MHz - 550 167MHz - 475 250MHz - 650 200MHz - 550 167MHz - 475 250MHz - 325 200MHz - 300 167MHz - 275 Operating Current (x36): DDR Operating Current (x18): DDR Operating Current (x9,x8): DDR Standby Current NOP IDD IDD ISB1 VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min Device Deselected (in NOP state), IOUT = 0mA (outputs open), f=Max, All inputs < 0.2V or > VDD -0.2V Unit Note mA 1 mA 1 mA 1 mA 2 Output High Voltage VOH1 RQ = 250Ω, IOH = -15mA VDDQ/2-0.12 VDDQ/2+0.12 V 3, 7 Output Low Voltage VOL1 RQ = 250Ω, IOL = 15mA VDDQ/2-0.12 VDDQ/2+0.12 V 4, 7 Output High Voltage VOH2 IOH = -0.1mA VDDQ-0.2 VDDQ V 5 Output Low Voltage VOL2 IOL = 0.1mA VSS 0.2 V 6 6431 tbl 10C NOTES: 1. Operating Current is measured at 100% bus utilization. 2. Standby Current is only after all pending read and write burst operations are completed. 3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance. 4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance. 5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point. 6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance measurement point. 7. Programmable Impedance Mode. 6.42 12 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V) Parameter Symbol Min Max Unit Notes Input High Voltage, DC V IH (DC) VREF +0.1 V DDQ +0.3 V 1,2 Input Low Voltage, DC V IL (DC) -0.3 VREF -0.1 V 1,3 Input High Voltage, AC VIH (AC) VREF +0.2 - V 4,5 Input Low Voltage, AC V IL (AC) - VREF -0.2 V 4,5 6431 tbl 10d NOTES: 1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width