IDT71V2559S85PF

128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter, Flow-Through Outputs IDT71V2557 IDT71V2559 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (±5%) 2.5V (±5%)I/O Supply (VDDQ) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) The IDT71V2557/59 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V2557/59 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip is deselected or a write is initiated. The IDT71V2557/59 have an on-chip burst counter. In the burst mode, the IDT71V2557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V2557/59 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). Description The IDT71V2557/59 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMs organized as 128K x 36 / 256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write. Pin Description Summary A0-A17 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 4878 tbl 01 ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. OCTOBER 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4878/05 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol Pin Function I/O Active Description A0-A17 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs re main unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. CE1, CE2 Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE 2 to enable the IDT71V2557/59. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71V2557/59. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation.. OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V2557/59. When OE is HIGH the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 2.5V I/O Supply. VSS Ground N/A N/A Ground. 4878 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Functional Block Diagram — 128K x 36 LBO Address A [0:16] 128K x 36 BIT MEMORY ARRAY D Q Address D Q Control CE1, CE2 CE2 R/W Input Register CEN ADV/LD BWx D DI Q DO Control Logic Clk Mux Clock Sel Gate OE Data I/O [0:31], I/O P[1:4] 4878 drw 01 6.42 3 , IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Functional Block Diagram — 256K x 18 LBO 256K x 18 BIT MEMORY ARRAY Address A [0:17] D Q Address D Q Control CE1, CE2 CE2 R/W Input Register CEN ADV/LD BWx DI D DO Control Logic Q Clk Mux Clock Sel Gate OE Data I/O [0:15], I/O P[1:2] 4878 drw 01a Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.135 3.3 3.465 V VDDQ I/O Supply Voltage 2.375 2.5 2.625 V VSS Ground 0 0 0 V 1.7 ____ VDD +0.3 1.7 ____ VIH VIH VIL Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage (1) -0.3 ____ VDDQ +0.3 (2) 0.7 NOTES: 1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle. V V V 4878 tbl 03 6.42 4 , IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Grade Temperature(1) VSS VDD V DDQ Commercial 0°C to +70°C 0V 3.3V±5% 2.5V±5% Industrial -40°C to +85°C 0V 3.3V±5% 2.5V±5% 4878 tbl 05 NOTE: 1. TA is the "instant on" case temperature. CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(3) NC(3) A8 A9 A6 A7 CE1 Pin Configuration — 128K x 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VSS(1) VDD VDD(2) VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 2 79 3 78 4 77 5 6 76 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VSS(1) VDD VSS(1,5) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 , 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO A5 A4 A3 A2 A1 A0 DNU(4) DNU(4) VSS VDD DNU(4) DNU(4) A10 A11 A12 A13 A14 A15 A16 4878 drw 02 Top View 100 TQFP NOTES: 1. Pins 14, 64, and 66 do not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH. 3. Pins 83 and 84 are reserved for future 8M and 16M respectively. 4. DNU = Do not use; Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK on future revisions. Within this current version, these pins are not connected. 5. On future revisions, Pin 64 will be used for ZZ (sleep mode). 6.42 5 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol CE2 NC NC BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(3) NC(3) A8 A9 A6 A7 CE1 Pin Configuration — 256K x 18 1 80 2 79 3 78 VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VSS(1) VDD VDD(2) VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC 4 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 24 58 57 25 56 26 55 27 54 28 53 29 A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS VSS(1) VDD VSS(1,5) I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO A5 A4 A3 A2 A1 A0 DNU(4) DNU(4) VSS VDD DNU(4) DNU(4) A11 A12 A13 A14 A15 A16 A17 4878 drw 02a Top View 100 TQFP NOTES: 1. Pins 14, 64, and 66 do not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH. 3. Pins 83 and 84 are reserved for future 8M and 16M respectively. 4. DNU = Do not use; Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK on future revisions. Within this current version, these pins are not connected. 5. On future revisions, pin 64 will be used for ZZ (sleep mode). 100 TQFP Capacitance (1) Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Terminal Voltage with Respect to GND -0.5 to +4.6 V VTERM(3,6) Terminal Voltage with Respect to GND -0.5 to VDD V VTERM(4,6) Terminal Voltage with Respect to GND -0.5 to VDD +0.5 V VTERM(5,6) Terminal Voltage with Respect to GND -0.5 to VDDQ +0.5 V Commercial Operating Temperature -0 to +70 o C Industrial Operating Temperature -40 to +85 o C TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -55 to +125 o C PT Power Dissipation 2.0 IOUT DC Output Current 50 TA CIN Input Capacitance CI/O I/O Capacitance W mA 4878 tbl 06 NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. TA is the "instant on" case temperature. , 1. Parameter(1) Conditions Max. Unit Symbol VIN = 3dV 5 pF CIN Input Capacitance VOUT = 3dV 7 pF CI/O I/O Capacitance 4878 tbl 07 (TA = +25°C, f = 1.0MHz) Parameter(1) (7) (TA = +25°C, f = 1.0MHz) 165 fBGA Capacitance(1) Symbol Unit 119 BGA Capacitance(1) (TA = +25°C, f = 1.0MHz) Symbol Commercial & Industrial Value VTERM(2) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC Rating Conditions Max. Unit VIN = 3dV TBD pF VOUT = 3dV TBD pF 4878 tbl 07b NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 6 Conditions Max. Unit V IN = 3dV 7 pF VOUT = 3dV 7 pF 4878 tbl 07a IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Pin Configuration — 128K x 36, 119 BGA 1 2 3 4 NC(3) ADV/LD A VDDQ A6 A4 B NC CE 2 A3 5 6 7 A8 A16 VDDQ A9 CE2 NC C NC A7 A2 VDD A12 A15 NC D I/O16 I/OP3 VSS NC VSS I/OP2 I/O15 E I/O17 I/O18 VSS CE1 VSS I/O13 I/O14 F VDDQ I/O19 VSS OE VSS I/O12 VDDQ G I/O20 I/O21 BW3 NC(3) BW 2 I/O11 I/O10 H I/O22 I/O23 VSS R/W VSS I/O9 I/O8 J VDDQ VDD VDD(2) VDD VSS(1) VDD VDDQ K I/O24 I/O26 VSS CLK VSS I/O6 I/O7 L I/O25 I/O27 BW4 NC BW1 I/O4 I/O5 M VDDQ I/O28 VSS CEN VSS I/O3 VDDQ N I/O29 I/O30 VSS A1 VSS I/O2 I/O1 P I/O31 I/OP4 VSS A0 VSS I/O0 I/OP1 R NC A5 LBO VDD A13 NC T NC NC A10 A11 A14 NC NC(5) VDDQ DNU(4) DNU(4) DNU(4) DNU(4) DNU(4) U VSS(1) VDDQ , 4878 drw 13A Top View Pin Configuration — 256K x 18, 119 BGA A 1 2 3 4 5 6 7 VDDQ A6 A4 NC(3) A8 A16 VDDQ ADV/LD A9 CE2 NC VDD A13 A17 NC B NC CE2 A3 C NC A7 A2 D I/O8 NC VSS NC VSS I/O7 NC E NC I/O9 VSS CE1 VSS NC I/O6 F VDDQ NC VSS OE VSS I/O5 VDDQ G NC I/O10 BW2 NC(3) VSS NC I/O4 H I/O11 NC VSS R/W VSS I/O3 NC J VDDQ VDD VDD(2) VDD VSS(1) VDD VDDQ K NC I/O12 VSS CLK VSS NC I/O2 L I/O13 NC VSS NC BW1 I/O1 NC M VDDQ I/O14 VSS CEN VSS NC VDDQ N I/O15 NC VSS A1 VSS I/O0 NC P NC I/OP2 VSS A0 VSS NC I/OP1 R NC A5 LBO VDD VSS(1) A12 NC T NC A10 A15 NC A14 A11 NC(5) U VDDQ DNU(4) DNU(4) DNU(4) DNU(4) DNU(4) VDDQ , 4878 drw 13B Top View NOTES: 1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL. 2. J3 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH. 3. G4 and A4 are reserved for future 8M and 16M respectively. 4. DNU = Do not use; Pins U2, U3, U4, U5 and U6 are reserved for respective JTAG Pins: TMS, TDI, TCK, TDO and TRST on future revisions. Within this current version, these pins are not connected. 5. On future revisions, Pin T7 will be used for ZZ (sleep mode). 6.42 7 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Pin Configuration — 128K x 36, 165 fBGA 1 A (3) NC 2 3 4 5 6 7 8 A7 CE1 BW3 BW2 CE2 CEN ADV/LD 9 10 11 (3) A8 NC (3) NC B NC A6 CE2 BW4 BW1 CLK R/W OE NC A9 NC(3) C I/OP3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2 D I/O17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14 E I/O19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12 F I/O21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10 G I/O23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9 I/O8 H VSS (1) (2) NC VDD VSS VSS VSS VDD NC NC NC(5) J I/O25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7 I/O6 K I/O27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5 I/O4 L I/O29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3 I/O2 M I/O31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1 I/O0 N I/OP4 NC VDDQ VSS DNU(4) NC VSS (1) VSS VDDQ NC I/OP1 P NC NC(3) A5 A2 DNU(4) A1 DNU(4) A10 A13 A14 NC R LBO NC(3) A4 A3 DNU(4) A0 DNU(4) A11 A12 A15 A16 VDD 4878 tbl 25 Pin Configuration - 256K x 18, 165 fBGA 1 A (3) NC 2 3 4 5 6 7 A7 CE1 8 BW2 NC CE2 CEN ADV/LD 9 10 11 (3) A8 A10 (3) NC B NC A6 CE2 NC BW1 CLK R/W OE NC A9 NC(3) C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1 D NC I/O8 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7 E NC I/O9 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6 F NC I/O10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5 G NC I/O11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4 NC VDD VSS VSS VSS VDD NC NC NC(5) H Vss (1) VDD J I/O12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3 NC K I/O13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2 NC L I/O14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1 NC M I/O15 NC VDDQ VDD VSS VSS VSS N I/OP2 (2) NC (3) VDDQ VSS (4) DNU (4) NC VSS VDD VDDQ I/O0 NC (1) VSS VDDQ NC NC (4) P NC NC A5 A2 DNU A1 DNU A11 A14 A15 NC R LBO NC(3) A4 A3 DNU(4) A0 DNU(4) A12 A13 A16 A17 4878 tbl 25a NOTES: 1. H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL. 2. H2 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH. 3. A9, B9, B11, A1, R2, and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively. 4. DNU = Do not use; Pins P5, P7, R5, R7 and N5 are reserved for respective JTAG Pins: TDI, TDO, TMS, TCK and TRST on future revisions. Within this current version, these pins are not connected. 5. On future revisions, pin H11 will be used for ZZ (sleep mode). 6.42 8 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table (1) CEN R/W CE1, CE2(5) ADV/LD BWx ADDRESS USED PREVIOUS CYCLE CURRENT CYCLE I/O (One cycle later) L L L L Valid External X LOAD WRITE D(7) L H L L X External X LOAD READ Q(7) L X X H Valid Internal LOAD WRITE / BURST WRITE BURST WRITE (Advance burst counter)(2) D(7) L X X H X Internal LOAD READ / BURST READ BURST READ (Advance burst counter)(2) Q(7) L X H L X X X DESELECT or STOP(3) HIZ L X X H X X DESELECT / NOOP NOOP HIZ H X X X X X X SUSPEND(4) Previous Value 4878 tbl 08 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state one cycle after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/ Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false. 6. Device Outputs are ensured to be in High-Z during device power-up. 7. Q - data read from the device, D - data written to the device. Partial Truth Table for Writes (1) R/W BW1 BW2 BW3(3) BW4(3) H X X X X L L L L L WRITE BYTE 1 (I/O[0:7], I/OP1) L L H H H WRITE BYTE 2 (I/O[8:15], I/OP2)(2) L H L H H WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3) L H H L H (2,3) WRITE BYTE 4 (I/O[24:31], I/OP4) L H H H L NO WRITE L H H H H OPERATION READ WRITE ALL BYTES (2) 4878 tbl 09 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Multiple bytes may be selected during the same cycle. 3. N/A for x18 configuration. Interleaved Burst Sequence Table (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 1 1 1 0 0 1 0 0 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. 6.42 9 4878 tbl 10 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 Fourth Address (1) 4878 tbl 11 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram (1) CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 A29 A30 A31 A32 A33 A34 A35 A36 A37 C29 C30 C31 C32 C33 C34 C35 C36 C37 D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35 D/Q36 CLOCK ADDRESS (A0 - A16) (2) CONTROL(2) (R/W, ADV/LD, BWx) (2) DATA I/O [0:31], I/O P[1:4] 4878 drw 03 NOTES: 1. This assumes CEN, CE1, CE2 and CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a delay from the rising edge of clock. 6.42 10 clock-to-data , IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselection NOOP Cycles(2) Cycle Address R/W ADV/LD CE1(1) CEN BWx OE I/O Comments n A0 H L L L X X D1 Load read n+1 X X H X L X L Q0 Burst read n+2 A1 H L L L X L Q0+1 Load read n+3 X X L H L X L Q1 Deselect or STOP n+4 X X H X L X X Z NOOP n+5 A2 H L L L X X Z Load read n+6 X X H X L X L Q2 Burst read n+7 X X L H L X L Q2+1 n+8 A3 L L L L L X Z Load write n+9 X X H X L L X D3 Burst write n+10 A4 L L L L L X D3+1 Load write n+11 X X L H L X X D4 Deselect or STOP n+12 X X H X L X X Z NOOP n+13 A5 L L L L L X Z Load write n+14 A6 H L L L X X D5 Load read n+15 A7 L L L L L L Q6 Load write n+16 X X H X L L X D7 Burst write n+17 A8 H L L L X X D7+1 Load read n+18 X X H X L X L Q8 Burst read n+19 A9 L L L L L L Q8+1 Load write Deselect or STOP NOTES: 1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 2. H = High; L = Low; X = Don't Care; Z = High Impedence. 6.42 11 4878 tbl 12 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Read Operation (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X X X L Q0 Contents of Address A0 Read Out NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 4878 tbl 13 Burst Read Operation (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X H X L X L Q0 Address A0 Read Out, Inc. Count n+2 X X H X L X L Q0+1 Address A0+1 Read Out, Inc. Count n+3 X X H X L X L Q0+2 Address A0+2 Read Out, Inc. Count n+4 X X H X L X L Q0+3 Address A0+3 Read Out, Load A1 n+5 A1 H L L L X L Q0 Address A0 Read Out, Inc. Count n+6 X X H X L X L Q1 Address A1 Read Out, Inc. Count n+7 A2 H L L L X L Q1+1 Address A1+1 Read Out, Load A2 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 4878 tbl 14 Write Operation (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X X X L X X D0 Write to Address A0 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Burst Write Operation 4878 tbl 15 (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X H X L L X D0 Address A0 Write, Inc. Count n+2 X X H X L L X D0+1 Address A0+1 Write, Inc. Count n+3 X X H X L L X D0+2 Address A0+2 Write, Inc. Count n+4 X X H X L L X D0+3 Address A0+3 Write, Load A1 n+5 A1 L L L L L X D0 Address A0 Write, Inc. Count n+6 X X H X L L X D1 Address A1 Write, Inc. Count n+7 A2 L L L L L X D1+1 Address A1+1 Write, Load A2 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 6.42 12 4878 tbl 16 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O Comments n A0 H L L L X X X AddressA0 and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X L Q0 Address A0 Read out, Load A1 n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+5 A2 H L L L X L Q1 Address A1 Read out, Load A 2 n+6 A3 H L L L X L Q2 Address A2 Read out, Load A 3 n+7 A4 H L L L X L Q3 Address A3 Read out, Load A 4 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 4878 tbl 17 Write Operation with Clock Enable Used (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O Comments n A0 L L L L L X X Address A0 and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A1 L L L L L X D0 Write data D0, Load A1. n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A2 L L L L L X D1 Write Data D1, Load A2 n+6 A3 L L L L L X D2 Write Data D2, Load A3 n+7 A4 L L L L L X D3 Write Data D3, Load A4 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 6.42 13 4878 tbl 18 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Read Operation With Chip Enable Used (1) Cycle Address R/W ADV/LD CE1(2) CEN BWx OE I/O(3) Comments n X X L H L X X ? Deselected. n+1 X X L H L X X Z Deselected. n+2 A0 H L L L X X Z Address A0 and Control meet setup. n+3 X X L H L X L Q0 Address A0 read out, Deselected. n+4 A1 H L L L X X Z Address A1 and Control meet setup. n+5 X X L H L X L Q1 Address A1 read out, Deselected. n+6 X X L H L X X Z Deselected. n+7 A2 H L L L X X Z Address A2 and Control meet setup. n+8 X X L H L X L Q2 Address A2 read out, Deselected. n+9 X X L H L X X Z Deselected. NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 3. Device outputs are ensured to be in High-Z during device power-up. 4878 tbl 19 Write Operation with Chip Enable Used (1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O(3) Comments n X X L H L X X ? Deselected. n+1 X X L H L X X Z Deselected. n+2 A0 L L L L L X Z Address A0 and Control meet setup n+3 X X L H L X X D0 Data D0 Write In, Deselected. n+4 A1 L L L L L X Z Address A1 and Control meet setup n+5 X X L H L X X D1 Data D1 Write In, Deselected. n+6 X X L H L X X Z Deselected. n+7 A2 L L L L L X Z Address A2 and Control meet setup n+8 X X L H L X X D2 Data D2 Write In, Deselected. n+9 X X L H L X X Z Deselected. NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 14 4878 tbl 20 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V +/-5%) Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VDD = Max., VIN = 0V to V DD ___ 5 µA |ILI| LBO Input Leakage Current(1) VDD = Max., VIN = 0V to V DD ___ 30 µA |ILO| Output Leakage Current VOUT = 0V to V CC ___ 5 µA IOL = +6mA, VDD = Min. ___ 0.4 V 2.0 ___ V VOL VOH Output Low Voltage Output High Voltage IOH = -6mA, VDD = Min. 4878 tbl 21 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%) 7.5ns Symbol Parameter Test Conditions 8ns 8.5ns Com'l Only Com'l Ind Com'l Ind Unit IDD Operating Power Supply Current Device Selected, Outputs Open, ADV/LD = X, VDD = Max., VIN > VIH or < VIL, f = fMAX(2) 275 250 260 225 235 mA ISB1 CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max., VIN > VHD or < VLD, f = 0(2,3) 40 40 45 40 45 mA ISB2 Clock Running Power Supply Current Device Deselected, Outputs Open, VDD = Max., VIN > VHD or < VLD, f = fMAX(2,3) 105 100 110 95 105 mA ISB3 Idle Power Supply Current Device Selected, Outputs Open, CEN > VIH, VDD = Max., VIN > VHD or < VLD, f = fMAX(2,3) 40 40 45 40 45 mA 4878 tbl 22 NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V. AC Test Loads AC Test Conditions (VDDQ = 2.5V) VDDQ/2 Input Pulse Levels 50Ω I/O Input Rise/Fall Times Z0 = 50Ω 4878 drw 04 6 , Figure 1. AC Test Load 5 0 to 2.5V 2ns Input Timing Reference Levels (VDDQ/2) Output Reference Levels (VDDQ/2) Output Load Figure 1 4878 tbl 23 4 ∆tCD 3 (Typical, ns) 2 , 1 20 30 50 80 100 Capacitance (pF) 200 4878 drw 05 Figure 2. Lumped Capacitive Load, Typical Derating 6.42 15 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) 8ns 7.5ns(5) Symbol Parameter 8.5ns Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 10 ____ 10.5 ____ 11 ____ ns tCH(1) Clock High Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns tCL(1) Clock Low Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns ____ 7.5 ____ 8 ____ 8.5 ns 2 ____ 2 ____ ns Output Parameters tCD Clock High to Valid Data tCDC Clock High to Data Change 2 ____ tCLZ(2,3,4) Clock High to Output Active 3 ____ 3 ____ 3 ____ ns tCHZ(2,3,4) Clock High to Data High-Z ____ 5 ____ 5 ____ 5 ns tOE Output Enable Access Time ____ 5 ____ 5 ____ 5 ns tOLZ(2,3) Output Enable Low to Data Active 0 ____ 0 ____ 0 ____ ns tOHZ(2,3) Output Enable High to Data High-Z ____ 5 ____ 5 ____ 5 ns Set Up Times tSE Clock Enable Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns tSA Address Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns 2.0 ____ 2.0 ____ 2.0 ____ ns 2.0 ____ 2.0 ____ ns 2.0 ____ 2.0 ____ ns ns tSD Data In Setup Time tSW Read/Write (R/W) Setup Time 2.0 ____ tSADV Advance/Load (ADV/LD) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ 2.0 ____ Byte Write Enable (BWx) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns Clock Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns tSC tSB Chip Enable/Select Setup Time Hold Times tHE tHA Address Hold Time 0.5 ____ tHD Data In Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHW Read/Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns ns tHADV Advance/Load (ADV/LD) Hold Time 0.5 ____ tHC Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ 0.5 ____ tHB Byte Write Enable (BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 4878 tbl 24 NOTES: 1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ. 2. Transition is measured ±200mV from steady-state. 3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V). 5. Commercial temperature range only. 6.42 16 6.42 17 tCLZ A1 tHA tHW tHE tSC tCD tHC A2 tSA tSW Q(A1) Read tSADV tSE Read Q(A2) tCDC tHADV tCH Q(A2+1) tCD tCL Burst Read Q(A2+2) Q(A2+3) (CEN high, eliminates current L-H clock edge) tCDC Q(A2+3) Q(A2) (Burst Wraps around to initial state) tCHZ NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. DATAOUT OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 4878 drw 06 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle (1,2,3,4) , 6.42 18 B(A1) A1 Write tSADV tHW tHE tHC D(A1) tSD tHD tHB B(A2) tSB tSC tHA A2 tSA tSW tSE Write D(A2) B(A2+1) tHADV tCH tHD D(A2+1) tSD B(A2+2) tCL (CEN high, eliminates current L-H clock edge) Burst Write D(A2+2) B(A2+3) D(A2+3) (Burst Wraps around to initial state) B(A2) D(A2) 4878 drw 07 NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. DATAIN BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycles (1,2,3,4,5) , 6.42 19 A1 tCD tHW tHE tHC tCHZ tHB B(A2) tSB tSC tHA A2 tSA tSW Q(A1) Read tSADV tSE Write A3 tCLZ D(A2) tSD tHD tHADV tCH Read Q(A3) tCDC B(A4) A4 tCL Write D(A4) B(A5) A5 Write D(A5) A6 Read Q(A6) A7 Read Q(A7) B(A8) A8 D(A8) A9 4878 drw 08 Write NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Combined Read and Write Cycles (1,2,3) , 6.42 20 tCD tCLZ A1 Q(A1) tSE tSADV tHE tHA tHW tHC Q(A1) tCDC tCHZ tHB B(A2) tSB tSC A2 tSA tSW tCH tHADV tCL tCD D(A2) tSD tHD A3 Q(A3) tCDC A4 A5 4878 drw 09 Q(A4) , NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of CEN Operation (1,2,3,4) 6.42 21 tCD tCLZ A1 tSADV tSC Q(A1) tHW tHE tHC tHA A2 tSA tSW tSE tCHZ tCDC Q(A2) tHADV tCH tHB B(A3) tSB A3 tCL D(A3) tSD tHD A4 Q(A4) A5 4878 drw 10 Q(A5) NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of CS Operation (1,2,3,4) , IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline 6.42 22 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 119 Ball Grid Array (BGA) Package Diagram Outline 6.42 23 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline 6.42 24 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation (1) OE tOE tOHZ tOLZ Q DATA Out Q , 4878 drw 11 NOTE: 1. A read operation is assumed to be in progress. Ordering Information IDT XXXX S XX XX X Device Type Power Speed Package Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF BG BQ 100-pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA) 75* 80 85 Access time (tCD) in tenths of nanoseconds , IDT71V2557 128Kx36 Flow-Through ZBT SRAM with 2.5V I/O IDT71V2559 256Kx18 Flow-Through ZBT SRAM with 2.5V I/O * Commercial temperature range only. 4878 drw 12 6.42 25 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 6/30/99 8/23/99 12/31/99 05/02/00 Pg. 5, 6 Pg. 7 Pg. 15 Pg. 21 Pg. 23 Pg. 5, 14, 15, 22 Pg. 5,6 Pg. 5,6,7 Pg. 6 Pg. 21 05/26/00 07/26/00 Pg. 23 Pg. 5-7 Pg. 8 Pg. 23 10/25/00 Pg. 8 Updated to new format Added Pin 64 to Note 1 and changed Pins 38, 42, and 43 to DNU Changed U2–U6 to DNU Improved tCH, tCL; revised tCLZ Added BGA package diagrams Added Datasheet Document History Added Industrial Temperature Range offerings Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Clarify note to TQFP and BGA pin configuration; corrected typo in pinout Add BGA capacitance Add TQFP Package Diagram Outline Add new package offering, 13 x 15mm 165 fBGA Correct 119 BGA Package Diagram Outline Add ZZ, sleep mode reference note to TQFP, BG119, and BQ 165 pinouts Update BQ165 pinout Update BG119 package diagram dimensions Remove Preliminary Status Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 26 for Tech Support: sramhelp@idt.com 800-544-7726, x4033