128K X 36
3.3V Synchronous SRAMs
2.5V I/O, Pipelined Outputs,
Burst Counter, Single Cycle Deselect
Features
◆
◆
◆
◆
128K x 36 memory configuration
Supports high system speed:
Commercial and Industrial:
– 200MHz 3.1ns clock access time
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆
◆
◆
◆
◆
◆
71V25761S
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP)
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see Ordering Information
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
Burst
Logic
Q0
CLR
ADSP
Q1
A0 - A16/17
GW
BWE
128K x 36
BIT
MEMORY
ARRAY
17/18
A0*
A1*
2
CLK EN
ADDRESS
REGISTER
INTERNAL
ADDRESS
Burst
Sequence
CEN
A0,A1
A2 - A17
36
17/18
Byte 1
Write Register
36
Byte 1
Write Driver
BW1
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
9
Byte 3
Write Register
Byte 3
Write Driver
BW3
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
9
OUTPUT
REGISTER
CE
CS0
CS1
D
Q
Enable
Register
DATA
INPUT
REGISTER
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OE
I/O0 — I/O31
I/OP1 — I/OP4
OUTPUT
BUFFER
36
5297 drw 01
1
Jul.27. 20
,
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Description
The IDT71V25761 are high-speed SRAMs organized as 128K x 36.
The IDT71V25761 SRAMs contain write, data, address and control
registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V25761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
Commercial and Industrial Temperature Ranges
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V25761 SRAMs utilizes a high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin
plastic quad flatpack (TQFP).
Pin Description Summary
A0-A17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
5297 tbl 01
6.42
2
Jul.27. 20
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and
ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte write
causes all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V25761/781. CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected. When
LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the
device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is
also selected. When OE is HIGH the I/O pins are in a high-impedance state.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V25761/781 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
V DD
Power Supply
N/A
N/A
3.3V core power supply.
V DDQ
Power Supply
N/A
N/A
2.5V I/O Supply.
V SS
Ground
N/A
N/A
Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
Jul.27.20
5297 tbl 02
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
– 128K x 36, PKG100
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration
(3)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD/NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
4
77
5
6
76
75
7
74
8
73
9
72
71
10
11
12
13
71V25761
PKG100
70
69
68
14
67
15
66
16
65
17
64
18
19
63
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
53
28
29
52
51
30
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
5297 drw 02a
100 TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
3. This text does not indicate orientation of actual part-marking.
6.42
4
Jul.27. 20
,
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Absolute Maximum Ratings(1)
Symbol
(2)
Rating
Recommended Operating
Temperature and Supply Voltage
Commercial &
Industrial
Unit
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
(4,6)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
Operating Temperature
-0 to +70
o
Industrial
Operating Temperature
-40 to +85
o
C
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-55 to +125
o
C
PT
Power Dissipation
2.0
W
IOUT
DC Output Current
50
mA
TA
(7)
Commercial and Industrial Temperature Ranges
C
CIN
Input Capacitance
CI/O
I/O Capacitance
Unit
VIN = 3dV
5
pF
VOUT = 3dV
7
pF
5297 tbl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
5
Jul.27.20
VDDQ
Commercial
0°C to +70°C
0V
3.3V±5%
2.5V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
2.5V±5%
5297 tbl 04
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDQ
I/O Supply Voltage
2.375
2.5
2.625
V
VSS
Supply Voltage
0
0
0
V
VIH
Input High Voltage Inputs
1.7
____
VDD
+0.3
V
VIH
Input High Voltage - I/O
1.7
____
VDDQ
+0.3(1)
V
VIL
Input Low Voltage
-0.3(2)
____
0.7
V
5297 tbl 05
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
(TA = +25°C, f = 1.0MHz)
Max.
VDD
Symbol
100 pin TQFP Capacitance
Conditions
VSS
Recommended DC Operating
Conditions
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Parameter(1)
Temperature(1)
NOTES:
1. TA is the "instant on" case temperature.
5297 tbl 03
Symbol
Grade
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5
µA
|ILZZ|
ZZ and LBO Input Leakage Current(1)
VDD = Max., VIN = 0V to VDD
___
30
µA
|ILO|
Output Leakage Current
VOUT = 0V to VDDQ, Device Deselected
___
5
µA
VOL
Output Low Voltage
IOL = +6mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -6mA, VDD = Min.
2.0
___
V
5297 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
200MHz
Symbol
Parameter
Test Conditions
183MHz
166MHz
Com'l Only
Com'l
Ind
Com'l
Ind
Unit
IDD
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
360
340
350
320
330
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
30
35
30
35
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)
130
120
130
110
120
mA
IZZ
Full Sleep Mode Supply
Current
ZZ > VHD, VDD = Max.
30
30
35
30
35
mA
5297 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
(VDDQ = 2.5V)
Input Pulse Levels
Input Rise/Fall Times
0 to 2.5V
(VDDQ/2)
Output Timing Reference Levels
(VDDQ/2)
AC Test Load
I/O
2ns
Input Timing Reference Levels
VDDQ/2
50Ω
Z0 = 50Ω
5297 drw 06
,
Figure 1. AC Test Load
6
See Figure 1
5
5297 tbl 10
4
ΔtCD 3
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
5297 drw 07
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
6
Jul.27. 20
,
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,3)
Address
Used
CE
CS0
CS 1
ADSP
ADSC
ADV
GW
BWE
BWx
OE
(2)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
-
HI-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
-
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
-
HI-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
-
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
-
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
-
HI-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
-
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
-
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
-
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
-
HI-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
-
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
-
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
-
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
-
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
-
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
-
HI-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
-
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
-
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
-
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
-
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
-
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
-
HI-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
-
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
-
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
-
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
-
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
-
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
-
HI-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
-
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
-
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
-
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
-
Operation
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
7
Jul.27.20
DIN
5297 tbl 11
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
(3)
H
L
L
H
H
H
(3)
Write Byte 2
H
L
H
L
H
H
Write Byte 3(3)
H
L
H
H
L
H
(3)
H
L
H
H
H
L
Write Byte 1
Write Byte 4
5297 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
Operation(2)
5297 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
5297 tbl 14
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
0
0
0
1
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
8
Jul.27. 20
5297 tbl 15
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
183MHz
200MHz(5)
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
5
____
5.5
____
6
____
ns
(1)
tCH
Clock High Pulse Width
2
____
2.2
____
2.4
____
ns
tCL(1)
Clock Low Pulse Width
2
____
2.2
____
2.4
____
ns
tCYC
Parameter
166MHz
Output Parameters
tCD
Clock High to Valid Data
____
3.1
____
3.3
____
3.5
ns
tCDC
Clock High to Data Change
1.0
____
1.0
____
1.0
____
ns
tCLZ
Clock High to Output Active
0
____
0
____
0
____
ns
tCHZ(2)
Clock High to Data High-Z
1.5
3.1
1.5
3.3
1.5
3.5
ns
tOE
Output Enable Access Time
____
3.1
____
3.3
____
3.5
ns
0
____
0
____
0
____
ns
____
3.1
____
3.3
____
3.5
ns
(2)
(2)
tOLZ
Output Enable Low to Output Active
tOHZ(2)
Output Enable High to Output High-Z
Set Up Times
tSA
Address Setup Time
1.2
____
1.5
____
1.5
____
ns
tSS
Address Status Setup Time
1.2
____
1.5
____
1.5
____
ns
tSD
Data In Setup Time
1.2
____
1.5
____
1.5
____
ns
tSW
Write Setup Time
1.2
____
1.5
____
1.5
____
ns
tSAV
Address Advance Setup Time
1.2
____
1.5
____
1.5
____
ns
tSC
Chip Enable/Select Setup Time
1.2
____
1.5
____
1.5
____
ns
Hold Times
tHA
Address Hold Time
0.4
____
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.4
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.4
____
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.4
____
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.4
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.4
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
100
____
ns
tCFG (4)
Configuration Set-up Time
20
____
22
____
24
____
ns
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.42
9
Jul.27.20
4876 tbl 16
Jul.27. 20
6.42
10
Output
Disabled
tSC
tSA
tSS
tHS
Ax
Pipelined
Read
tOLZ
tOE
tHC
tHA
O1(Ax)
Ay
(1)
tCH
tCLZ
tOHZ
tCD
tSW
tCL
tSAV
O1(Ay)
tCDC
tHAV
O2(Ay)
tHW
Burst Pipelined Read
O3(Ay)
ADV HIGH suspends
burst
O4(Ay)
(Burst wraps around
to its initial state)
O1(Ay)
tCHZ
O2(Ay)
,
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW,BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
5297 drw 08
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipeline Read Cycle(1,2)
Jul.27.20
6.42
11
tSA
tHA
tSS
tHS
tCLZ
tCD
Single Read
Ax
(2)
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Pipelined
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tOLZ
tCD
O2(Az)
Pipelined Burst Read
O1(Az)
tCDC
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az;
O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO
input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
5297 drw 09
O3(Az)
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
,
Jul.27. 20
6.42
12
O4(Aw)
Ax
Burst Read
tHC
O3(Aw)
tSC
tSA
tHA
tSS
tHS
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
I2(Ay)
Burst Write
I2(Ay)
(ADV HIGH suspends burst)
tSAV
GW is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
tCH
.
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the
external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
I3(Az)
5297 drw 10
Burst Write
I2(Az)
tHD
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
,
Jul.27.20
6.42
13
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
Burst Write
I2(Ay)
(ADV suspends burst)
BWx is ignored when ADSP initiates a cycle and is sampled on next clock rising edge
BWE is ignored when ADSP initiates a cycle and is sampled on next clock rising edge
tCH
I2(Ay)
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the
external address Ay; I2 (Ay) represent the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by
the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
5297 drw 11
I3(Az)
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
,
Jul.27. 20
6.42
14
tSS
tSC
tSA
tHS
Ax
Single Read
tOLZ
tOE
tHC
tHA
O1(Ax)
tCH
tCL
tZZPW
Snooze Mode
tZZR
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
5297 drw 12
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
DATAOUT
(Aw)
(Ax)
(Ay)
,
5297 drw 14
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
,
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
15
Jul.27.20
5297 drw 15
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
X
XXXX
S
X
XX
Device
Type
Power
Speed
Package
X
X
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
PF
100-pin Plastic Thin Quad Flatpack (PKG100)
200
183
166
Frequency in Megahertz
S
Standard Power
71V25761
128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/O
5297 drw 13
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
Orderable Part Information
Pkg.
Code
Pkg.
Type
Temp.
Grade
71V25761S166PFG
PKG100
TQFP
C
71V25761S166PFG8
PKG100
TQFP
C
Speed
(MHz)
166
183
200
Orderable Part ID
71V25761S166PFGI
PKG100
TQFP
I
71V25761S166PFGI8
PKG100
TQFP
I
71V25761S183PFG
PKG100
TQFP
C
71V25761S183PFG8
PKG100
TQFP
C
71V25761S183PFGI
PKG100
TQFP
I
71V25761S183PFGI8
PKG100
TQFP
I
71V25761S200PFG
PKG100
TQFP
C
71V25761S200PFG8
PKG100
TQFP
C
71V25761S200PFGI
PKG100
TQFP
I
71V25761S200PFGI8
PKG100
TQFP
I
6.42
16
Jul.27. 20
71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
04/04/00
06/01/00
07/15/00
10/25/00
04/22/03
06/30/03
03/13/09
05/27/10
07/24/14
07/27/20
Created new datasheet from 71V2576 and 71V2578 datasheets
Added Industrial Temperature range offerings
Added 100pin TQFP Package Diagram Outline
Add capacitance table for BGA package; Add Industrial temperature to table; Insert note to Absolute
Max Ratings and Recommended Operating Temperature tables
Add new package offering, 13 x 15mm 165 fBGA
Pg. 20
Correct BG119 Package Diagram Outline
Pg. 7
Add note reference to BG119 pinout
Pg. 8
Add DNU note to BQ165 pinout
Pg. 20
Update BG119 Package Diagram Outline Dimensions
Remove Preliminary from datasheet
Pg. 8
Add reference note to pin N5 in BQ165 pinout, reserved for JTAG, TRST
Pg.4
Updated 165 BGA table information from TBD to 7
Pg. 1,2,3,5-9
Updated datasheet with JTAG information
Pg. 5-8
Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiring NC or connection to Vss.
Pg. 19,20
Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions
Pg. 21-23
Removed old package information from the datasheet
Pg. 24
Updated ordering information with JTAG and Y stepping information. Added information
regarding packages available IDT website.
Pg.21
Removed "IDT" from orderable part number
Pg.20
Added "Restricted hazardous substance device" to the ordering information
Pg.1-20
Removed IDT71V25781S/SA from datasheet.
Pg. 20
Updated Ordering Information changed indicator from "Restricted hazardous substance
device" to"Green" and added Tape & Reel
Pg. 1-18
Rebranded as Renesas datasheet
Pg.1 &16
Deleted Y die stepping from part number and Ordering Information
Pg. 1&16
Added Industrial temp range and Green to Features and Ordering Information
Pg. 1-3,6,14 &15 Removed JTAG information
Pg. 1-3,6, 7 & 16 Deleted obsolete119BGA Ball Grid Array and 165fBGA fine pitch Ball Grid Array information
Pg. 5
Updated package code
Pg. 16
Added Orderable Part Information table
Pg. 1, 4, 8, 19
Pg. 18
Pg. 4
6.42
17
Jul.27.20
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