IDT71V424YL10PH

71V424S 71V424L 3.3V CMOS Static RAM 4 Meg (512K x 8-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description 512K x 8 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times — Commercial and Industrial: 10/12/15ns Single 3.3V power supply One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 36-pin, 400 mil plastic SOJ package and 44-pin, 400 mil TSOP. Industrial temperature range (–40°C to +85°C) is available for selected speeds The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized as 512K x 8. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71V424 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44pin, 400 mil TSOP. Functional Block Diagram A0 A18 • • • • • • ADDRESS DECODER 8 8 I/O0 - I/O7 4,194,304-BIT MEMORY ARRAY I/O CONTROL 8 WE OE CS CONTROL LOGIC 3622 drw 01 1 May.04.21 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Pin Configurations (1) A0 A1 A2 A3 A4 CS I/O0 I/O1 VDD VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 71V424 PBG36 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 SOJ Top View NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VDD I/O5 I/O4 A14 A13 A12 A11 A10 NC 3622 drw 02 NOTE: 1. This text does not indicate orientation of actual part-marking. NC 1 44 NC NC 2 43 NC A0 3 A1 A2 4 42 41 NC A18 5 40 A17 A3 6 39 A16 A4 7 38 A15 CS 8 37 OE I/00 9 36 I/07 35 I/06 34 VSS I/01 10 VDD 11 VSS 12 33 VDD I/02 13 32 I/05 I/03 14 31 I/04 WE 15 30 A14 A5 A6 16 29 A13 17 28 A12 A7 18 27 A11 A8 19 26 A10 A9 20 25 NC NC 21 24 NC NC 22 23 NC 71V424 PHG44 TSOP Top View Pin Description Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) A0 – A18 Address Inputs Input CS Chip Select Input Symbol WE Write Enable Input CIN Input Capacitance OE Output Enable Input CI/O I/O Capacitance I/O0 - I/O7 Data Input/Output VDD 3.3V Power VSS Ground Parameter(1) Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 8 pF 3622 tbl 03 I/O NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. Power Gnd 3622 tbl 02 Truth Table(1,2) CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled X X High-Z Deselected - Standby (I SB) X X High-Z Deselected - Standby (I SB1 ) H VHC (3) NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VDD -0.2V. 3. Other inputs ≥VHC or ≤VLC. 6.42 2 May.04.21 3622 drw 11 Function 3622 tbl 01 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Absolute Maximum Ratings(1) Symbol Rating Value Unit VDD Supply Voltage Relative to VSS -0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to VSS -0.5 to VDD+0.5 V TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 1 W IOUT DC Output Current 50 mA Grade Temperature VSS VDD Commercial 0°C to +70°C 0V See Below Industrial –40°C to +85°C 0V See Below 3622 tbl 05 C Recommended DC Operating Conditions C Symbol 3622 tbl 04 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 VDD Supply Voltage VSS Ground VIH Input High Voltage 2.0 ____ VIL Input Low Voltage -0.3(2) ____ V VDD+0.3 V (1) 0.8 V 3622 tbl 06 NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71V424 Symbol Parameter Test Condition Min. Max. Unit |ILI| Input Leakage Current VDD = Max., VIN = VSS to VDD ___ 5 µA |ILO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___ 5 µA VOL Output Low Voltage IOL = 8mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = -4mA, VDD = Min. 2.4 ___ V 3622 tbl 07 DC Electrical Characteristics(1, 2, 3) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V424S/L 10 Symbol Parameter ICC Dynamic Operating Current CS < VLC, Outputs Open, V DD = Max., f = fMAX(4) ISB ISB1 71V424S/L 12 71V424S/L 15 Unit Com'l. Ind. Com'l. Ind. Com'l. Ind. S 180 180 170 170 160 160 mA L 165 165 155 155 145 145 mA Dynamic Standby Power Supply Current CS > VHC, Outputs Open, V DD = Max., f = fMAX(4) S 60 60 55 55 50 50 mA L 55 55 50 50 45 45 mA Full Standby Power Supply Current (static) CS > VHC, Outputs Open, V DD = Max., f = 0(4) S 20 20 20 20 20 20 mA L 10 10 10 10 10 10 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High). 3. Power specifications are preliminary. 4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 6.42 3 May.04.21 mA 3622 tbl 08 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figure 1, 2 and 3 3622 tbl 09 AC Test Loads +1.5V 3.3V 50Ω I/O 320Ω Z0 = 50Ω DATA OUT 30pF 5pF* 350Ω 3622 drw 03 3622 drw 04 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 7 • 6 ΔtAA, tACS (Typical, ns) 5 4 • 3 • 2 • 1 • • 8 20 • 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) Figure 3. Output Capacitive Derating 6.42 4 May.04.21 3622 drw 05 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 3.3V ± 10%, Commercial and Industrial Temperature Ranges) 71V424S/L10 Symbol Parameter 71V424S/L12 71V424S/L15 Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ns 4 ____ 4 ____ 4 ____ ns (1) tCLZ Chip Select to Output in Low-Z tCHZ(1) Chip Deselect to Output in High-Z ____ 5 ____ 6 ____ 7 ns tOE Output Enable to Output Valid ____ 5 ____ 6 ____ 7 ns tOLZ(1) Output Enable to Output in Low-Z 0 ____ 0 ____ 0 ____ ns tOHZ(1) Output Disable to Output in High-Z ____ 5 ____ 6 ____ 7 ns tOH Output Hold from Address Change 4 ____ 4 ____ 4 ____ ns tPU(1) Chip Select to Power Up Time 0 ____ 0 ____ 0 ____ ns Chip Deselect to Power Down Time ____ 10 ____ 12 ____ 15 ns tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tAW Address Valid to End of Write 8 ____ 8 ____ 10 ____ ns tCW Chip Select to End of Write 8 ____ 8 ____ 10 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 8 ____ 8 ____ 10 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End of Write 6 ____ 6 ____ 7 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tOW(1) Output Active from End of Write 3 ____ 3 ____ 3 ____ ns tWHZ(1) Write Enable to Output in High-Z ____ 6 ____ 7 ____ 7 ns (1) tPD WRITE CYCLE 3622 tbl 10 NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 6.42 5 May.04.21 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ CS tCLZ DATAOUT VCC SUPPLY ICC CURRENT ISB (5) (5) tACS (3) tCHZ HIGH IMPEDANCE (5) tOHZ (5) DATAOUT VALID tPD tPU 3622 drw 06 Timing Waveform of Read Cycle No. 2(1, 2, 4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 3622 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 6 May.04.21 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4) tWC ADDRESS tAW CS tWR tAS tWP WE tWHZ DATAOUT (2) (5) tOW HIGH IMPEDANCE (3) (3) tDH tDW DATAIN tCHZ (5) (5) DATAIN VALID 3622 drw 08 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4) tWC ADDRESS tAW CS tAS tCW tWR WE tDW tDH DATAIN VALID DATAIN 3622 drw 09 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6.42 7 May.04.21 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Ordering Information 71V424 X XX XXX Device Type Power Speed Package X X X Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (–40°C to +85°C) G Green Y PH 36-pin 400 mil SOJ (PBG36) 44-pin TSOP Type II (PHG44) 10 12 15 Speed in nanoseconds S L Standard Power Low Power NOTE: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 6.42 8 May.04.21 3622 drw 10 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Orderable Part Information Speed (ns) 10 12 15 Orderable Part ID 71V424L10PHG Pkg. Code Pkg. Type Temp. Grade Speed (ns) PHG44 TSOP C 10 Pkg. Code Pkg. Type Temp. Grade 71V424S10PHG PHG44 TSOP C PHG44 TSOP C Orderable Part ID 71V424L10PHG8 PHG44 TSOP C 71V424S10PHG8 71V424L10PHGI PHG44 TSOP I 71V424S10PHGI PHG44 TSOP I 71V424L10PHGI8 PHG44 TSOP I 71V424S10PHGI8 PHG44 TSOP I 71V424L10YG PBG36 SOJ C 71V424S10YG PBG36 SOJ C 71V424L10YG8 PBG36 SOJ C 71V424S10YG8 PBG36 SOJ C 71V424L10YGI PBG36 SOJ I 71V424S10YGI PBG36 SOJ I 71V424L10YGI8 PBG36 SOJ I 71V424S10YGI8 PBG36 SOJ I 71V424L12PHG PHG44 TSOP C 71V424S12PHG PHG44 TSOP C 71V424L12PHG8 PHG44 TSOP C 71V424S12PHG8 PHG44 TSOP C 71V424L12PHGI PHG44 TSOP I 71V424S12PHGI PHG44 TSOP I 71V424L12PHGI8 PHG44 TSOP I 71V424S12PHGI8 PHG44 TSOP I PBG36 SOJ C 12 71V424L12YG PBG36 SOJ C 71V424S12YG 71V424L12YG8 PBG36 SOJ C 71V424S12YG8 PBG36 SOJ C 71V424L12YGI PBG36 SOJ I 71V424S12YGI PBG36 SOJ I 71V424S12YGI8 PBG36 SOJ I 71V424S15PHG PHG44 TSOP C C 71V424S15PHG8 PHG44 TSOP C I 71V424S15PHGI PHG44 TSOP I PHG44 TSOP I 71V424L12YGI8 PBG36 SOJ I 71V424L15PHG PHG44 TSOP C 71V424L15PHG8 PHG44 TSOP 71V424L15PHGI PHG44 TSOP 15 71V424L15PHGI8 PHG44 TSOP I 71V424S15PHGI8 71V424L15YG PBG36 SOJ C 71V424S15YG PBG36 SOJ C 71V424L15YG8 PBG36 SOJ C 71V424S15YG8 PBG36 SOJ C 71V424L15YGI PBG36 SOJ I 71V424S15YGI PBG36 SOJ I I 71V424S15YGI8 PBG36 SOJ I 71V424L15YGI8 PBG36 SOJ 6.42 9 May.04.21 71V424S, 71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Datasheet Document History 8/13/99 Pg. 2 Pg. 7 8/31/99 11/22/02 07/31/03 07/28/04 Pg. 9 Pg. 1–9 Pg. 8 Pg. 8 Pg. 3 09/20/08 Pg. 8 Pg. 1, 8 05/12/09 06/11/09 09/26/13: Pg. 3,5,8 Pg.1,8 Pg.1-9 Pg.1 Pg.8 05/04/21 Pg.1-11 Pg.2 & 8 Pg.8 Pg.9 Updated to new format Removed SO44-1 from TSOP pinout Revised footnotes on Write Cycle No. 1 diagram Removed footnote for tWR on Write Cycle No. 2 diagram Added Datasheet Document History Added Industrial temperature range offerings Added die revision option to ordering information Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y. Increased ISB for all "L" and S15 speeds by 10mA and increased for S12 speed by 5mA (refer to PCN# SR-0402-02). Added "Restricted hazardous substance device" to the ordering information. Added Y and V step part numbers to front page and ordering information. Updated the ordering information by removing the “IDT” notation. Add Industrial grade for 10ns Low Power. Removed VS, VL from datasheet and ordering information. Removed the /YS & /YL from the device name for the entire datasheet. Removed IDT's reference to fabrication. Updated ordering information by adding T&R, updated Restricted Hazardous Substance Device wording to Green and removed the Die Stepping Revision, the”Y” designator. Rebranded as Renesas datasheet Updated package codes Added Industrial temp footnote to Ordering Information Added Orderable Part Information tables 6.42 10 May.04.21 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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