32K x 32 CacheRAM™
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
Features
◆
◆
◆
◆
◆
32K x 32 memory configuration
Supports high-performance system speed:
Commercial and Industrial:
— 5ns Clock-to-Data Access (100MHz)
— 6ns Clock-to-Data Access (83MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
◆
◆
◆
◆
IDT71V432
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW),
byte write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular
plastic thin quad flatpack (TQFP)
Green parts available, see ordering information
Functional Block Diagram
LBO
ADV
CLK
Burst
Logic
15
CLK EN
ADDRESS
REGISTER
32K x 32
BIT
MEMORY
ARRAY
15
A0*
CLR
ADSP
A0–A14
GW
BWE
2
Binary
Counter
ADSC
INTERNAL
ADDRESS
Burst
Sequence
CE
A1*
A0, A1
2
.
A2–A14
32
32
15
Byte 1
Write Register
Byte 1
Write Driver
BW1
8
Byte 2
Write Register
Byte 2
Write Driver
BW2
8
Byte 3
Write Register
Byte 3
Write Driver
BW3
8
Byte 4
Write Register
Byte 4
Write Driver
BW4
8
OUTPUT
REGISTER
CE
Q
Enable
Register
D
CS0
CS1
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OUTPUT
BUFFER
OE
32
I/O0–I/O31
3104 drw 01
OCTOBER 2014
1
©2014 Integrated Device Technology, Inc.
DSC-3104/08
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit
CacheRAM organized as 32K x 32 with full support of the
Pentium™ and PowerPC™ processor interfaces. The pipelined
burst architecture provides cost-effective 3-1-1-1 secondary
cache performance for processors up to 100 MHz.
The IDT71V432 CacheRAM contains write, data, address,
and control registers. Internal logic allows the CacheRAM to
generate a self-timed write based upon a decision which can be
left until the extreme end of the write cycle.
The burst mode feature offers the highest level of performance to the system designer, as the IDT71V432 can provide
four cycles of data for a single address presented to the
Commercial and Industrial Temperature Ranges
CacheRAM. An internal burst address counter accepts the first
cycle address from the processor, initiating the access sequence.
The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of
output data will be available to the user on the next three rising
clock edges. The order of these three addresses will be defined
by the internal burst counter and the LBO input pin.
The IDT71V432 CacheRAM utilizes high-performance, highvolume 3.3V CMOS process, and is packaged in a JEDEC
Standard 14mm x 20mm 100-pin thin plastic quad flatpack
(TQFP) for optimum board density in both desktop and notebook
applications.
Pin Description Summary
A0–A14
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chips Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0–I/O31
Data Input/Output
I/O
Synchronous
VDD
3.3V Power
Power
DC
VSS
Ground
Ground
DC
3104 tbl 01
CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
6.42
2
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
A0–A14
Description
Address Inputs
I
N/A
Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Sy nchronous Ad dress Status from Cache Controller. ADSC is an active LOW
input that is used to load the address registers with new addresses. ADSC is
NOT GATED by CE.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is
used to load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to
advance the internal burst counter, co ntrolling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1–BW4. If BWE is
LOW at the rising edge of CLK then BWX inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
BW1 - BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8),
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW1–BW4 must meet specified setup and hold times
with respect to CLK.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS 0 and CS1 to enable the
IDT71V432. CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input to the IDT71V432. All timing referenc es for the device are
made with respect to this input.
CS0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable
the chip.
CS1
Chip Select 1
I
LOW
Sy nchronous active LOW chip select. CS1 is used with CE and CS0 to enable
the chip.
GW
Global Write Enable
I
LOW
I/O0–I/O31
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Asynchronous burst order sele ction DC input. When LBO is HIGH the Interleaved
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
sequence is selected. LBO is a static DC input and must not change state while
the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are
enabled on the I/O pins. OE is gated internally by a delay circuit driven by CE,
CS0, and CS1. In dual-bank mode, when the user is utilizing two banks of
IDT71V432 and toggling back and forth between them using CE, the internal
de lay circuit delays the OE activation of the data output drivers by one cycle to
prevent bus contention between the banks. When used in single bank mode CE,
CS0, and CS1 are all tied active and there is no output enable delay. When OE is
HIGH the I/O pins are in a high-impedence state.
VDD
Power Supply
N/A
N/A
3.3V power supply inputs.
VSS
Ground
N/A
N/A
Ground pins.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V432 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode.
Synchronous global write enable. This input will write all four 8-bit data bytes
when LOW on the rising edge of CLK. GW supercedes individual byte write
enables.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
3104 tbl 02
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings(1)
Symbol
Value
Unit
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
Terminal Voltage with
Respect to GND
–0.5 to VDD+0.5
TA
Operating Temperature
0 to +70
o
C
TBIAS
Temperature Under Bias
–55 to +125
o
C
TSTG
Storage Temperature
–55 to +125
o
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
VTERM
(2)
VTERM
(3)
Rating
Commercial and Industrial Temperature Ranges
Grade
Temperature
VSS
VDD
Commercial
0°C to +70°C
0V
3.3V+10/-5%
Industrial
–40°C to +85°C
0V
3.3V+10/-5%
V
3104 tbl 03
Recommended DC Operating
Conditions
Symbol Parameter
3104 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
VDD
Supply Voltage
VSS
Ground
Min.
Typ.
Max.
Unit
3.135
3.3
3.63
V
0
0
0
V
(2)
VIH
Input High Voltage — Inputs
2.0
—
VIH
Input High Voltage — I/O
2.0
—
VDD+0.3
V
—
0.8
V
VIL
Input Low Voltage
(1)
–0.5
4.6
NOTES:
1. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
6
pF
VOUT = 3dV
7
pF
3104 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
4
V
3104 tbl 04
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Pin Configuration
Top View TQFP
NOTES:
1. Pin 14 can either be directly connected to V DD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
Commercial and Industrial Temperature Ranges
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,2)
Address
Used
CE
CS0
CS1
ADSP
ADSC
ADV
GW
BWE
BWX
OE(3)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
↑
Hi-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
↑
Hi-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
↑
Hi-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
↑
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
↑
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
↑
Hi-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
↑
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
↑
Hi-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
↑
DIN
Operation
3104 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
6.42
6
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1(2)
H
L
L
H
H
H
Write Byte 2(2)
H
L
H
L
H
H
(2)
H
L
H
H
L
H
(2)
H
L
H
H
H
L
Write Byte 3
Write Byte 4
3104 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out (I/O 0 - I/O31)
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z — Data In (I/O 0 - I/O 31)
Active
Deselected
X
L
High-Z
Standby
Sleep
X
H
High-Z
Sleep
3104 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
(1)
Fourth Address
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
3104 tbl 10
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
(1)
Fourth Address
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
7
3104 tbl 11
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., V IN = 0V to VDD
—
5
µA
|ILI|
ZZ and LBO Input Leakage Current (1)
VDD = Max., V IN = 0V to VDD
—
30
µA
|ILO|
Output Leakage Current
CE > VIH or OE > VIH, VOUT = 0V to VDD , VDD = Max.
—
5
µA
VOL
Output Low Voltage (I/O1–I/O 31)
IOL = 5mA, VDD = Min.
—
0.4
V
VOH
Output High Voltage (I/O1–I/O31)
IOH = –5mA, VDD = Min.
2.4
—
V
3104 tbl 12
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to V SS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1) (VDD = 3.3V +10/-5%, VHD = VDD–0.2V, VLD = 0.2V)
IDT71V432S5
IDT71V432S6
Com'l.
Ind.
Com'l.
Ind.
Unit
I DD
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
VIN > VIH or < VIL, f = f MAX(2)
200
200
180
180
mA
ISB
Standby Power Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VIN > VIH or < VIL, f = f MAX(2)
65
65
60
60
mA
ISB1
Full Standby Power Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VIN > VHD or < VLD, f = 0(2)
15
15
15
15
mA
I ZZ
Full Sleep M ode Power Supply Current
ZZ > VHD, VDD = Max.
10
10
10
10
mA
Symbol
Parameter
Test Conditions
3104 tbl 13a
NOTES:
1. All values are maximum guaranteed values.
2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
AC Test Loads
+3.3V
+1.5V
317Ω
50Ω
I/O
I/O
Z0 = 50Ω
351Ω
5pF*
3104 drw 03
Figure 1. AC Test Load
* Including scope and jig capacitance.
6
3104 drw 04
Figure 2. AC Test Load
5
(for tOHZ, tCHZ, tOLZ, and tDC1)
4
3
ΔtCD
(Typical, ns)
2
AC Test Conditions
Input Pulse Levels
1
20 30 50
80 100
Capacitance (pF)
200
3104 drw 05
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
AC Test Load
Figure 3. Lumped Capacitive Load, Typical Derating
0 to 3.0V
See Figures 1 and 2
3104 tbl 14
6.42
8
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V432S5
71V432S6
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
10
____
12
____
ns
(1)
Clock High Pulse Width
4
____
4.5
____
ns
(1)
Clock Low Pulse Width
4
____
4.5
____
ns
Symbol
Parameter
CLOCK PARAMETERS
tCYC
tCH
tCL
OUTPUT PARAMETERS
tCD
Clock High to Valid Data
____
5
____
6
ns
tCDC
Clock High to Data Change
1.5
____
2
____
ns
tCLZ(2)
Clock High to Output Active
0
____
0
____
ns
tCHZ(2)
Clock High to Data High-Z
1.5
5
2
5
ns
tOE
Output Enable Access Time
____
5
____
5
ns
tOLZ(2)
Output Enable Low to Data Active
0
____
0
____
ns
tOHZ(2)
Output Enable High to Data High-Z
____
4
____
5
ns
tSA
Address Setup Time
2.5
____
2.5
____
ns
tSS
Address Status Setup Time
2.5
____
2.5
____
ns
tSD
Data in Setup Time
2.5
____
2.5
____
ns
tSW
Write Setup Time
2.5
____
2.5
____
ns
tSAV
Address Advance Setup Time
2.5
____
2.5
____
ns
tSC
Chip Enable/Select Setup Time
2.5
____
2.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
ns
ZZ Pulse Width
100
—
100
____
ns
(3)
ZZ Recovery Time
100
—
100
____
ns
(4)
Configuration Set-up Time
40
—
50
____
ns
SETUP TIMES
HOLD TIMES
SLEEP MODE AND CONFIGURATION PARAMETERS
tZZPW
tZZR
tCFG
3104 tbl 15a
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42
9
6.42
10
Output
Disabled
tSC
tSA
tSS
tHS
Ax
Pipelined
Read
tOLZ
tOE
tHC
tHA
O1(Ax)
Ay
(1)
tCH
tCLZ
tOHZ
tCD
tSW
tCL
tSAV
O1(Ay)
tCDC
tHAV
O2(Ay)
tHW
Burst Pipelined Read
O3(Ay)
O4(Ay)
(Burst wraps around
to its initial state)
ADV inserts a wait-state
O1(Ay)
tCHZ
O2(Ay)
3104 drw 06
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A 1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW, BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
6.42
11
tSA
tHA
tSS
tHS
tCLZ
tCD
Single Read
Ax
(2)
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Pipelined
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tOLZ
tCDC
O2(Az)
Pipelined Burst Read
O1(Az)
3104 drw 07
O3(Az)
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresses Az; O2(Az) represents the next
output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
6.42
12
tHC
O4(Aw)
Ax
Burst Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
BWE is ignored when ADSP initiates burst
tCH
I2(Ay)
Burst Write
I2(Ay)
(ADV suspends burst)
tSAV
.
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I3(Az)
3104 drw 08
Burst Write
I2(Az)
tHD
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
6.42
13
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
BWx is ignored when ADSP initiates burst
BWE is ignored when ADSP initiates burst
tCH
Burst Write
I2(Ay)
(ADV suspends burst)
I2(Ay)
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
3104 drw 09
I3(Az)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A 0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
6.42
14
tSS
tSC
tSA
tHS
Ax
Single Read
tOLZ
tOE
tHC
tHA
O1(Ax)
tCH
tCL
t ZZPW
Snooze Mode
t ZZR
NOTES:
1. Device must power up in deselected Mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
3104 drw 10
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform(1,2,3,4)
CLK
ADSP or ADSC
ADDRESS
Av
Aw
DATAOUT
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
3104 drw 11
NOTES:
1. ZZ, CE, CS1, and OE are LOW for this cycle.
2. ADV, GW, BWE, BWx, and CS0 are HIGH for this cycle.
3. (Ax) represents the data for address Ax, etc.
4. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
Non-Burst Write Cycle Timing Waveform(1,2,3,4)
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW or
BWE and BWx
DATAIN
(Av)
(Aw)
3104 drw 12
NOTES:
1. ZZ, CE and CS1 are LOW for this cycle.
2. ADV, OE and CS0 are HIGH for this cycle.
3. (AX) represents the data for address AX, etc.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
15
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Ordering Information
6.42
16
Commercial and Industrial Temperature Ranges
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/10/99
03/09/00
04/04/00
08/09/00
08/17/01
03/31/05
08/01/14
10/03/14
Pg. 3–5
Pg. 5
Pg. 11–14
Pg. 17
Pg. 1, 4, 8, 9, 16
Pg. 16
Pg. 17
Pg. 1-3
Pg. 17
Pg. 1
Pg. 1-2
Pg. 2
Pg. 5
Pg. 8
Pg. 9
Pg. 16
Pg. 17
Updated to new format
Adjusted page layout, added extra page
Added notes to pin configuration
Revised notes
Added Datasheet Document History
Added Industrial temperature range offerings
Added 100pinTQFP package Diagram Outline
Added “Not recommended for new designs”
Removed “Not recommended for new designs” from the background on the datasheet
Added RoHS “Restricted Hazardous Substance Device” to ordering information
Moved the FBD, the pin description and pin definition tables to pages 1 - 3 respectively to
align the datasheet reading flow to that of our other established datasheets
In the Ordering Information, Tape & Reel added & RoHS designation changed to Green
Removed 7ns Clock-to-Data Access (66MHz). and added green availability in Features
Moved notes regarding IDT’s use of the CacheRAM, the Pentium processor & the PowerPC
terminology
Removed the reference to IDT with regards to the CMOS process
The package code PK100-1 changed to PK100 to match standard package codes
Removed IDT71V432S7 speed grade offering in the DC Chars table
Removed 71V432S7 speed grade offering in the AC Chars table
Removed TQFP Package Diagram Outline
In the Ordering Information, PK100-1 package code changed to PK100 and 7ns speed
grade was removed
Updated Customer’s SRAM Tech Support phone number and email address
6.42
17
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