IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
IDT74FCT88915TT
55/70/100/133
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 133MHz
• Pin and function compatible with MC88915
• Five non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• Output Skew < 500ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 0.55ns (from tPD max. spec)
• 64/–15mA drive at TTL output voltage levels
• Available in PLCC and SSOP packages
The FCT88915TT uses phase-lock loop technology to lock the frequency
and phase of outputs to the input reference clock. It provides low skew clock
distribution for high performance PCs and workstations. One of the outputs is
fed back to the PLL at the FEEDBACK input resulting in essentially zero delay
across the device. The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The VCO is designed to run optimally between
20MHz and f2Q Max.
The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is
inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs
at half the Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the output path.
PLL _EN allows bypassing of the PLL, which is useful in static test modes. When
PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the
input frequency is not limited to the specified range and the polarity of outputs
is complementary to that in normal operation (PLL_EN = 1). The LOCK output
attains logic high when the PLL is in steady-state phase and frequency lock.
The FCT88915TT requires external loop filter components as recommended in Figure 2.
FUNCTIONAL BLOCK DIAGRAM
FEEDBAC K
SYNC (0)
SYNC (1)
LOCK
0M
u
1x
Phase/Freq.
Detector
Voltage
Controlled
Oscilator
C harge Pump
LF
REF_SEL
PLL_EN
0
1
Mux
2Q
(÷ 1)
Divide
-By-2
1M
u
0x
( ÷ 2)
D
CP
Q
D
FREQ_SEL
Q0
R Q
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q/2
CP R
RST
D
CP R
D
CP
R
D
CP
R
D
CP
R
D
CP R
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 2001
1
© 2001 Integrated Device Technology, Inc.
DSC-4245/4
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
RST
VCC
Q5
GND
Q4
VCC
2Q
PIN CONFIGURATIONS
4
3
2
1
28
27
26
FEEDBK
5
25
Q/2
REF_SEL
6
24
GND
GND
1
28
Q4
Q5
2
27
VCC
VCC
3
26
2Q
RST
4
25
Q/2
FEEDBACK
5
24
GND
REF_SEL
6
23
Q3
SYNC(0)
7
23
Q3
VCC(AN)
8
22
VCC
SYNC(0)
7
22
VCC
LF
9
21
Q2
VCC(AN)
8
21
Q2
LF
9
20
GND
GND(AN)
10
20
GND
GND(AN)
10
19
LOCK
SYNC(1)
11
19
LOCK
18
PLL_EN
17
GND
16
Q1
15
VCC
14
Q0
13
GND
FREQ_SEL
12
SYNC(1)
11
18
PLL_EN
FREQ_SEL
12
17
GND
GND
13
14
16
15
Q1
Q0
PLCC
TOP VIEW
SSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
FREQ_SEL
FEEDBACK
LF
Q0-Q4
Q5
2Q
Q/2
LOCK
RST
PLL_EN
I/O
I
I
I
I
I
I
O
O
O
O
O
I
I
Description
Reference clock input
Reference clock input
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram)
Feedback input to phase detector
Input for external loop filter connection
Clock outputs
Inverted clock output
Clock output (2 x Q frequency)
Clock output (Q frequency ÷ 2)
Indicates phase lock has been achieved (HIGH when locked)
Asynchronous reset (active LOW)
Disables phase-lock for low frequency testing (refer to functional block diagram)
2
VCC
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
VTERM(3)
TA
TBIAS
TSTG
IOUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
StorageTemperature
DC Output Current
Max.
–0.5 to 7
–0.5 to VCC+0.5
0 to +70
–55 to +125
–55 to +125
–60 to 120
Parameter(1)
Symbol
Unit
V
V
°C
°C
°C
mA
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SYNC INPUT TIMING REQUIREMENTS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Outputs and I/O terminals.
Symbol
TRISE/FALL
Frequency
Duty Cycle
Parameter
Rise/Fall Times, SYNC inputs
(0.8V to 2.0V)
Input Frequency, SYNC Inputs
Input Duty Cycle, SYNC Inputs
Min.
—
Max.
3
Unit
ns
10
25%
2Q fmax
75%
MHz
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 5.0V ±5%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current
VCC = Max.
VI = VCC
—
—
±1
µA
IIL
Input LOW Current
VI = GND
—
—
±1
µA
VIK
Clamp Diode Voltage
—
–0.7
–1.2
V
VIH
Input Hysteresis
—
100
—
mV
VOH
Output HIGH Voltage
VCC = Min.
IOH = –15mA
2.4
3.5
—
V
VOL
Output LOW Voltage
VCC = Min.
IOL = 64mA
—
0.2
0.55
V
ICCL
ICCH
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
(Test mode, LF connected to GND)
—
2
4
mA
VCC = Min., IIN = –18mA
—
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
3
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔICC
ICCD
CPD
IC
PD1
PD2
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Power Dissipation Capacitance
Total Power Supply Current(5,6)
Power Dissipation
Power Dissipation
Test Conditions(1)
VCC = Max.
VIN = VCC –2.1V(3)
VCC = Max.
VIN = VCC
All Outputs Open
VIN = GND
50% Duty Cycle
VCC = Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50pF.
All other outputs open.
VCC = Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50Ω
Thevenin termination. All other outputs open.
50Ω Thevenin termination @ 33MHz
50Ω Paralell termination to GND @ 33MHz
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
—
0.5
0.7
—
—
25
65
40
80
mA/
MHz
pF
mA
—
—
—
mA
—
—
120
300
—
—
mW
mW
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
ILOAD = Dynamic Current due to load.
OUTPUT FREQUENCY SPECIFICATIONS
Max.(2)
Symbol
f2Q
fQ
fQ/2
Parameter
Operating frequency 2Q Output
Operating frequency Q0-Q4, Q5 Outputs
Operating frequency Q/2 Output
Min.
40
20
10
55
55
27.5
13.75
70
70
35
17.5
100
100
50
25
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded with 50pF.
4
133
133
66.7
33.3
Unit
MHz
MHz
MHz
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition(1)
Min.
Max.
Unit
CL = 50pF
RL = 500Ω
1(2)
2.5
ns
tRISE/FALL
All Outputs
Rise/Fall Time
(between 0.2 VCC and 0.8 VCC )
tRISE/FALL
2Q Output(3)
Rise/Fall Time
(between 0.8V and 2.0V)
CL = 20pF &
termination(7)
0.5(2)
1.6
ns
tPULSE WIDTH
Q, Q, Q/2 Outputs(3)
Output Pulse Width
Q0-Q4, Q5, Q/2 @ VCC/2
CL = 50pF
0.5tCYCLE – 0.5(5)
0.5tCYCLE + 0.5(5)
ns
tPULSE WIDTH
2Q Output(3)
Output Pulse Width
2Q Output @ VCC/2
CL = 50pF
0.5tCYCLE – 1(5)
0.5tCYCLE + 1(5)
ns
tPULSE WIDTH
2Q Output(3)
Output Pulse Width
2Q @ 1.5V
Termination as in
note 7
0.5tCYCLE – 0.5(5)
0.5tCYCLE + 0.5(5)
ns
tPD
SYNC-FEEDBACK(3)
SYNC input to FEEDBACK delay
(measured at SYNC0 or 1 and FEEDBACK
input pins)
Output to Output Skew between outputs 2Q,
Load = 50Ω to VCC/2,
CL = 20pF
0.1MF from LF to Analog GND(9)
CL = 50pF
–0.5
+0.5
ns
—
500
ps
—
500
ps
—
500
ps
1(2)
10
ms
1.5(2)
8
ns
9
—
ns
5
—
ns
tSKEWr
(rising)(3, 4)
tSKEWf
Q0-Q4,Q/2 (rising edges only)
Output to Output Skew between outputs 2Q,
(falling)(3, 4)
Q0-Q4 (falling edges only)
tSKEWALL(3, 4)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
tLOCK(6)
Time required to acquire Phase-Lock from time
SYNC input signal is received
tRST
Propagation Delay, RST (HIGH-to-LOW) to any
Reset – Q
Output (HIGH-to-LOW)
tREC(10)
Reset Recovery Time
Rising RST edge to falling SYNC edge
tW(10)
Minimum Pulse Width RST input LOW
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, CL = 50pF (±2pF), and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF (where C1 is loop filter
capacitor shown in Figure 2).
7. These two specs ( tRISE/FALL and tPULSE WIDTH 2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed
by IDT, the termination scheme shown in Figure 1 must be used:
Rs
88915TT
2Q
Output
Zo (clock trace)
68040
P-Clock
Input
Rs = Zo - 7 Ω
Rp
Rp = 1.5 Zo
Figure 1. MC68040 P-Clock Input Termination Scheme
5
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
GENERAL AC SPECIFICATION NOTES, CONTINUED
8. The wiring diagrams and written explanations of Figures 4a-4c demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also, it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration:
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHz)
Corresponding 2Q Output
Frequency Range
Phase Relationship
of the Q Outputs
to Rising SYNC Edge
0°
HIGH
Q/2
10 to (2Q fMAX Spec)/4
40 to (2Q fMAX Spec)
HIGH
Any Q (Q0-Q4)
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
0°
HIGH
Q5
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
180°
HIGH
2Q
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
0°
LOW
Q/2
5 to (2Q fMAX Spec)/8
20 to (2Q fMAX Spec)/2
0°
LOW
Any Q (Q0-Q4)
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
0°
LOW
Q5
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
180°
LOW
2Q
20 to (2Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
0°
9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input varies with process, temperature, and voltage. The phase
measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with the loop
filter connection shown in Figure 2 below:
LF
External Loop
Filter
0.1µF
C1
Analog GND
Figure 2. Loop Filter Connection
6
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
BOARD V CC
ANALOG V CC
10 μ F
Low
Freq.
Bypass
0.1 μ F
High
Freq.
Bypass
LF
Analog loop filter/VCO
section of the FCT88915TT
0.1 μ F (Loop
Filter Cap)
ANALOG G ND
BOARD GND
A separate Analog power supply is not necessary
and should not be used. Following these prescribed guidelines is all that is necessary to use
the FCT88915TT in a norm al digital environment.
Figure 3. Recommended Loop Filter and Analog Isloation Scheme for the FCT88915TT
NOTES:
1. Figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free
operation:
a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable
voltage transients at the LF pin.
b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915TT's sensitivity to voltage
transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 88915TT's
digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 3 is to give the 88915TT additional protection from the power supply and ground plane transients
that can occur in a high frequency, high speed digital system.
c. The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of Figure 3, there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board
ground plane. This will reduce output switching noise caused by the 88915TT outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass
capacitors should also be tied as close to the 88915TT package as possible.
7
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
Q2, Q3 and Q4).
50 MHz signal
25 MHz feedback signal
HIGH
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the Q/2 output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of Q/2 and SYNC. Thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
Q5
RST
Q4
FEEDBACK
LOW
25 MHz
input
2Q
Q/2
12.5 MHz
signal
REF_SEL
Q3
SYNC(0)
FCT88915T
T
VCC(AN)
LF
25 MHz
"Q"
Clock
Outputs
Q2
GND(AN
)
FQ_SEL
50 MHz signal
12.5 M Hz feedback signal
Q0
Q1
PLL_EN
HIG H
HIGH
HIGH
RST
Q5
Q4
FEED BACK
LO W
12.5 M Hz
input
2Q
Q/2
Allowable Input Frequency Range:
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL LOW)
REF_SEL
Q3
SYNC(0)
V CC (AN)
FCT88915TT
Q2
LF
25 MHz
"Q"
Clock
Outputs
Figure 4b. Wiring Diagram and Frequency Relationships
with Q4 Output Feedback
GND(AN)
FQ_SEL
Q0
HIGH
Q1
PLL_EN
HIGH
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the 2Q output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of 2Q and SYNC. Thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Allowable Input Frequency Range:
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q FMAX Spec)/8 (for FREQ_SEL LOW)
50 MH z feedback signal
HIGH
Figure 4a. Wiring Diagram and Frequency Relationships
with Q/2 Output Feedback
RST
Q5
Q4
FEED BAC K
LOW
50 MHz
input
Q/2
12.5 MHz
input
REF_SEL
Q3
SYN C(0)
V CC (AN)
FCT88915TT
Q2
LF
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the Q4 output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of Q4 and SYNC. Thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
2Q
25 MH z
"Q"
Clock
Outputs
GN D(AN)
FQ_SEL
Q0
HIGH
Q1
PLL_EN
HIGH
Allowable Input Frequency Range:
40MHz to (f2Q FMAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL LOW)
Figure 4c. Wiring Diagram and Frequency Relationships
with 2Q Output Feedback
8
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
CM M U
CM M U
CPU
CM M U
CM M U
CM M U
CM M U
CM M U
CPU
CM M U
CM M U
CM M U
CPU
CARD
FCT88915TT
CLOCK
@f
PLL
2f
SYSTEM
CLOCK
SOURCE
CPU
CARD
FCT88915TT
PLL
2f
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
at point of use
FCT88915TT
PLL
ME MO RY
CONTROL
2f
ME MO RY
CARDS
CLOCK @ 2f
at point of use
Figure 5. Multiprocessing Application Using the FCT88915 for Frequency Multiplication
and Low Board-to-Board skew
FCT88915 SYSTEM LEVEL TESTING FUNCTIONALITY
When the PLL_EN pin is LOW, the PLL is bypassed and the FCT88915TT
is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q
output is inverted from the selected SYNC input, and the Q outputs are divideby-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divideby-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divideby-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A recommended test
configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie
PLL_EN and REF_SEL together and connect them to the test select logic.
This functionality is needed since most board-level testers run at 1 MHz or
below, and the FCT88915TT cannot lock onto that low of an input frequency.
In the test mode described above, any test frequency test can be used.
9
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
V OUT
V IN
Pulse
Generator
D.U.T.
50pF
500 Ω
CL
RT
Test Circuits For All Outputs
SYNC IN PUT
(SYNC (1) or
SYNC (0))
1.5V
t C YC LE
SYN C IN PU T
t PD
1.5V
FEED BACK
INPUT
1.5V
Q/2 OUTPUT
t SK EW A LL
t SKEW f
t SKEW r
t SKE W f
t SKE W r
1.5V
Q0-Q4
OUTPUTS
t C YC LE
"Q" OU TP UTS
1.5V
Q5 OUTPUT
1.5V
2Q OUTPUT
Propagation Delay, Output Skew
(These waveforms represent the configuration shown in Figure 4a)
NOTES:
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input. Therefore, the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency, and the Q/2 output would run at half the SYNC frequency.
10
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
FCT
XXXX
IDT
XX
Temp. Range
Device Type
X
Speed
X
Package
J
JG
PY
PYG
(1)
Plastic Leaded Chip Carrier
PLCC - Green
Small Shrink Outline IC
SSOP - Green
55
(1)
70
(1)
100
(1)
133
55MHz Max. frequency
70MHz Max. frequency
100MHz Max. frequency
133MHz Max. frequency
88915TT
Low Skew PLL-Based CMOS Clock Driver
74
0°C to +70°C
NOTE:
1. When ordering GREEN packages, replace this numeric value with the equivalent letter below.
A= 55 MHz
B= 70 MHz
C= 100 MHz
D= 133 MHz
For example, to order a 133MHz version, Green PLCC, the nomenclature would be 74FCT88915TTDPYG.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
11
for Tech Support:
clockhelp@idt.com
