IDT79RC32V364-133DAG 数据手册
79RC32364™
RISControllerTM Embedded 32-bit
Microprocessor, based on
RISCore32300
Features
Flexible RC4000 compatible MMU with 32-page TLB on-chip
– Variable page size
– Variable number of locked entries
– No performance penalty for address translation
◆
Flexible bus interface allows simple, low-cost designs
– Bus interface runs at a fraction of pipeline rate
– Programmable port-width interface (8-,16-, 32-bit memory and
I/O regions)
– Programmable bus turnaround times (BTA)
– Supports single data or burst transactions
◆
Improved real-time support
– Fast interrupt decode
◆
Low-power operation
– Active power management: powers down inactive units
– Typical power 700mW @ 133MHz
– Stand-by mode VCC
3.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
Recommended Operation Temperature and Supply Voltage
Voltage
Grade
Temperature
Gnd
RC32364
VCC Core & Vcc I/O
Commercial
0°C to +85°C (Case)
0V
3.3V±5%
Industrial
-40°C + 85°C (Case)
0V
3.3V±5%
AC Electrical Characteristics — Commercial/Industrial Temperature
Ranges—RC32364
VCC Core & VCC I/O = 3.3V ± 5%; TCase = 0°C to +85°C Commercial, TCase = -40° C to +85°C Industrial
Clock Parameters—RC32364
Note: Operation of the RC32364 is only guaranteed with the Phase Lock Loop enabled
Parameter
Symbol
Pipeline clock frequency
Test
Conditions
PClk
RC32364 100MHz
RC32364 133MHz
Min
Max
Min
Max
80
100
80
133
MHz
Units
MasterClock HIGH
tMCHIGH
Transition ≤ 2ns
6
—
5
—
ns
MasterClock LOW
tMCLOW
Transition ≤ 2ns
6
—
5
—
ns
MasterClock Frequency
—
—
10
50
10
67
MHz
tMCP
—
20
100
15
100
ns
tJitterIn1
—
—
±250
—
±250
ps
MasterClock Period
1
Clock Jitter for MasterClock
2
MasterClock Rise Time
tMCRise
—
—
3
—
3
ns
MasterClock Fall Time2
tMCFall
—
—
3
—
3
ns
JTAG Clock Period
tTCK
—
100
—
100
—
ns
JTAG Clock High and Low Time
tTCKLOW, tTCKHIGH
—
40
—
40
—
ns
JTAG Clock Fall and Rise Time
tTCKFall, tTCKRise
—
—
3
—
3
ns
1.
Guaranteed by design
2. Rise and
Fall times are measured between 10% and 90%.
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79RC32364™
System Interface Parameters—RC32364
Parameter
Symbol
Test Conditions
RC32364
100MHz
RC32364
133MHz
Min
Max
Min
Max
Units
Data Output
tDO = Max
—
6
—
6
ns
Data Output Hold
tDOH
0.7
—
0.7
—
ns
Data Output for ALE
tDOA
—
6
—
6
ns
Data Setup
tDS
3
—
3
—
ns
6
—
5
—
ns
trise = 2ns
tfall = 2ns
Data Setup Special: Ack, Retry, BusErr tDSS
Data Hold
tDH
0.5
—
0.5
—
ns
JTAG Clock Period
tTCK, t3
100
—
100
—
ns
DCLK Clock Period
tDCK, t11
12.5
—
12.5
—
ns
DCLK High, Low Time
tDCK High, t9
tDCK Low, t10
2.5
—
2.5
—
ns
DCLK Rise, Fall Time
tDCK Rise, t15
tDCK Fall, t15
—
3.5
—
3.5
ns
TDO Output Delay Time
tTDODO, t4
—
6
—
6
ns
TDI Input Setup Time
tTDIS, t5
4
—
4
—
ns
TDI Input Hold Time
tTDIH, t6
2
—
2
—
ns
TPC Output Delay Time
tTPCDO, t8
-1
6
-1
6
ns
PCST Output Delay Time
tPCSTDO, t7
-1
6
-1
6
ns
TRST* Low TIme
tTRSTLow, t12
100
—
100
—
ns
TRST* Removal TIme
tTRSTR, t13
3
—
3
—
ns
DC Electrical Characteristics — Commercial/Industrial Temperature
Ranges—RC32364
VCC Core & VCC I/O = 3.3V ± 5%; TCase = 0°C to +85°C Commercial, TCase = -40° C to +85°C Industrial
RC32364
100MHz
Parameter
RC32364
133MHz
Conditions
Min
Max
Min
Max
VOL
—
0.1V
—
0.1V
VOH
VCC - 0.1V
—
VCC - 0.1V
—
VOL
—
0.4V
—
0.4V
VOH
2.4V
—
2.4V
—
VIL
–0.5V
0.2VCC
–0.5V
0.2VCC
—
VIH
0.7VCC
VCC +0.3V
0.7VCC
VCC + 0.3V
—
CIN
—
10pF
—
10pF
—
COUT
—
10pF
—
10pF
—
I/OLEAK
—
20uA
—
20uA
Input/Output Leakage
|IOUT|= 20uA
|IOUT|= 4mA
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June 20, 2000
79RC32364™
Output Loading For AC Testing
VREF
To Device
Under Test
–
+
+1.5V
CLD
Figure 3 Output Loading for AC Testing
Signal
Cld
All Signals
50 pF
Power Consumption — RC32364
Parameter
System Condition:
ICC
P
1.
RC32364 100MHz
Typical
Maximum
100/50MHz
RC32364 133MHz
Typical
Conditions
Maximum
133/67MHz
—
standby1
50mA
90mA
50mA
90mA
CL = 50pF
Tc = 25oC
Vcc core & Vcc I/O = 3.65V
active
160mA
180mA
200mA
250mA
CL = 50pF
TC = 25oC
Vcc core, Vcc I/O = 3.65V
0.6W
0.7Watt
0.9
CL = 50pF
TC = 25oC
Vcc core, Vcc I/O = 3.65V
power
0.58W
dissipation
Executing wait instruction
Capacitive Load Deration — RC32364
Parameter
Symbol
Load Derate
CLD
Test
Conditions
—
100MHz
133MHz
Min
Max
Min
Max
—
2
—
2
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Units
ns/25pF
June 20, 2000
79RC32364™
Power Curves
The following two graphs contain power curves that show power consumption at various bus frequencies.
Note: Only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported.
275.0
ICC (mA)
225.0
3x
6x 5x
4x
175.0
2x
2x
3x
4x
7x
5x
8x
6x
125.0
7x
8x
75.0
25.0
10 15 20 25 30 35 40 45 50 55 60 65
System Bus Speed (MHz)
Figure 4 Typical Power Usage - RC32364
350.0
5x
ICC (mA)
300.0
6x
3x
4x
2x
7x
250.0
2x
3x
4x
8x
5x
200.0
6x
150.0
7x
8x
100.0
50.0
10 15 20 25 30 35 40 45 50 55 60 65
System Bus Speed (MHz)
Figure 5 Maximum Power Usage - RC32364
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June 20, 2000
79RC32364™
Timing Characteristics — RC32364
tMCKP
tMCKLOW
tMCKHIGH
MasterClock
Input
Output
tMCRISE
tDS
tMCFALL
tDH
tDO
tDO
ALE
tDOH
tDOA
Ack*
Retry*
BusErr*
tDSS
tDH
Figure 6 System Clocks Data Setup, Output, and Hold timing
VCC
MasterClock
(MClk)
ColdReset*
Reset*
ModeBit[9:0]
>= 100 ms
>= 10 ms
>= 64 MClk
cycles
Figure 7 Mode Configuration Interface Reset Sequence
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June 20, 2000
79RC32364™
Standard JTAG Timing
Figure 8 represents the timing diagram for the EJTAG interface signals.
The standard JTAG connector is a 10-pin connector providing 5 signal and 5 ground pins. For Enhanced JTAG, a 24-pin connector has been
chosen providing 12 signal pins and 12 ground pins. This guarantees the elimination of noise problems by incorporating a signal-ground type arrangement.
TPC,PCST[2:0] capture
t3
TCK
t14
t14
t1
DCLK
t11
t2
t15
t15
t9
TDI/DINT*
TMS
TDO/TPC,
TPC[8:2]
t5
TDO
t6
TDO
t10
TPC
t8
t4
PCST[2:0],
PCST
t7
TRST*
t13
t12
Notes to diagram:
t1 = tTCKlow
t2 = tTCKHIGH
t3 = tTCK
t4 = tTDODO
t5 = tTDIS
t6 = tTDIH
t7 = tPCSTDO
t8 = tTPCDO
t9 = tDCKHIGH
t10 = tDCKLOW
t11 = tDCK
t12 = tTRSTDO
t13 = tTRSTR
t14 = tTCK RISE, tTCK FALL
t15 = tDCK RISE, tDCK FALL
Figure 8 Standard JTAG timing
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79RC32364™
Table 4 shows the pin numbering for the Standard EJTAG (EJT) connector. All the even numbered pins are connected to GROUND. The two righthand most columns show the target signal direction and the recommended termination at the target. Target termination resistors may be internal to the
chip or external on the board.
PIN
SIGNAL
TARGET
I/O
TERMINATION1
1
TRST* (optional)
Input
10 kΩ pull-down resistor
3
TDI/DINT*
Input
10 kΩ pull-up resistor
5
TDO/TPC
Output
33 Ω series resistor
7
TMS
Input
10 kΩ pull-up resistor
9
TCK
Input
10 kΩ pull-up resistor2
11
RST*
Input
10 kΩ pull-up resistor
13
PCST[0]
Output
33 Ω series
15
PCST[1]
Output
33 Ω series
17
PCST[2]
Output
33 Ω series
19
DCLK
Output
33 Ω series
21
Debugboot
Input
10 kΩ pull-down resistor
23
VIO
Input
Must be connected to the VCC IO supply of the device.
Table 4 Pin Numbering of the JTAG and EJTAG Target Connector
1. The
value of the series resistor may depend on the actual PCB layout situation.
2.
TCK pull-up resistor is not required according to the JTAG (IEEE1149) standard. It is indicated here to prevent a floating
CMOS input when the EJTAG connector is unconnected.
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June 20, 2000
79RC32364™
RC32364 Package Drawing — 144-pin TQFP
(Note: The RC32364 is available in a 144-pin thin quad flat pack (TQFP) package.)
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79RC32364™
RC32364 Package Drawing
— Page Two
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June 20, 2000
79RC32364™
Ordering Information
IDT79RCXX
Product
Type
YY
Operating
Voltage
XXXX
999
Device
Type
Speed
A
Package
A
Temp range/
Process
Blank Commercial Temperature Range
(0°C to +85°C Case)
I
Industrial Temperature Range
(-40°C to +85°C Case)
DA
144-pin TQFP
100
133
100 MHz PClk
133 MHz PClk
364
Embedded Processor
V
3.3V +/-5%
79RC32 32-bit Embedded
Microprocessor
Valid Combinations
IDT79RC32V364 - 100,133 DA
IDT79RC32V364 - 100,133 DAI
TQFP package, Commercial Temperature
TQFP package, Industrial Temperature
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: rischelp@idt.com
phone: 408-284-8208
The IDT logo is a trademark of Integrated Device Technology, Inc.
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June 20, 2000