IDTCV136PAG

IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 FEATURES: DESCRIPTION: • One high precision N and SSC programmable PLL for CPU • One high precision N and SSC programmable PLL for SRC[2:1] • One high precision N and SSC programmable PLL for SRC[7:3] SRC0 (PCI Express) and PCI • One high precision PLL for 48MHz • Band-gap circuit for differential outputs • Support multiple spread spectrum modulation, down and center • Support SMBus block read/write, index read/write • Selectable output strength for REF, PCI, 48MHz • Available in TSSOP package IDTCV136 is a 56 pin clock device for Intel P4 processors. The CPU output buffer is designed to support up to 400MHz processor. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU/SRC clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. KEY SPECIFICATION: • CPU CLK cycle to cycle jitter < 85ps • SRC CLK cycle to cycle jitter < 125ps FUNCTIONAL BLOCK DIAGRAM SRC SSC N Programming SRC[7:3], 0 SRC PCI0 PCI/ SRC PLL SSC N Programming 14.318MHz Osc CPU PLL SSC N Programming CLKREQ0# CLKREQ1# SRC/ SRC[2:1] CPU/HOST CPU[2:0] TURBO1# USB48 Fixed PLL No SSC 48MHz/ 48MHz REF[2:0] Reset# OUTPUT TABLE CPU CLKREQ SRC PCI TURBO USB48 48MHz REF RESET# 3 2 8 1 1 1 1 3 1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2005 1 © 2005 Integrated Device Technology, Inc. DSC - 6733/18 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE FREQUENCY SELECTION PIN CONFIGURATION XIN 1 56 VDD_REF XOUT 2 55 VSS_REF VDD_48 3 54 REF0/FSA USB_48 4 53 REF1/FSB VSS_48 5 52 REF2 VTT_PWRGD#/PD 6 51 VDD_PC1 SCL 7 50 PCI0/409_410# SDA 8 49 VSS_PCI 48MHz/FSC (1) CLKREQ0# 9 48 10 47 CPU_Stop# CPUT0 (1) CLKREQ1# 11 46 CPUC0 SRCT7 12 45 VDD_CPU SRCC7 13 44 VSS_CPU VDD_SRC 14 43 CPUT1 RESET# 15 42 CPUC1 SRCT6 16 41 CPUT2 SRCC6 17 40 CPUC2 SRCT5 18 39 VDDA SRCC5 19 38 VSSA VSS_SRC 20 37 IREF VDD_SRC 21 36 VSS_SRC SRCT4 22 35 VDD_SRC SRCC4 23 34 SRCT0 (2) SRCT3 24 33 SRCC0 SRCC3 25 32 VDD_SRC TURBO1 26 31 VSS_SRC SRCT2 27 30 SRCT1 SRCC2 28 29 SRCC1 409_410#, FSC, B, A 0000 0001 0010 0011 0100 0101 0110 0111 1x00 1x01 1x10 1x11 1x00 1x01 1x10 1x11 (1) CPU 266 133 200 166 333 100 400 100 133.3 200 166.67 SRC 100 100 100 100 100 100 100 100 100 100 100 100 CPU AND SRC SPREAD SPECTRUM MAGNITUDE CONTROL SMC[2:0] 000 001 010 011 100 101 110 111 NOTES: 1. Internal 130KΩ pull-down resistor. 2. Power On Tristate. SSOP/ TSSOP TOP VIEW 2 % OFF - 0.25 - 0.5 - 0.75 ±0.125 ±0.25 ±0.375 ±0.5 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Name XIN XOUT PCI0/409_410# USB48 CPUC[2:0] CPUT[2:0] SRCC[7:0] SRCT[7:0] Type IN OUT I/O OUT OUT Pin # 1 2 50 4 40, 41, 42, 43, 46, 47 Description XTAL in XTAL out PCI clock/ CPU type select, see Frequency Selection Table. 48MHz Differential clock OUT Differential clock IREF REF0/FSA REF1/FSB REF2 48MHz/ FSC VTT_PWRGD#/PD OUT I/O I/O OUT IN IN 12, 13, 16, 17, 18, 19 22, 23, 24, 25, 27, 28, 29, 30, 33, 34 37 54 53 52 9 6 CPU_STP# CLKREQ0# CLKREQ1# SDA SCL Turbo1 RESET# IN IN IN I/O IN IN OUT, OD 48 10 11 8 7 26 15 Differential output reference current HW frequency select, sampled at VTT_PWRGD# assertion. 14.318MHz afterward. HW frequency select, sampled on VTT_PWRGD# assertion. 14.318MHz afterward. 14.318MHz Frequency Select at VTT_PWRGD# assertion. 48 MHz is tri-state at power on. 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down (active HIGH). CPU clock stop, low active SRC OE control, see byte 3 and 4, low active SRC OE control, see byte 3 and 4, low active SMBus data SMBus clock Turbo frequency switch Reset output signal, Open Drain SE SIGNAL STRENGTH SELECTION Str[1:0] 00 01 10 11 RESOLUTION Strength 0.6x 0.8x 1x 1.2x Parameter CPU = 100MHz mode CPU = 133MHz mode CPU = 166MHz mode CPU = 200MHz mode CPU = 266MHz mode CPU = 333MHz mode CPU = 400MHz mode SRC (PCI Express) PCI (BASED ON SRC = 100MHz) PCIS[1:0] 00 01 10 11 PCI 33.33 36.36 40.00 30.77 3 N Resolution (MHz) 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 0.666667 % 0.67% 0.50% 0.80% 0.67% 0.50% 0.80% 0.67% 0.67% IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE SM PROTOCOL INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes). Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop RANDOM BYTE WRITE RANDOM BYTE READ Setting bit[11] = 1, bit[12:18] = starting address, the following is the first write data. After writing it, master issues stop bit. Setting bit[11] = 1, bit[12:18] = starting address, the following is the first read data. After reading back the first data byte, master issues Stop bit. 4 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRCT7, SRCC7 SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 SRCT3, SRCC3 SRCT2, SRCC2 SRCT1, SRCC1 SRCT0, SRCT0 Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 USB48 REF2 REF1 REF0 48MHz CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 0 1 1 1 BYTE 1 BYTE 2 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 PCI0 Reserved PCI SEL1 PCI SEL0 CPUTs CPUT2, CPUC2 Output Enable Tristate Enable CPUT1, CPUC1 RW 1 0 CPUT0, CPUC0 Tristate when stoped Stopped with CPU_STOP# Stopped with CPU_STOP# Stopped with CPU_STOP# 1 0 0 0 0 1 1 Driven in CPU_STOP# Free running, not stopped by CPU_STOP# Free running, not stopped by CPU_STOP# Free running, not stopped by CPU_STOP# RW RW RW RW RW RW RW 1 See PCI select table CPUT0 CPU_STOP drive mode Allow control of CPU2 with assertion of CPU_STOP# Allow control of CPU1 with assertion of CPU_STOP# Allow control of CPU0 with assertion of CPU_STOP# BYTE 3 Bit Output(s) Affected 7 6 5 4 3 2 1 0 SRC7 SRC6 SRC5 SRC4 SRC3 Reserved Reserved SRC0 Description / Function Controlled by CLKREQ0# or CLKREQ1# Controlled by CLKREQB# or CLKREQA# 5 0 1 Type Power On CLKREQ0# CLKREQ0# CLKREQ0# CLKREQ0# CLKREQ0# CLKREQ1# CLKREQ1# CLKREQ1# CLKREQ1# CLKREQ1# CLKREQ0# CLKREQ1# RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected 7 6 5 4 3 2 1 0 SRC7 SRC6 SRC5 SRC4 SRC3 Reserved Reserved SRC0 Description / Function When CLKREQ is HIGH, Output is Hi-Z When CLKREQ is HIGH, Output is Hi-Z 0 1 Type Power On Not Controlled Not Controlled Not Controlled Not Controlled Not Controlled Controlled Controlled Controlled Controlled Controlled Not Controlled Controlled RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 BYTE 5 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRCs CPUs PCIStrC1 PCIStrC0 REFStr1 REFStr0 48MHzStr1 48MHzStr0 SRCT Pwrdwn drive mode CPUT0 Pwrdwn drive mode PCI strength selection Driven in power down Driven in power down Tristate in power down Tristate in power down RW RW RW RW RW RW RW RW 0 0 1 0 1 0 1 0 0 1 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Type Power On R R R R R R R R 0 0 0 0 0 1 0 1 REF strength selection USB48MHz strength selection BYTE 6 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Reserve SRC0, SR[7:3], SMC2 SRC0, SR[7:3], SMC1 SRC0, SR[7:3], SMC0 Reserved SRC[2:1], SMC2 SRC[2:1], SMC1 SRC[2:1], SMC0 Description / Function SRC0, SRC[7:3] SSC control (see SMC table) SRC[2:1] control (see SMC table) BYTE 7 Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function 0 Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID 6 1 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE BYTE 8 (INDEX BLOCK READ BYTE COUNT) Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 1 0 1 0 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 1 0 1 1 BYTE 9 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved CPU SMC2 CPU SMC1 CPU SMC0 Description / Function 0 1 CPU PLL SSC control (see SMC table) BYTE 10 Bit Output(s) Affected 7 6 5 4 3 2 1 0 WD_1_ Timer 7 WD_1_ Timer 6 WD_1_ Timer 5 WD_1_ Timer 4 WD_1_ Timer 3 WD_1_ Timer 2 WD_1_ Timer 1 WD_1_ Timer 0 Description / Function 0 1 WatchDog_1_Alarm timer Default is 11*290ms BYTE 11 Bit Output(s) Affected 7 6 5 4 3 CPU_N8 Reserved Reserved Reserved WDRB 2 1 0 RESET#(1) Reserved Watch Dog Enable Description / Function 0 1 Type Power On Alarm RW RW RW RW R 0 0 0 0 0 RW RW RW 0 0 0 Alarm read back, reset by WD disable Reset Enable Disable Reset Enable Watch Dog Enable Disable Enable 7 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE BYTE 12 (CPU N) Bit Output(s) Affected 7 6 5 4 3 2 1 0 CPU_N7 CPU_N6 CPU_N5 CPU_N4 CPU_N3 CPU_N2 CPU_N1 CPU_N0, LSB Description / Function 0 1 CPU N default should reflect latched FS CPU CLK = N*Resolution(1) Type Power On RW RW RW RW RW RW RW RW 1 1 0 0 1 0 0 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 NOTE: 1. Resolution depends on FSA, FSB, and FSC values that are latched during power on (see Resolution table). BYTE 13 (SRC[2:1] N) Bit Output(s) Affected 7 6 5 4 3 2 1 0 SRC1_N7, MSB SRC1_N6 SRC1_N5 SRC1_N4 SRC1_N3 SRC1_N2 SRC1_N1 SRC1_N0, LSB Description / Function 0 1 SRC2, SRC1 SRD CLK = N*0.66667 BYTE 14 (SRC[7:3], SRC0 N) Bit Output(s) Affected 7 6 5 4 3 2 1 0 SRC0_N7, MSB SRC0_N6 SRC0_N5 SRC0_N4 SRC0_N3 SRC0_N2 SRC0_N1 SRC0_N0, LSB Description / Function 0 1 SRC[7:3], SRC0 SRD CLK = N*0.66667 BYTE 15 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Reserved CPU N programming enable SRC1, SRC2 N Programming enable SRC0, SRC[7:3] N Programming enable Turbo1 enable Turbo1 Reserved T1CN8 Description / Function 0 1 Type Power On Turbo Active Selection Disable Disable Disable Disable Disable Active LOW Enable Enable Enable Enable Enable Active HIGH RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 8 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE BYTE 16 (TURBO1 N FOR CPU) Bit Output(s) Affected 7 6 5 4 3 2 1 0 T1CN7 T1CN6 T1CN5 T1CN4 T1CN3 T1CN2 T1CN1 T1CN0 Description / Function 0 1 Turbo1 CPU PLL N setting Type Power On RW RW RW RW RW RW RW RW 1 1 0 0 1 0 0 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 BYTE 17 (TURBO1 FOR SRC1,2) Bit Output(s) Affected 7 6 5 4 3 2 1 0 TSRC1_N7, MSB TSRC1_N6 TSRC1_N5 TSRC1_N4 TSRC1_N3 TSRC1_N2 TSRC1_N1 TSRC1_N0, LSB Description / Function 0 1 Turbo1 SRC2, SRC1 SRC CLK = N*0.66667 BYTE 18 (RESERVED FOR USER) Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 BYTE 19 (RESERVED FOR USER) Bit Output(s) Affected Description / Function 0 7 6 5 4 3 2 1 0 9 1 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE BYTE 20 (RESERVED FOR USER) Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Type Power On R R R R RW RW RW 409_410# FSC FSB FSA 0 0 0 RW 0 BYTE 21 Bit Output(s) Affected Description / Function 0 7 6 5 4 3 2 1 Reserved Reserved Test_scl On chip test mode Enable normal 0 Test_hiz CLK Outputs Enable normal 409_410# FSC latched value on power up FSB latched value on power up FSA latched value on power up BYTE 62 = 60h BYTE 63 = 13h ABSOLUTE MAXIMUM RATINGS(1) Symbol 1 Max Unit VDDA 3.3V Core Supply Voltage Description Min 4.6 V VDD 3.3V I/O Supply Voltage 4.6 V VIH 3.3V Input HIGH 4.6 V VID 3.3V Input LOW –0.5 TS Storage Temperature –65 +150 °C ESD Prot Input ESD Protection 2000 V V Human Body Model NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 10 SCLK=1, CLK outputs=1 SCLK=0, CLK outputs=0 CLK outputs=Tristate IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS 3.3V Input HIGH Voltage VDD 0.7 — VDD + 0.3 V VIL_FS 3.3V Input LOW Voltage VSS - 0.3 — 0.35 V IIH Input HIGH Current VIN = VDD –5 — 5 µA IIL1 Input LOW Current VIN = 0V, inputs with no pull-up resistors –5 — — µA IIL2 Input LOW Current VIN = 0V, inputs with pull-up resistors –200 — — µA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current All differential pairs driven — — 70 mA All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH Logic inputs — — 5 Output pin capacitance — — 6 X1 and X2 pins — — 5 Modulation Frequency(2) Triangular modulation 30 — 33 KHz TSU_PD# Stop response of all clocks after PD# assertion — — 100 ns Clock Stabilization(2,3) From VDD power-up or de-assertion of PD# to first clock — — 1.8 ms TRISE_PD#(2) Rise time of PD# — — 5 ns TFALL_PD#(2) Fall time of PD# — — 5 ns TSU_CPU(2) CPU output disable after CPU_Stop# assertion — — 60 ns TDRIVE_CPU_Stop#(2) CPU output enable after CPU_Stop# de-assertion — — 60 ns TSU_SRC(2) SRC output disable after CLKREQ# assertion — — 60 ns TDRIVE_SRC(2) SRC output enable after CLKREQ# de-assertion — — 60 ns FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 11 pF IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 1150 mV VLOW Voltage LOW(2) oscilloscope math function –300 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Long Accuracy(2,3) See TPERIOD Min. - Max. values –300 — 300 ppm 400MHz nominal / -0.5% spread 2.4993 — 2.5133 333.33MHz nominal / -0.5% spread 2.9991 — 3.016 266.66MHz nominal / -0.5% spread 3.7489 — 3.77 200MHz nominal / -0.5% spread 4.9985 — 5.0266 166.66MHz nominal / -0.5% spread 5.9982 — 6.032 133.33MHz nominal / -0.5% spread 7.4978 — 7.54 Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 100MHz nominal / -0.5% spread 9.997 — 10.0533 400MHz nominal / -0.5% spread 2.4143 — — 333.33MHz nominal / -0.5% spread 2.9141 — — 266.66MHz nominal / -0.5% spread 3.6639 — — 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 4.9135 5.9132 — — — — 133.33MHz nominal / -0.5% spread 7.4128 — — 100MHz nominal / -0.5% spread 9.912 — — mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps d-tR Rise Time Variation(2) — — 125 ps d-tF Fall Time Variation(2) — — 125 ps dT3 Duty Cycle(2) Skew, CPU[1:0](2) Skew, CPU2(2) 45 — — — — — 55 100 250 % — — 250 — — 85 — — — — 100 125 tSK3 Skew, Measurement from differential waveform VT = 50% SRC(2) Jitter, Cycle to Cycle, CPU[1:0](2) tJCYC-CYC Jitter, Cycle to Cycle, CPU2(2) Jitter, Cycle to Cycle, SRC(2) Measurement from differential waveform NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 12 ps ps IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - PCICLK Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol ppm TPERIOD Parameter Test Conditions Long Accuracy(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values Clock Period(2) — — 300 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 500 ps Min. Typ. Max. Unit — — 300 ppm 20.8257 — 20.834 ns IOL dT1 tJCYC-CYC Output LOW Current Duty Cycle(1) Jitter, Cycle to Cycle(1) mA NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS - 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1,2) See Tperiod Min. - Max. values Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — ppm TPERIOD IOL Output LOW Current mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % Jitter, Cycle to Cycle(1) VT = 1.5V — — 350 ps tJCYC-CYC NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 13 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) VOL IOH ppm TPERIOD IOL Min. Typ. Max. Unit — — 0 ppm 69.827 — 69.855 ns IOH = -1mA 2.4 — — V Output LOW Voltage(1) IOL = 1mA — — 0.4 V Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — Output LOW Current mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 1000 ps dT1 tJCYC-CYC Duty Cycle(1) Jitter, Cycle to Cycle(1) NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 14 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE PD, POWER DOWN PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches. PD CPU CPU# SRC SRC# PCI USB REF 0 Normal Normal Normal Normal 33MHz 48MHz 14.318MHz 1 IREF * 2 or float Float IREF * 2 or float Float Low Low Low PD ASSERTION t SU _PD# PD CPU 133M Hz C PU# 133M Hz SR C 100M Hz SR C# 100M Hz U SB 48M Hz PCI 33M Hz REF 14.31818 15 IDTCV136 PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400 COMMERCIAL TEMPERATURE RANGE PD DE-ASSERTION The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. tSTAB