IDTCV141PVG

IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 1-TO-8 DIFFERENTIAL CLOCK BUFFER IDTCV141 FEATURES: DESCRIPTION: • • • • • • • • The CV141 differential buffer is compliant with Intel DB800 specifications. It is intended to distribute the SRC (serial reference clock) as a companion chip to the main clock of the CK409, CK410/CK410M, CK410B, etc. PLL is off in bypass mode and has no clock detect. Compliant with Intel DB800 spec Eight differential clock pairs at 0.7V 50ps skew 50ps cycle-to-cycle jitter Programmable Bandwidth PLL bypass configurable Divide by 2 programmable Available in SSOP and TSSOP packages FUNCTIONAL BLOCK DIAGRAM OE_INV (1) (1) DIF_0 OE[7:0] SRC_STOP (1) DIF_0# Output Control DIF_1 DIF_1# PWRDWN DIF_2 DIF_2# SCL SM Bus Controller SDA DIF_3 Output Buffer DIF_3# DIF_4 SRC_DIV2# DIF_4# DIF_5 PLL/BYPASS# DIF_5# SRC_IN DIF_6 SRC_IN# DIF_6# DIV HIGH_BW# PLL DIF_7 DIF_7# LOCK NOTE: 1. See OE_INV table for active HIGH or active LOW. The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE OCTOBER 2005 1 © 2005 Integrated Device Technology, Inc. DSC 6738/19 IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description 3.3V Core Supply Voltage VDDIN 3.3V Logic Input Supply Voltage GND - 0.5 TSTG Storage Temperature SRC_DIV2# 1 48 VDD 2 47 VDDA VSSA VSS 3 46 IREF TAMBIENT Ambient Operating Temperature SRC_IN 4 45 LOCK TCASE Case Temperature SRC_IN# 5 ESD Prot Input ESD Protection 44 OE_7 (1) (1) OE_0 6 43 OE_4 (1) (1) OE_3 7 42 DIF_7 DIF_0 8 41 DIF_7# DIF_0# 9 40 OE_INV VSS 10 39 VDD VDD 11 38 DIF_6 DIF_1 12 37 DIF_6# DIF_1# 13 36 OE_6 (1) (1) OE_1 14 35 OE_5 (1) (1) OE_2 15 34 DIF_5 DIF_2 16 33 DIF_5# DIF_2# 17 32 VSS VSS 18 31 VDD Min VDDA –65 0 Max Unit 4.6 V 4.6 V +150 °C +70 °C +115 °C 2000 V Human Body Model NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OE_INV OE_[7:0] PWRDWN SRC_STOP VDD 19 30 DIF_4 DIF_3 20 29 DIF_4# DIF_3# 21 28 HIGH_BW# PLL/BPASS# 22 27 SRC_STOP (1) SCL 23 26 PWRDWN (1) SDA 24 25 VSS OE_INV = 0 Active HIGH Active LOW Active LOW OE_INV = 1 Active LOW Active HIGH Active HIGH HIGH_BW# SELECTION PLL BW PLL Peaking NOTE: 1. See OE_INV table for active HIGH or active LOW. HIGH_BW# = 0 Min. Typ. Max. 2 3 4 — 1 3 HIGH_BW#=1 Min. Typ. Max. 0.7 1 1.4 — 1 3 Unit MHz dB SSOP/ TSSOP TOP VIEW OE FUNCTIONALITY [OE_INV = 0] OE_[7:0] - Pin OE_[7:0] - SMBus bit 1 1 1 0 0 1 0 0 DIF_[7:0] Normal Tristate Tristate Tristate OE FUNCTIONALITY [OE_INV = 1] DIFF_[7:0]# Normal Tristate Tristate Tristate OE_[7:0] - Pin OE_[7:0] - SMBus bit 1 1 1 0 0 1 0 0 2 DIF_[7:0] Tristate Tristate Normal Tristate DIFF_[7:0]# Tristate Tristate Normal Tristate IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Name Type Pin # Description SRC_IN, SRC_IN# IN, DIF 4,5 0.7V differential SRC input DIF_[7:0], DIF_ [7:0]# OUT, DIF 8, 9, 12, 13, 16, 17, 20, 21, 29, 30, 33, 34, 37, 38, 41, 42 0.7V differential clock output OE[7:0] IN 6, 7, 14, 15, 35, 36, 43, 44 PWRDWN IN 26 3.3V LVTTL for power down (see OE_INV table) IREF IN 46 Reference current for differential output 3.3V LVTTL input for enabling differential outputs (see OE_INV table) LOCK OUT 45 HIGH, locked PLL/Bypass# IN 22 1 = PLL mode, 0 = bypass, PLL OFF HIGH_BW# IN 28 0 = HIGH BW, 1 = LOW BW (see HIGH_BW# Selection table) SRC_DIV2# IN 1 LOW = divide by 2 mode SRC_STOP IN 27 SRC stop (see OE_INV table) SCL IN 23 SMBus clock SDA I/O, Open Collector 24 SMBus data OE_INV IN 40 (see OE_INV table) INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start DCh Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master Description Start DCh Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start DDh Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop INDEX BYTE WRITE INDEX BYTE READ Setting bit[11:18] = starting address, bit[20:27] = 01h. Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. 3 IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE CONTROL REGISTERS BYTE 0 Bit Output(s) Affected 7 6 5 4 3 2 1 0 PowerDown dirve mode SRC_STOP# drive mode Reserved Reserved Reserved High_BW# PLL/Bypass# SRC_DIV2# Bit 7 6 5 4 3 2 1 0 Description/Function 0 1 Type Power On Driven Driven Tri-state Tri-state Logically AND with HW pin Logically AND with HW pin Logically AND with HW pin High band width Bypass Divided by 2 Low band width PLL mode Normal RW RW RW RW RW RW RW RW 0 0 0 0 0 1 1 1 Output(s) Affected Description/Function 0 1 Type Power On DIFF_7 DIFF_6 DIFF_5 DIFF_4 DIFF_3 DIFF_2 DIFF_1 DIFF_0 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 DIFF_7 DIFF_6 DIFF_5 DIFF_4 DIFF_3 DIFF_2 DIFF_1 DIFF_0 Free Running with SRC_STOP# Free Running with SRC_STOP# Free Running with SRC_STOP# Free Running with SRC_STOP# Free Running with SRC_STOP# Free Running with SRC_STOP# Free Running with SRC_STOP# Free Running with SRC_STOP# Free Free Free Free Free Free Free Free stopped stopped stopped stopped stopped stopped stopped stopped RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 BYTE 1 BYTE 2 BYTE 3 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description / Function 0 1 Type RW RW RW RW RW RW RW RW 4 Power On IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Description / Function 0 1 Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID Type Power On R R R R R R R R 0 0 0 0 0 1 0 1 BYTE 62 = 10h BYTE 63 = 14h ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V IIH Input HIGH Current VIN = VDD –5 — 5 µA IIL1 Input LOW Current VIN = 0V, inputs with no pull-up resistors IIL2 Input LOW Current VIN = 0V, inputs with pull-up resistors LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) Logic inputs Output pin capacitance 5 –5 — — µA –200 — — µA — — 7 nH — — — — 5 6 pF IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - DIF 0.7 CURRENT MODE DIFFERENTIAL PAIR Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Parameter(1) Symbol Test Conditions Min. Typ. Max. Unit mV VHIGH Voltage HIGH +150 — — VLOW Voltage LOW — — –150 VMAX Max Input Voltage — — 1150 VMIN Min Input Voltage –300 — — Crossing Voltage (abs) 250 — 550 mV VCROSS(ABS) Measurement on single-ended signal using absolute value mV tR Rise Time VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time VOL = 0.175V, VOH = 0.525V 175 — 700 ps d-tR Rise Time Variation — — 125 ps d-tF Fall Time Variation — — 125 ps dT3 Duty Cycle Measurement from differential waveform 45 — 55 % tSK3 Output Pin-to-Pin Skew VT = 50% — — 50 ps Measurement from differential waveform — — 50 ps tJCYC-CYC Jitter, Cycle to Cycle(2) NOTES: 1. Parameter is guaranteed by design, but not 100% production tested. 2. Bypass mode, additive. SRC_IN 0.7V AC TIMING CHARACTERISTICS Parameter(1) Symbol Min. Max. Unit Rising Edge Rate Rising Edge Rate 0.6 4 V/ns Falling Edge Rate Falling Edge Rate 0.6 4 V/ns VIH Differential Input HIGH Voltage +150 — mV VIL Differential Input LOW Voltage — –150 mV VCROSS Absolute Crossing Point Voltages 250 550 mV VMAX Absolute Maximum Input Voltage — +1.15 V VMIN Absolute Minimum Input Voltage –0.3 — V 45 55 % Duty Cycle SRC_IN Duty Cycle 6 IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE DIF AC TIMING CHARACTERISTICS PLL Bandwidth and Peaking Symbol TPROP,PLL TPROP, BYPASS TSKEW PLL bandwidth PLL bandwidth PLL Peaking TCCJITTER Duty cycle Duty cycle Parameter SRC_IN to DIF Propagation Delay, PLL Mode(1) SRC_IN to DIF Propagation Delay, Bypass Mode(1) DIF_[7:0] Pin to Pin Skew(1) HIGH_BW#=0 (high bandwidth)(1) HIGH_BW#=1 (low bandwidth)(1) PLL Peaking(1,2) Cycle to Cycle Jitter(1) PLL Mode(1) Bypass (assume input is 50%)(1) Min -250 2.5 — 2 0.7 — — 45 40 Typ — — — 3 1 1 — — — Max 250 4.5 250 4 1.4 3 50 55 60 Units ps ns ps MHz MHz dB pS % % NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. Measured at 3dB downpoint. OUTPUT CONTROL Symbol TDRIVE_PWRDWN TACTIVE_PWRDWN TACTIVE_OE TINACTIVE_OE Parameter CLK driven from PD De_Assertion CLK Toggling from PD De_Assertion CLK toggling from OE_[7:0] Assertion CLK Tri-stated from OE_[7:0] De_Assertion Min — — 2 2 Typ — — — — Max 300 1 6 6 Units μs ms Clock Periods Clock Periods PWRDWN (OE_INV = 0) SRC_STOP (OE_INV = 0) The PWRDWN signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion. The SRC_STOP signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of DIF# to be recognized as a valid assertion or deassertion. PWRDWN 1 0 DIF Normal Iref*2 or Float DIF# Normal Float SRC_STOP 1 0 PWRDWN (OE_INV = 1) PWRDWN 1 0 DIF Iref*2 or Float Normal DIF Normal Iref*6 or Float DIF# Normal Float SRC_STOP (OE_INV = 1) DIF# Float Normal SRC_STOP 1 0 7 DIF Iref*6 or Float Normal DIF# Float Normal IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE SRC STOP FUNCTIONALITY The SRC_STOP signal is an input controlling DIF[7:0] and DIF[7:0] # outputs. This signal can be asserted asynchronously. SRC_STOP is active high when OE_INV = HIGH (see OE_INV table). SRC_STOP = DRIVEN, PWRDWN = DRIVEN 1mS (1) SRC_Stop (1) PWRDWN DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP = TRISTATE, PWRDWN = DRIVEN 1mS (1) SRC_Stop (1) PWRDWN DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) NOTE: 1. The polarity depends on OE_INV. 8 IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE SRC_STOP = DRIVEN, PWRDWN = TRISTATE 1mS (1) SRC_Stop (1) PWRDWN DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP = TRISTATE, PWRDWN = TRISTATE 1mS (1) SRC_Stop (1) PWRDWN DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) NOTE: 1. The polarity depends on OE_INV. 9 IDTCV141 1-TO-8 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION XXX IDTCV Device Type XX Package X Grade 10 Blank Commercial Temperature Range (0°C to +70°C) PV PVG PA PAG Small Shrink Outline Package SSOP - Green Thin Small Shrink Outline Package TSSOP - Green 141 1-to-8 Differential Clock Buffer IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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