IDTCV146PVG

IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR FEATURES: DESCRIPTION: • One high precision PLL for CPU, with SSC and N programmable • One high precision PLL for SRC/PCI/SATA, SSC and N programmable • One high precision PLL for 96MHz/48MHz • Band-gap circuit for differential outputs • Supports spread spectrum modulation, down spread 0.5% • Supports SMBus block read/write, index read/write • Selectable output strength for REF • Allows for CPU frequency to change to a higher frequency for maximum system computing power • Enhanced capacitance on XTAL_IN and XTAL_OUT pins • Available in SSOP package IDTCV146 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. OUTPUTS: • 2*0.7V current –mode differential CPU CLK pair • 6*0.7V current –mode differential SRC CLK pair, one SATA_SRC pair • One CPU_ITP/SRC selectable CLK pair • 6*PCI, two free running, 33.3MHz • 1*96MHz, 1*48MHz • 2*REF KEY SPECIFICATIONS: • CPU/SRC CLK cycle to cycle jitter < 85ps • SATA CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 250ps FUNCTIONAL BLOCK DIAGRAM PLL1 SSC N Programmable XTAL_IN CPU CLK Output Buffers Stop Logic CPU[1:0] CPU_ITP/SRC6 XTAL Osc Amp IREF REF[1:0] XTAL_OUT ITP_EN SDATA SCLK SM Bus Controller SRC CLK Output Buffer Stop Logic PLL2 SSC N Programmable SRC[5:0] SATA_SRC PCI[5:0], PCIF[1:0] IREF VTT_PWRGD#/PD Control Logic 48MHz FSA.B.C 48MHz/96MHz Output BUffer PLL3 DOT96 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE APRIL 2005 1 © 2005 Integrated Device Technology, Inc. DSC-6749/4 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Min VDDA 3.3V Core Supply Voltage VDD 3.3V Logic Input Supply Voltage GND - 0.5 TSTG Storage Temperature PCI0 1 56 VDD_REF PCI1 2 55 REF0/FSC VDD_PCI GND_PCI 3 54 REF1/FSA TAMBIENT Ambient Operating Temperature 4 53 GND_REF TCASE Case Temperature PCI2 5 52 XTAL_IN ESD Prot Input ESD Protection PCI3 6 51 XTAL_OUT PCI4 7 50 SDAT PCI5 8 49 GND_PCI 9 48 SCL GND_CPU VDD_PCI 10 47 CPU0 *TEST_SEL/PCIF0 11 46 CPU0# ITP_EN/PCIF1 VDD48 12 45 VDD_CPU 13 44 CPU1 USB48/FSB 14 43 CPU1# GND48 15 42 IREF GND_A VDD_A ITP_EN 1 0 16 41 17 40 VTT_PWRGD#/PD 18 39 CPU_ITP/SRC6 SRC0 19 38 CPU_ITP#/SRC6# SRC0# 20 37 VDD_SRC SRC1 21 36 SRC5 SRC1# 22 35 SRC5# VDD_SRC 23 34 GND_SRC GND_SRC 24 33 SRC4 SRC2 25 32 SRC4# 26 31 SRC3 27 30 SRC3# SATA_SRC# 28 29 VDD_SRC V 4.6 V +150 °C +70 °C +115 °C 2000 V NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DOT96 SRC2# 0 Unit 4.6 Human Body Model DOT96# SATA_SRC –65 Max pin 38 CPUC2_ITP SRCC6 pin 39 CPUT_ITP SRCT6 TEST CLARIFICATION TABLE HW SW TEST_SEL/ TEST SELECT PCICLK_F0 BIT B6b6 OUTPUT 0 0 Normal 1 X Hi-Z 0 1 Hi-Z Comments Normal Operation Power-up with TEST_SEL =1 to enter test mode. Cycle power with TEST_SEL = 0 to disable test mode If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B6b6. Cycle power with TEST_SEL = 0 to disable test mode. * = Internal pull down SSOP TOP VIEW FREQUENCY SELECTION TABLE FSC, B, A CPU Mode, MHz SATA_SRC SRC[5:0] PCI USB DOT96 REF 101 100 100 100 33.3 48 96 14.318 001 133 100 100 33.3 48 96 14.318 011 166 100 100 33.3 48 96 14.318 010 200 100 100 33.3 48 96 14.318 000 266 100 100 33.3 48 96 14.318 100 333 100 100 33.3 48 96 14.318 110 400 100 100 33.3 48 96 14.318 111 Reserve 100 100 33.3 48 96 14.318 2 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Number Name Type 1 2 3 4 5 6 7 8 9 10 11 PCI0 PCI1 VDD_PCI VSS_PCI PCI2 PCI3 PCI4 PCI5 VSS_PCI VDD_PCI TEST_SEL/PCIF0 OUT OUT PWR GND OUT OUT OUT OUT GND PWR I/O 12 ITP_EN/PCIF1 I/O 13 14 15 16 17 18 VDD48 USB48 /FS_B VSS48 DOT96T DOT96C VTT_PWRGD#/PD PWR I/O GND OUT OUT IN 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 SRCT0 SRCC0 SRCT1 SRCC1 VDD_SRC VSS_SRC SRCT2 SRCC2 SRCT_SATA SRCC_SATA VDD_SRC SRCC3 SRCT3 SRCC4 SRCT4 VSS_SRC SRCC5 SRCT5 VDD_SRC CPUC2_ITP/ SRCC6 CPUT2_ITP/ SRCT6 VDD_A VSS_A IREF OUT OUT OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT OUT OUT GND OUT OUT PWR OUT OUT PWR GND OUT Description PCI clock PCI clock 3.3V GND PCI clock PCI clock PCI clock PCI clock GND 3.3V Test Select (sampled at VTT_PWRGD# assertion), see TEST_SEL table. PCI clock afterward, free running. Pin38, 39, CPU_ITP/SRC6 select (sampled on VTT_PWRGD# assertion), HIGH = CPU_2PCI clock. PCI clock afterward, running. 3.3V 48MHz clock/ FS_B input GND 96MHz 0.7V current mode differential clock output 96MHz 0.7V current mode differential clock output 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C, TEST_SEL and ITP_EN inputs, VTT_PWRGD# is low assertion/ After VTT_PWRGD# assertion, becomes a real-time input for asserting power down (active HIGH). Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock 3.3V GND Differential Serial reference clock Differential Serial reference clock SATA clock SATA clock 3.3V Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock GND Differential Serial reference clock Differential Serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRCC6. Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRCT6. 3.3V GND Reference current for differential output buffer 3 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONT.) Pin Number Name Type 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 VSS_CPU SCL SDA XTAL_OUT XTAL_IN VSS_REF REF1/ FSA REF0/ FSC VDD_REF OUT OUT PWR OUT OUT GND IN I/O OUT IN GND I/O I/O PWR Description Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output 3.3V Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output GND SM bus clock SM bus data Xtal output Xtal input GND 14.318 MHz reference clock output. CPU frequency selection at VTT_PWRGD# assertion. 14.318 MHz reference clock output. CPU frequency selection at VTT_PWRGD# assertion. 3.3V INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop INDEX BYTE WRITE INDEX BYTE READ Setting bit[11:18] = starting address, bit[20:27] = 01h. Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. 4 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CONTROL REGISTERS N PROGRAMMING PROCEDURE • • Use Index byte write. For N programming, the user only needs to access Byte17, Byte 25, and Byte8. 1. 2. 3. • • • Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17. Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f. Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly. Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang. Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming. Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according to each power on frequency selection. To avoid mistakes, don’t write on those byte (be careful about Block Write). It is suggested to use the Index Byte write to access bytes. FREQUENCY SELECTION TABLE SSC MAGNITUDE CONTROL, SMC SMC[2:0] 000 001 010 011 100 101 110 111 FS_C, B, A 101 001 011 010 000 100 110 111 -0.25 -0.5 -0.75 -1 ±0.125 ±0.25 ±0.375 ±0.5 RESOLUTION CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150 5 CPU 100 133 166 200 266 333 400 RESERVE IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 CPUT2, CPUC2/ SRCT6, SRCC6 Output enable Tristate Enable RW 1 6 5 4 3 2 1 0 SRCT5, SRCT4, SRCT3, SATAT, SRCT2, SRCT1, SRCT0, Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW 1 1 1 1 1 1 1 SRCC5 SRCC4 SRCC3 SATAC SRCC2 SRCC1 SRCC0 BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 Reserved DOT96T, DOT96C USB48 REF0 REF1 CPUT1, CPUC1 CPUT0, CPUC0 Spread Spectrum Output enable Output enable Output enable Output enable Output enable Output enable Spread Spectrum Enable Tristate Tristate Tristate Tristate Tristate Tristate Off Enable Enable Enable Enable Enable Enable On RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 PCIF1 PCIF0 Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 BYTE 2 BYTE 3 Bit Output(s) Affected 7 CPUT2, CPUC2/ SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 SRCT3, SRCC3 SATAT, SATAC SRCT2, SRCC2 SRCT1, SRCC1 SRCT0, SRCC0 6 5 4 3 2 1 0 Description / Function Free running, not affected by PCI/SRC_Stop bit (Byte6, bit3) 6 0 1 Type Power On Free-Running Stoppable RW 0 Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable RW RW RW RW RW RW RW 0 0 0 0 0 0 0 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Reserved DOT96 PCIF1 PCIF0 Reserved Reserved Reserved Reserved Description / Function 0 1 Type DOT96 power down drive mode Free running, not affected by PCI/SRC_Stop bit (Byte6, bit3) Driven in power down Free-Running Free-Running Tristate Stoppable Stoppable RW RW RW Power On 1 0 0 0 1 1 1 1 BYTE 5 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 0 Stopped SRC Reserved Reserved Reserved SRC CPU_ITP CPU1 CPU0 Drive Mode in PCI_Stop Driven Tristate RW SRC PWRDWN drive mode CPUT2 PWRDWN drive mode CPUT1 PWRDWN drive mode CPUT0 PWRDWN drive mode Driven in power down Driven in power down Driven in power down Driven in power down Tristate in power down Tristate in power down Tristate in power down Tristate in power down RW RW RW RW 0 0 0 0 0 0 0 0 Type Power On BYTE 6 Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 Reserved Test Select REF1 REF0 Reserved Test Select Strength Select Strength Select normal 1x 1x All CLK outputs Hi-Z 2x 2x FS_C latch read back FS_B latch read back FS_A latch read back 0 0 1 1 1 R R R BYTE 7 Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function 0 Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID 1 Type Power On 0 0 0 0 0 1 0 1 7 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 8 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRC SSC enable Only valid when Byte1 bit0 is 1 CPU PLL power down SRC PLL power down USB PLL power down USB 48 Strength control disable normal normal normal 1x enable Power down Power down Power down 2x N Programming enable Disable disable enable enable RW RW RW RW RW RW RW RW 1 0 0 0 0 0 0 0 Description / Function 0 1 Type Power On Must be 0 Must be 0 RW 0 (Must be 0) 0 0 1 0 0 0 1 USB48 Reserve One cycle read BYTE 9 Bit Output(s) Affected 7 6 5 4 3 2 1 0 CPU SMC2 CPU SMC1 CPU SMC0 Reserve SRC SMC2 SRC SMC1 SRC SMC0 RW RW RW RW RW RW RW see SMC table CPU PLL SSC control see SMC table SRC/PCI SSC control BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTE 17 Bit Output(s) Affected 7 6 5 4 3 2 1 0 CPU_N7, MSB CPU_N6 CPU_N5 CPU_N4 CPU_N3 CPU_N2 CPU_N1 CPU_N0, LSB Description / Function 0 1 Type RW RW RW RW RW RW RW RW see Resolution table CPU CLK = N* Resolution BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. 8 Power On IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 25 Bit Output(s) Affected 7 6 5 4 3 2 1 0 SRC_N7, MSB SRC_N6 SRC_N5 SRC_N4 SRC_N3 SRC_N2 SRC_N1 SRC_N0, LSB Description / Function 0 1 Type RW RW RW RW RW RW RW RW 100MHz N= 150 Resolution = 0.666667 SRC f = N*SRC Resolution BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. 9 Power On IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS LOW Voltage, HIGH Threshold For FSA.B.C test_mode 0.7 — VDD + 0.3 V VIL_FS LOW Voltage, LOW Threshold For FSA.B.C test_mode VSS - 0.3 — 0.35 V Input LeakageCurrent 0< VIN < VDD, no internal pull-up or pull-down –5 — +5 mA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current All differential pairs driven — — 70 mA All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH Logic inputs — — 5 Output pin capacitance — — 6 IIL FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB pF X1 and X2 pins — — 5 Clock Stabilization(2,3) From VDD power-up or de-assertion of PD# to first clock — — 1.8 ms Modulation Frequency(2) Triangular modulation 30 — 33 KHz TDRIVE_SRC(2) SRC output enable after PCI_Stop# de-assertion — — 15 ns TDRIVE_PD#(2) CPU output enable after PD# de-assertion — — 300 us TFALL_PD#(2) Fall time of PD# — — 5 ns TRISE_PD#(2) Rise time of PD# — — 5 ns TDRIVE_CPU_Stop#(2) CPU output enable after CPU_Stop# de-assertion — — 10 us TFALL_CPU_Stop#(2) Fall time of PD# — — 5 ns TRISE_CPU_Stop#(2) Rise time of PD# — — 5 ns NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 10 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 1150 mV VLOW Voltage LOW(2) oscilloscope math function –300 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Static Error(2,3) See TPERIOD Min. - Max. values — — 0 ppm 400MHz nominal / -0.5% spread 2.4993 — 2.5133 333.33MHz nominal / -0.5% spread 2.9991 — 3.016 266.66MHz nominal / -0.5% spread 3.7489 — 3.77 200MHz nominal / -0.5% spread 4.9985 — 5.0266 166.66MHz nominal / -0.5% spread 5.9982 — 6.032 133.33MHz nominal / -0.5% spread 7.4978 — 7.54 100MHz nominal / -0.5% spread 9.997 — 10.0533 96MHz nominal 10.4135 — 10.4198 400MHz nominal / -0.5% spread 2.4143 — — 333.33MHz nominal / -0.5% spread 2.9141 — — 266.66MHz nominal / -0.5% spread 3.6639 — — 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 4.9135 5.9132 — — — — 133.33MHz nominal / -0.5% spread 7.4128 — — 100MHz nominal / -0.5% spread 9.912 — — 10.1635 — — Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps — — 125 ps — 45 — — 125 55 ps % d-tR Rise Time Variation(2) d-tF dT3 Fall Time Variation(2) Duty Cycle(2) Measurement from differential waveform NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 11 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR, CONTINUED(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol tSK3 Parameter Skew, CPU[1:0](2) Skew, CPU2(2) Skew, tJCYC-CYC Test Conditions VT = 50% SRC(2) Jitter, Cycle to Cycle, CPU[1:0](2) Jitter, Cycle to Cycle, CPU2(2) Measurement from differential waveform SRC(2) Jitter, Cycle to Cycle, Jitter, Cycle to Cycle, DOT96(2) Min. — — Typ. — — Max. 100 250 — — 250 — — 85 — — 100 — — — — 125 250 Unit ps ps NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol Parameter Test Conditions ppm Static Error(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values TPERIOD Clock Period(2) — — 0 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 IOL Output LOW Current VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 500 ps VT = 1.5V — — 500 ps Cycle(1) dT1 Duty tSK1 Skew(1) tJCYC-CYC Jitter, Cycle to Cycle(1) NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 12 mA IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS, 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions ppm Static Error(1,2) See Tperiod Min. - Max. values TPERIOD Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage VOL IOH IOL Min. Typ. Max. Unit — — 0 ppm 20.8257 — 20.834 ns IOH = -1mA 2.4 — — V Output LOW Voltage IOL = 1mA — — 0.55 V Output HIGH Current VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — Output LOW Current mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % — — 350 ps Min. Typ. Max. Unit — — 0 ppm 69.827 — 69.855 ns tJCYC-CYC Jitter, Cycle to Cycle NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) IOH = -1mA 2.4 — — V VOL Output LOW Voltage(1) IOL = 1mA — — 0.4 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — ppm TPERIOD IOL Output LOW Current mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % Jitter, Cycle to Cycle(1) VT = 1.5V — — 1000 ps tJCYC-CYC NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 13 IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PCI STOP FUNCTIONALITY If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit. PCI_STOP (Byte 6 bit 3) CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 1 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz 0 Normal Normal IREF * 6 or float Low Low 48MHz Normal Normal 14.318MHz PD, POWER DOWN PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches. PWRDWN CPU CPU# SRC SRC# PCIF/PCI USB 0 Normal 1 IREF * 2 or float Normal Normal Normal 33MHz Float IREF * 2 or float Float Low PD ASSERTION PWRDWN CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 14 DOT96 DOT96# REF 48MHz Normal Normal 14.318MHz Low IREF * 2 or float Float Low IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD DE-ASSERTION The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. tSTABLE