IDTCV174CPAG

IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV174C DESCRIPTION: FEATURES: IDTCV174C is a 56 pin clock device, incorporating Intel CK505 requirements for the Intel advance P4 processor. The CPU output buffer is designed to support up to 400MHz reference clock for the CPU. This chip has three PLLs inside for CPU, SRC/PCI and 48MHz/DOT96 IO clocks. • Compliant with Intel CK505 • Power management control suitable for low power applications • One high precision PLL for CPU/SRC/PCI, SSC and N programming • One high precision PLL for SRC/PCI, SSC and N programming • One high precision PLL for 96MHz/48MHz • Push-pull IOs for differential outputs • Support spread spectrum modulation, –0.5 down spread and others • Support SMBus block read/write, index read/write • Selectable output strength • Smooth transition for N programming • Available in SSOP and TSSOP packages OUTPUTS: • • • • • • • • KEY SPECIFICATIONS: • CPU/SRC CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 500ps 2*0.7V differential CPU CLK pair 7*0.7V differential SRC CLK pair One CPU_ITP/SRC differential clock pair One SRC0/DOT96 differential clock pair 6*PCI, 33.3MHz 1*48MHz 1*REF 1*SATA FUNCTIONAL BLOCK DIAGRAM REF XTAL_IN XTAL Osc Amp XTAL_OUT PLL1 SSC N Programmable CPU[1:0] CPU, SRC, PCI Output Buffer Stop Logic CPU_ITP/SRC8 SDATA SCLK SM Bus Controller PLL3 SSC N Programmable SRC CLK Output Buffer Stop Logic SRC[7:1] PCI[4:0], PCIF5 SATA CKPRWGD/PD# CPU_STOP# PCI_STOP# Control Logic SRC5_EN, LTE 48MHz Fixed PLL PLL2 ITP_EN 48MHz/96MHz Output BUffer DOT96/SRC0 CR#_[F:A] FSC,B,A The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2006 1 © 2005 Integrated Device Technology, Inc. DSC 6898/8 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION PCI0/CR#_A 1 56 SCL SDA VDD_PCI 2 55 PCI1/CR#_B 3 54 REF/FSC/TEST_SEL PCI2//LTE 4 53 VDD_REF PCI3 5 52 XTAL_IN PCI4/SRC5_EN 6 51 XTAL_OUT PCIF5/ITP_EN 7 50 VSS_REF VSS_PCI 8 49 FSB/TEST_MODE VDD_48MHz 9 48 CKPWRGD/PD# USB_48/FSA 10 47 VDD_CPU VSS_48MHz 11 46 CPUT0 VDD_IO 12 45 CPUC0 SRCT0/DOT96T 13 44 VSS_CPU SRCC0/DOT96C 14 43 CPUT1 VSS_IO 15 42 CPUC1 VDD_PLL3 16 41 VDD_CPU_IO SRCT1/SE1 17 40 IO_VOUT SRCC1/SE2 18 39 SRCT8/CPU_ITPT VSS_PLL3 19 38 SRCC8/CPU_ITPC VDD_PLL3_IO 20 37 VDD_SRC_IO SATAT/SRCT2 21 36 SRCT7/CR#_F SATAC/SRCC2 22 35 SRCC7/CR#_E VSS_SRC 23 34 VSS_SRC SRCT3/CR#_C 24 SRCT6 SRCC3/CR#_D 25 33 32 VDD_SRC_IO 26 31 VDD_SRC SRCT4 27 30 PCI_STOP#/SRCT5 SRCC4 28 29 CPU_STOP#/SRCC5 TSSOP TOP VIEW 2 SRCC6 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin # 1 Name PCI0/CR#_A Type I/O 2 3 VDD_PCI PCI1/CR#_B PWR I/O 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCI2/LTE PCI3 PCI4/SRC5_EN PCIF5/ITP_EN VSS_PCI VDD_48 USB 48/FS_A VSS_48 VDD_IO SRCT0/DOT96T SRCC0/DOT96C VSS_IO VDD_PLL3 SRCT1/SE1 SRCC1/SE2 VSS_PLL3 VDD_PLL3_IO SRCT2/SATAT SRCC2/SATAC VSS_SRC SRCT3/CR#_C I/O OUT I/O I/O GND PWR I/O GND PWR OUT OUT GND PWR OUT OUT GND PWR OUT OUT GND I/O 25 SRCC3/CR#_D I/O 26 27 28 29 30 31 32 33 34 35 VDD_SRC_IO SRCT4 SRCC4 CPU_Stop#/SRCC5 PCI_Stop#/SRCT5 VDD_SRC SRCC6 SRCT6 VSS_SRC SRCC7/CR#_E PWR OUT OUT I/O I/O PWR OUT OUT GND I/O 36 SRCT7/CR#_F I/O 37 38 39 VDD_SRC_IO SRCC8/CPU_ ITPC SRCT8/CPU_ ITPT PWR OUT OUT Description 33.33MHz/SRC0, 2 Differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode is selected by SMBus control register. Default is PCI clock mode 3.3V 33.33MHz/SRC1, 2 Differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode is selected by SMBus control register. Default is PCI clock mode 33.33MHz. High = overclocking disabled. Power-on latch. 33.33MHz 33.33MHz. Pin 29, 30 mode selection. Power on latch, high = SRC5, low = CPU and PCI Stop# 33.33MHz. Pin 38, 39 mode selection. Power on latch, high = CPU_ITP, low = SRC8 GND 3.3V 48MHz/ Frequency select, power on latch GND 0.8V Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0 Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0 GND 3.3V Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1. Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1 GND 0.8V Differential output clock Differential output clock GND SRC clock/ SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by SMBus control register. Default is SRC3. SRC clock/ SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by SMBus control register. Default is SRC3.. 0.8V Differential output clock Differential output clock CPU stop, low = stop/ SRC clock. Mode selected by pin6, SRC5_EN. PCI stop, low = stop/ SRC clock. Mode selected by pin6, SRC5_EN. 3.3V Differential output clock Differential output clock GND SRC clock/ SRC differential clock output enable, control SRC6, 0 = enable. Mode selected by SMBus control register. Default is SRC7. SRC clock/ SRC differential clock output enable, control SRC8, 0 = enable. Mode selected by SMBus control register. Default is SRC7. 0.8V SRC clock/CPU clock. Mode selected by pin7. SRC clock/CPU clock. Mode selected by pin7. 40 IO_VOUT OUT V_IO adjustment 3 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION, CONTINUED Pin # 41 42 43 44 45 46 47 48 Name VDD_CPU_IO CPUC1 CPUT1 VSS_CPU CPUC0 CPUT0 VDD_CPU CKPWRGD/PD# Type PWR OUT OUT GND OUT OUT PWR IN 49 50 51 52 53 54 FS_B/TestMode VSS_REF XTAL_OUT XTAL_IN VDD_REF REF/FS_C/TestSel IN GND OUT IN PWR I/O 55 56 SDA SCL I/O IN Description 0.8V Differential output clock Differential output clock GND Differential output clock Differential output clock 3.3V CKPWRGD power good, active LOW, used to latch FSA,B,C, ITP_EN, TME, and SRC5_EN , active HIGH. After, becomes power down, LOW active. Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table GND XTAL out XTAL in 3.3V 14.318MHz. Frequency Select at CKPWRGD assertion. Selects test mode if pulled above 2V at CKPWRGD assertion. SMBus clock SMBus data TEST MODE SELECTION(1) If TEST_SEL sampled above 2V at CKPWRGD active LOW Test_Mode CPU SRC PCI/F REF DOT_96/DOT_SSC USB 1 REF/N REF/N REF/N REF REF/N REF/N 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NOTE: 1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with VIH_FS and VIL_FS threshoulds. FREQUENCY SELECTION FSC, B, A CPU SRC[7:0] PCI USB DOT REF 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 Reserve 100 33.3 48 96 14.318 4 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Min RESOLUTION Max Unit VDDA 3.3V Core Supply Voltage 4.6 V VDD 3.3V Logic Input Supply Voltage GND - 0.5 4.6 V TSTG Storage Temperature TAMBIENT Ambient Operating Temperature TCASE Case Temperature ESD Prot Input ESD Protection –65 +150 °C 0 +70 °C +115 °C 2000 CPU CPU CPU CPU CPU CPU CPU SRC V Human Body Model NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. = 100MHz = 133MHz = 166MHz = 200MHz = 266MHz = 333MHz = 400MHz = 100MHz N Resolution (MHz) 0.500000 0.666667 0.666667 1.000000 1.333333 1.333333 2.000000 0.500000 % 0.5% 0.5% 0.4% 0.5% 0.5% 0.4% 0.5% 0.5% N= 200 200 250 200 200 250 200 200 SM PROTOCOL INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit 30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master 5 Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PLL3 CONFIG TABLE(1) PLL#_CFB[3,2,1,0] Comments 0000 PLL3 Disabled PLL3 off, SRC1 = SRC_Main 0001 100MHz 0.5% SSC Stby PLL3 on, SRC1 = SRC_Main 0010 100MHz 0.5% SSC only SRC1 sourced from PLL3 0011 100MHz 1.0% SSC only SRC1 sourced from PLL3 0100 100MHz 1.5% SSC only SRC1 sourced from PLL3 0101 100MHz 2.0% SSC only SRC1 sourced from PLL3 0110 100MHz 2.5% SSC only SRC1 sourced from PLL3 0111 Reserved Reserved 1000 1394A 3.3V only 1394A on SE1 and SE2 1001 1394A&B 3.3V only 1394A on SE1, 1394B on SE2 1010 1394B 3.3V only 1394B on SE1 and SE2 1011 27MHz, 3.3V only 27MHz on SE1 and SE2 1100 25MHz 3.3V only 25MHz on SE1 and SE2 1101 Reserved Reserved 1110 Reserved Reserved 1111 Reserved Reserved NOTE: 1. PLL3 spread depend on byte4 bit0 and byte1 bit5, default -0.5%. IO_VOUT [2:0] TABLE DEVICE ID TABLE ID3,ID2,ID1,ID0 Comments 000 0.3V 0000 CK505 56 pin TSSOP CK505 YC 001 0.4V 0001 CK505 64 pin TSSOP CK505 YC 010 0.5V 0010 48 pin QFN CK505 YC 011 0.6V 0011 56 pin QFN CK505 YC 100 0.7V 0100 64 pin QFN CK505 YC 101 0.8V 0101 72 pin QFN CK505 YC 110 0.9V CK505 YC 111 1V 0110 48 pin SSOP 0111 56 pin SSOP CK505 YC 1000 Reserved CK505 Derivative (non YC) 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved IB1, IB0 CPU Frequency 1101 Reserved 01 (N + 0.3333) * resolution 1110 Reserved 10 (N + 0.6666) * resolution Reserved 00, 11 N * resolution 1111 IB TABLE 6 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE N-PROGRAMMING PROCEDURE CPU 1. Power on CPU frequency = 200MHz. Resolution corresponding to 200MHz is 1.0 2. To change CPU frequency from 200MHz to 100MHz, divide 100 by 1.0(100 / 1.0 = 100 [decimal] = 64 [hex]). 3. Program Byte 17 with 64h. CPU frequency changes from 200MHz to 100MHz. SRC 1. Power on SRC frequency = 100MHz. 2. To change SRC frequency from 100MHz to 50MHz, divide 50 by 0.5 (50 / 0.5 = 100 [decimal] = 64 [hex]). 3. Program Byte 18 with 64h. SRC frequency changes from 100MHz to 50MHz. CONTROL REGISTERS BYTE 0 Bit Output(s) Affected Description/Function 7 6 5 4 3 2 FSC FSB FSA iAMT_EN Reserved SRC_SEL Latched FSC Latched FSB Latched FSA iAMT Mode 1 0 SATA_SEL PD_Restore SRC clock source SATA source SMBUS control registers setting after the power down 0 1 Type Power On Legacy Mode Enabled R R R RW PLL1, PLL3_CFG table applies SRC_main Power on default PLL3, PLL3_CFG table not applicable PLL2(2) Save register contents RW Latched Value Latched Value Latched Value HW M1 setting(1) 0 0 RW RW 0 1 NOTES: 1. Sticky 1, can only be reset by power off. 2. 100MHz, no SSC. BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRC0_sel PLL1_SSC_DC PLL3_SSC_DC PLL3_CFB3 PLL3_CFB2 PLL3_CFB1 PLL3_CFB0 PCI Pin13/14 mode select SSC mode selection SSC mode selection SRC0 Down spread Down spread DOT96 Center spread Center spread Only valid if Byte0 bit2 = 0 See PLL3_CFB table, configure pin17, 18 output mode PCI select PLL1 SRC, as byte0 bit2 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 1 1 BYTE 2 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 REF USB_48 PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 7 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 3 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Reserved Reserved Reserved SRC8/ITP SRC7 SRC6 SRC5 SRC4 Description/Function 0 Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate 1 Type Power On Enabled Enabled Enabled Enabled Enabled RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 BYTE 4 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 SRC3 SATA/SRC2 SRC1 SRC0/DOT96 CPU1 CPU0 PLL1_SSC_ON PLL3_SSC_ON Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable SSC Enable SSC Enable Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 CR#_A CR#_A control CR#_B CR#_B control CR#_C CR#_C control CR#_D CR#_D control Pin1 mode selection CR#_A control selection Pin3 mode selection CR#_B control selection Pin24 mode selection CR#_C control selection Pin25 mode selection CR#_D control selection PCI0 mode SRC0 PCI1mode SRC1(1) SRCT3 mode SRC0 SRCC3 mode SRC1 CR#_A mode SRC2 CR#_B mode SRC4 CR#_C mode SRC2 CR#_D mode SRC4 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 BYTE 5 NOTE: 1. Only when SRC1 is SRC Clock. BYTE 6(1) Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 CR#_E CR#_F Reserved Reserved Reserved Reserved SSCD_STP_CRTL SRC_STP_CRTL Pin 35 mode selection, control SRC6 Pin 36 mode selection, control SRC8 SRCC7 mode SRCT7 mode CR#_E mode CR#_F mode If set, SSCD stop with PCI_STOP# If set, SRCs stop with PCI_STOP# Free running Free running Stoppable Stoppable RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 NOTE: 1. STOP - CPUT and SRCT stay high, CPUC and SRCC stay low. 8 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 7 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Description / Function 0 1 Type Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID Power On 0 0 0 0 0 1 0 1 BYTE 8 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Device_ID3 Device_ID2 Device_ID1 Device_ID0 SE1_OE SE2_OE Description / Function 0 1 Type Power On Enabled Enabled R R R R RW RW RW RW 0 0 0 0 0 1 Type Power On Free running normal 1x Hi-Z Normal operation stoppable No overclocking 2x REF/N mode Test mode, controlled by byte9 bit 4 RW R RW RW RW 0 0 1 0 0 RW RW RW 1 0 1 See device ID table Output Enable Output Enable Disabled Disabled BYTE 9 Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function PCIF5 with PCI_STOP# Free running LTE_STRAP Over-clocking Enable (N programming) REF Drive Strength Strength control Only valid when Byte9 bit3 is 1 Test Mode entry control IO_VOUT2 IO_VOUT1 IO_VOUT0 Programmable IO_VOUT voltage BYTES 10 + 11 - RESERVED BYTE 12 - BYTE COUNT - DEFAULT 0x0D BYTE 13 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 0 48M REF PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Strength control Strength control Strength control Strength control Strength control Strength control Strength control Strength control 1 1 1 1 1 1 1 1 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 9 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 14 Bit Output(s) Affected 7 6 5 4 3 2 1 0 SRC skew selection Reserved Reserved SRC3, 4, 5, 6 SRC2, 7, 8 CPU strength SRC0/ DOT strength SRC1/ PLL3CLK Strength Description / Function Strength (output impedance) Strength Strength Strength Strength 0 1 Type Power On 250ps 400ps 17Ω 17Ω 17Ω 17Ω 17Ω 25Ω 25Ω 25Ω 25Ω 25Ω RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 1 Enabled Hard and Soft Alarm Alarm Alarm 1160ms base Type RW RW R R RW RW RW RW Power On 0 0 BYTE 15, WATCH DOG(1) Bit 7 6 5 4 3 2 1 0 Output(s) Affected Watch Dog Enable Watch Dog Select Watch Dog Hard Alarm Status Watch Dog Soft Alarm Status Watch Dog control WD_1_ Timer 2 WD_1_ Timer 1 WD_1_ Timer 0 Description / Function 0 Watch Dog Alarm Enable Disabled Watch Dog Hard/Soft Alarm Select Hard Alarm Only Watch Dog Hard Alarm Status Normal Watch Dog Soft Alarm Status Normal Watch Dog Time Base Control 290ms base WatchDog_1_Alarm Timer Default is 7*290ms 0 1 1 1 NOTE: 1. Hard Alarm switch to HW FS frequency. BYTE 16 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 WDEAPD Set Byte15 bit7 = 1 after Power Down to enable the watch dog after the power down Disabled Enabled RW 0 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved IB1 IB0 CPUN8 RW RW RW RW RW RW RW 0 0 0 0 0 0 FS latch Type Power On Increment bit1, fine tune CPU frequnecy Increment bit0 See IB table See IB table BYTE 17 (PLL1) Bit Output(s) Affected 7 6 5 4 3 2 1 0 CPUN7 CPUN6 CPUN5 CPUN4 CPUN3 CPUN2 CPUN1 CPUN0 Description / Function 0 1 RW RW RW RW RW RW RW RW CPU frequency = N*Resolution (see Resolution table, N-Programming Procedure) 10 FS latch IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 18 (PLL3) Bit 7 6 5 4 3 2 1 0 Output(s) Affected PN PN PN PN PN PN PN PN 7 6 5 4 3 2 1 0 Description / Function 0 1 Type RW RW RW RW RW RW RW RW SRC frequency = N*Resolution (see Resolution table, N-Programming Procedure) Power On 100MHz BYTE 19, CLOCK SOURCE SELECTION, WRITEN AFTER STOP BIT Bit Output(s) affected 7 CPU MODE Control 6 5 4 SFSC SFSB SFSA 3 N programming enable enable disable RW SRC1 source controlled by PLL3_CFB[3:0] PLL2 RW 0 PCI source Reserv ed and byte0 bit2 Follow by te1 bit0 - PLL2 - RW - 0 0 2 1 0 Description/ Function Will be reset to O during the Hard Alarm 0 CPU Mode is based on Hardware SFS - 11 1 CPU Mode is based on SFS Type Power On RW 0 RW RW RW LATCH Latch Latch Power on LTE latch IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE DC OPERATING CHARACTERISTICS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol VDD_3.3 Parameter Supply VoltageOperating Supply Current Test Conditions Min. Max. Unit 5% 3.125 3.465 V VIH Input HIGH Voltage (SE)(1) 2 VDD + 0.3 V VIL Input LOW Voltage (SE)(1) VSS - 0.3 0.8 V VIH_FS_Test Input HIGH Voltage (SE)(2) 2 VDD + 0.3 V VIH_FS_Normal Input HIGH Voltage (FS)(2) 0.7 1.5 V VIL_FS_Normal Input LOW Voltage (FS)(2) VSS - 0.3 0.35 V Input LeakageCurrent(3) 0 < VIN < VDD –5 +5 µA VOH Output HIGH Voltage (SE)(4) IOH = –1 mA 2.4 — V VOL Output LOW Voltage (SE)(4) IOL = 1 mA — .4 V LOW Voltage Differential 0.72 0.88 V CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance — 6 pF IDD_CFG1_3.3V Operating Supply Current, default configuration — 250 mA IDD_CFG2_3.3V Operating Supply Current, PLL3 differential out — 250 mA IDD_CFG3_3.3V Operating Supply Current, PLL3 single-ended out — 250 mA Differential IO Current, all outputs enabled 25 80 mA IDD_PWRDWN_3.3V Power Down Supply Current — 1 mA IDD_PWRDWN_0.8V Power Down Supply Current — 0.1 mA IDD_M1_3.3V MT Mode Supply Current — 25 mA IDD_M1_0/8V MT Mode Supply Current — 0.8 mA IIL VDD_IO IDD_IO_O.8V NOTES: 1. All inputs referenced to 3.3V power suppply. 2. Frequency select inputs which have tri-level input. 3. Input leakage current does not include inputs with pull-up or pull-down resistors. 4. Signal edge is required to be monotonic when transitioning through this region. 12 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Test Conditions Min. Typ. Max. Unit Statistical measurement on single-ended signal using 660 — 850 mV oscilloscope math function –150 — +150 — — 1150 Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Static Error(2,3) See TPERIOD Min. - Max. values — — 0 ppm 400MHz nominal / -0.5% spread 2.4993 — 2.5133 333.33MHz nominal / -0.5% spread 2.9991 — 3.016 266.66MHz nominal / -0.5% spread 3.7489 — 3.77 200MHz nominal / -0.5% spread 4.9985 — 5.0266 166.66MHz nominal / -0.5% spread 5.9982 — 6.032 133.33MHz nominal / -0.5% spread 7.4978 — 7.54 100MHz nominal / -0.5% spread 9.997 — 10.0533 96MHz nominal 10.4135 — 10.4198 400MHz nominal / -0.5% spread 2.4143 — — 333.33MHz nominal / -0.5% spread 2.9141 — — 266.66MHz nominal / -0.5% spread 3.6639 — — 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 4.9135 5.9132 — — — — 133.33MHz nominal / -0.5% spread 7.4128 — — 100MHz nominal / -0.5% spread 9.912 — — 10.1635 — — VHIGH Voltage HIGH(2) VLOW Voltage LOW(2) VOVS Max Voltage(2) Measurement on single-ended signal using absolute value VUDS ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps — — 125 ps — 45 — — 125 55 ps % d-tR Rise Time Variation(2) d-tF dT3 Fall Time Variation(2) Duty Cycle(2) Measurement from differential waveform NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 13 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR, CONTINUED(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol tSK3 Parameter Skew, CPU[1:0](2) Skew, CPU2(2) Skew, tJCYC-CYC Test Conditions VT = 50% SRC(2) Jitter, Cycle to Cycle, CPU[1:0](2) Jitter, Cycle to Cycle, CPU2(2) Measurement from differential waveform SRC(2) Jitter, Cycle to Cycle, Jitter, Cycle to Cycle, DOT96(2) Min. — — Typ. — — Max. 100 250 — — 250 — — 85 — — 100 — — — — 125 250 Unit ps ps NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol Parameter Test Conditions ppm Static Error(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values TPERIOD Clock Period(2) — — 0 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — IOL Output LOW Current mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 250 ps VT = 1.5V — — 500 ps Cycle(1) dT1 Duty tSK1 Skew(1) tJCYC-CYC Jitter, Cycle to Cycle(1) NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 14 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS, 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions ppm Static Error(1,2) See Tperiod Min. - Max. values TPERIOD Clock Period(2) 48MHz output nominal Min. Typ. Max. Unit — — 0 ppm 20.8257 — 20.834 ns VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — IOL Output LOW Current mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns VT = 1.5V 45 — 55 % — — 350 ps Min. Typ. Max. Unit — — 0 ppm 69.827 — 69.855 ns dT1 tJCYC-CYC Duty Cycle(1) Jitter, Cycle to Cycle NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) IOH = -1mA 2.4 — — V VOL Output LOW Voltage(1) IOL = 1mA — — 0.4 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — ppm TPERIOD IOL Output LOW Current mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 1000 ps dT1 tJCYC-CYC Duty Cycle(1) Jitter, Cycle to Cycle(1) NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 15 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE MISC. AC TIMING REQUIREMENTS Symbol Min. Max. Unit All Clock Stabilization from Power-Up — 200mV 18 IDTCV174C PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD# ASSERTION PD# CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 PD# DE-ASSERTION tSTABLE