DAC1001D125
Dual 10-bit DAC, up to 125 Msps
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The DAC1001D125 is a dual-port high-speed 2-channel CMOS Digital-to-Analog
Converter (DAC), optimized for high dynamic performance with low power dissipation.
The Supporting an update rate of up to 125 Msps, the DAC1001D125 is suitable for Direct
IF applications.
Separate write inputs allow data to be written to the two DAC ports independently of one
another. Two separate clocks control the update rate of each DAC port.
The DAC1001D125 can interface two separate data ports or one single interleaved
high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its
original I and Q data and latched. The I and Q data is then converted by the two DACs
and updated at half the input data rate.
Each DAC port has a high-impedance differential current output, suitable for both
single-ended and differential analog output configurations.
The DAC1001D125 is pin compatible with the AD9763, DAC2900 and DAC5652.
2. Features and benefits
Dual 10-bit resolution
125 Msps update rate
Single 3.3 V supply
Typical 185 mW power dissipation
16 mW power-down
SFDR: 80 dBc; fo = 1 MHz;
fs = 52 Msps
Dual-port or Interleaved data modes
SFDR: 77 dBc; fo = 10.4 MHz; fs = 78
Msps
1.8 V, 3.3 V and 5 V compatible digital SFDR: 72 dBc; fo = 1 MHz;
inputs
fs = 52 Msps; 12 dBFS
Internal and external reference
LQFP48 package
2 mA to 20 mA full-scale output current Industrial temperature range of
40 C to +85 C
3. Applications
Quadrature modulation
Medical/test instrumentation
Direct IF applications
Direct digital frequency synthesis
Arbitrary waveform generator
®
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
4. Ordering information
Table 1.
Ordering information
Type number
DAC1001D125HL
Package
Name
Description
Version
LQFP48
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm
SOT313-2
5. Block diagram
DA9 to DA0
10
INPUT A
LATCH
10
DAC A
LATCH
10
DAC
A
WRTA/IQWRT
DAC1001D125
CONTROL
AMPLIFIER
CLKB/IQRESET
10
VDDA
INPUT B
LATCH
AGND
10
VDDD
DAC B
LATCH
DGND
BVIRES
GAINCTRL
10
DAC
B
IOUTBP
IOUTBN
001aai947
Block diagram
DAC1001D125 3
Product data sheet
AVIRES
PWD
WRTB/IQSEL
Fig 1.
IOUTAN
REFIO
REFERENCE
CLKA/IQCLK
DB9 to DB0
IOUTAP
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
2 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
6. Pinning information
37 PWD
38 AGND
39 IOUTBP
40 IOUTBN
41 BVIRES
42 GAINCTRL
43 REFIO
44 AVIRES
45 IOUTAN
46 IOUTAP
DA9
1
36 n.c.
DA8
2
35 n.c.
DA7
3
34 n.c.
DA6
4
33 n.c.
DA5
5
32 DB0
DA4
6
DA3
7
DA2
8
29 DB3
DA1
9
28 DB4
DA0 10
27 DB5
n.c. 11
26 DB6
n.c. 12
25 DB7
31 DB1
DB8 24
DB9 23
30 DB2
VDDD 22
DGND 21
WRTB/IQSEL 20
CLKB/IQRESET 19
CLKA/IQCLK 18
WRTA/IQWRT 17
VDDD 16
DGND 15
n.c. 14
DAC1001D125HL
n.c. 13
Fig 2.
47 VDDA
48 MODE
6.1 Pinning
001aai945
Pin configuration SOT313-2 (LQFP48)
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type[1]
Description
DA9
1
I
DAC A, data input bit 9 (MSB)
DA8
2
I
DAC A, data input bit 8
DA7
3
I
DAC A, data input bit 7
DA6
4
I
DAC A, data input bit 6
DA5
5
I
DAC A, data input bit 5
DA4
6
I
DAC A, data input bit 4
DA3
7
I
DAC A, data input bit 3
DA2
8
I
DAC A, data input bit 2
DA1
9
I
DAC A, data input bit 1
DA0
10
I
n.c.
11
not connected
n.c.
12
not connected
n.c.
13
not connected
DAC A, data input bit 0 (LSB)
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
3 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
Table 2.
Pin description …continued
Symbol
Pin
n.c.
14
DGND
15
Type[1]
Description
not connected
G
digital ground
VDDD
16
S
digital supply voltage
WRTA/IQWRT
17
I
input write port A/input write IQ in Interleaved mode
CLKA/IQCLK
18
I
input clock port A/input clock IQ in Interleaved mode
CLKB/IQRESET
19
I
input clock port B/reset IQ in Interleaved mode
WRTB/IQSEL
20
I
input write port B/select IQ in Interleaved mode
DGND
21
G
digital ground
VDDD
22
S
digital supply voltage
DB9
23
I
DAC B, data input bit 9 (MSB)
DB8
24
I
DAC B, data input bit 8
DB7
25
I
DAC B, data input bit 7
DB6
26
I
DAC B, data input bit 6
DB5
27
I
DAC B, data input bit 5
DB4
28
I
DAC B, data input bit 4
DB3
29
I
DAC B, data input bit 3
DB2
30
I
DAC B, data input bit 2
DB1
31
I
DAC B, data input bit 1
DB0
32
I
n.c.
33
not connected
n.c.
34
not connected
n.c.
35
not connected
n.c.
36
PWD
37
I
power-down mode
AGND
38
S
analog ground
IOUTBP
39
O
DAC B current output
DAC B, data input bit 0 (LSB)
not connected
IOUTBN
40
O
complementary DAC B current output
BVIRES
41
I
adjust DAC B for full-scale output current
GAINCTRL
42
I
gain control mode
REFIO
43
I/O
reference I/O
AVIRES
44
I
adjust DAC A for full-scale output current
IOUTAN
45
O
complementary DAC A current output
IOUTAP
46
O
DAC A current output
VDDA
47
S
analog supply voltage
MODE
48
I
select between Dual-port or Interleaved mode
[1]
Type description: S = Supply; G = Ground; I = Input; O = Output; I/O = Input/Output.
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
4 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
0.3
+5.0
V
0.3
+5.0
V
VDDD
digital supply voltage
[1]
VDDA
analog supply voltage
[1]
VDD
supply voltage difference
between analog and digital supply voltage
150
+150
mV
VI
input voltage
digital inputs referenced to DGND
0.3
+5.5
V
pins REFIO, AVIRES, BVIRES referenced to
AGND
0.3
+5.5
V
pins IOUTAP, IOUTAN, IOUTBP and IOUTBN
referenced to AGND
0.3
VDDA + 0.3 V
VO
output voltage
Tstg
storage temperature
55
+150
C
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
-
125
C
[1]
All supplies are connected together.
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air
89.3
K/W
Rth(c-a)
thermal resistance from case to ambient
in free air
60.6
K/W
9. Characteristics
Table 5.
Characteristics
VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 C to +85 C; typical values
measured at Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDD
digital supply voltage
3.0
3.3
3.65
V
VDDA
analog supply voltage
3.0
3.3
3.65
V
IDDD
digital supply current
fs = 65 Msps, fo = 1 MHz,
VDD = 3.0 V to 3.6 V
-
6
7
mA
IDDA
analog supply current
fs = 65 Msps, fo = 1 MHz,
VDD = 3.0 V to 3.6 V
-
50
65
mA
Ptot
total power dissipation
fs = 65 Msps, fo = 1 MHz,
VDD = 3.0 V to 3.6 V
-
185
260
mW
Ppd
power dissipation in
power-down mode
-
16.5
-
mW
Digital inputs
VIL
LOW-level input voltage
DGND
-
0.9
V
VIH
HIGH-level input voltage
1.3
-
VDDD
V
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
5 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
Table 5.
Characteristics …continued
VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 C to +85 C; typical values
measured at Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIL
LOW-level input current
VIL = 0.9 V
-
5
-
A
IIH
HIGH-level input current
VIH = 1.3 V
-
5
-
A
Ci
input capacitance
-
5
-
pF
[1]
Analog outputs: pins IOUTAP, IOUTAN, IOUTBP and IOUTBN
IO(fs)
full-scale output current
differential outputs
2
-
20
mA
VO
output voltage
compliance range
1
-
+1.25
V
Ro
output resistance
[1]
-
150
-
k
output capacitance
[1]
-
3
-
pF
[1]
1.21
1.26
1.31
V
-
100
-
nA
1.0
-
1.26
V
-
1
-
M
-
-
125
Msps
2
-
-
ns
Co
Reference voltage input/output: pin REFIO
VO(ref)
reference output voltage
IO(ref)
reference output current
Vi
input voltage
Ri
input resistance
compliance range
Input timing; see Figure 18
fs
sampling frequency
tw(WRT)
WRT pulse width
pins WRTA, WRTB
tw(CLK)
CLK pulse width
pins CLKA, CLKB
2
-
-
ns
th(i)
input hold time
1
-
-
ns
tsu(i)
input set-up time
1.8
-
-
ns
Output timing: pins IOUTAP, IOUTAN, IOUTBP and IOUTBN
td
delay time
-
1
-
ns
tt
transition time
rising or falling transition
(10 % to 90 % or 90 % to 10 %)
[1]
-
0.6
-
ns
ts
settling time
1 LSB
[1]
-
16
-
ns
25 C
0.1
0.13
0.18
LSB
40 C to +85 C
0.08
-
0.18
LSB
40 C to +85 C
0.03
0.05
0.07
LSB
0.02
-
+0.02
%
with external reference
1.9
1.5
+2.5
%
with internal reference
2.9
2.1
+2.9
%
between DAC A and DAC B
0.5
0.5
+0.5
%
Static linearity
INL
DNL
integral non-linearity
differential non-linearity
Static accuracy (relative to full-scale) with GAINCTRL = 0
Eoffset
offset error
EG
gain error
G
gain mismatch
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
6 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
Table 5.
Characteristics …continued
VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 C to +85 C; typical values
measured at Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
80
-
dBc
Dynamic performance
SFDR
spurious free dynamic range
B = Nyquist
fs = 52 Msps; fo = 1 MHz
0 dBFS
6 dBFS
-
78
-
dBc
12 dBFS
-
72
-
dBc
-
78
-
dBc
fo = 10.4 MHz
-
77
-
dBc
fo = 15.7 MHz
-
70
-
dBc
fs = 52 Msps; 0 dBFS
fo = 5.24 MHz
fs = 78 Msps; 0 dBFS
fs = 100 Msps; 0 dBFS
fo = 5.04 MHz
-
76
-
dBc
fo = 20.2 MHz
60
68
-
dBc
-
67
-
dBc
fs = 52 Msps; fo = 1 MHz;
2 MHz span
-
87
-
dBc
fs = 52 Msps; fo = 5.24 MHz;
10 MHz span
-
85
-
dBc
fs = 78 Msps; fo = 5.26 MHz;
10 MHz span
-
88
-
dBc
fs = 125 Msps; fo = 5.04 MHz;
10 MHz span
78
88
-
dBc
fs = 52 Msps; fo = 1 MHz
-
77
-
dBc
fs = 78 Msps; fo = 5.26 MHz
-
75
-
dBc
fs = 100 Msps; fo = 5.04 MHz
-
73
-
dBc
fs = 125 Msps; fo = 20.1 MHz
-
63
59
dBc
fs = 65 Msps;
2 MHz < fo < 2.99 MHz; 8 tones at
110 kHz spacing at 0 dB full-scale
-
80
-
dBc
fs = 125 Msps; 0 dBFS
fo = 20.1 MHz
Within a Window
THD
total harmonic distortion
MTPR
multitone power ratio
NSD
noise spectral density
fs = 100 Msps; fo = 5.04 MHz
-
148.5
-
dBm/Hz
cs
channel separation
fs = 78 Msps; fo = 10.4 MHz
-
88.0
-
dBc
fs = 125 Msps; fo = 20.1 MHz
-
83.5
-
dBc
[1]
Guaranteed by design.
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
7 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aai996
80
SFDR
(dBc)
(1)
76
(2)
72
(3)
68
(4)
64
−60
−20
0
20
60
100
T (°C)
(1) fo = 5 MHz.
(2) fo = 10 MHz.
(3) fo = 15 MHz.
(4) fo = 20 MHz.
Fig 3.
SFDR as a function of the ambient temperature at 125 Msps
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
8 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aai984
0
α
(dBm)
−20
−40
−60
−80
−100
0
10
20
30
f (MHz)
fs = 52 Msps; fc = 5.24 MHz; = 0 dBFS
001aai986
0
α
(dBm)
−20
−40
−60
−80
−100
0
10
20
30
40
50
f (MHz)
fs = 100 Msps; fc = 20 MHz; = 0 dBFS
Fig 4.
1-tone SFDR
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
9 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aai988
0
α
(dBm)
−20
−40
−60
−80
−100
0
10
20
30
40
f (MHz)
fs = 78 Msps; fc = 9.44 MHz, fc = 10.44 MHz; = 0 dBFS
Fig 5.
2-tone SFDR
001aai989
0
α
(dBm)
−20
−40
−60
−80
−100
0
10
20
30
f (MHz)
fs = 52 Msps; fc = 6.25 MHz, fc = 6.75 MHz; fc = 7.25 MHz, fc = 7.75 MHz; = 0 dBFS
Fig 6.
4-tone SFDR
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
10 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aai990
0
α
(dBm)
−20
−40
−60
−80
−100
0
10
20
30
40
f (MHz)
fs = 78 Msps; from fc = 9.5 MHz, 110 kHz spacing; = 0 dBFS
Fig 7.
8-tone SFDR
001aaj000
0.2
INL
(dB)
0.1
0
−0.1
−0.2
0
192
384
576
768
960
1152
input code
Fig 8.
INL as a function of the input code
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
11 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aai999
0.06
DNL
(dB)
0.04
0.02
0
−0.02
0
192
384
576
768
960
1152
input code
Fig 9.
DNL as a function of the input code
001aaj046
80
SFDR
(dBc)
76
72
(1)
68
(2)
(3)
64
0
5
10
15
20
fo (MHz)
(1) fo = 0 dBFS.
(2) fo = 6 dBFS.
(3) fo = 12 dBFS.
Fig 10. SFDR full-scale at 78 Msps as a function of the output frequency
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
12 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aaj047
85
SFDR
(dBc)
80
75
70
(1)
65
(2)
(3)
60
0
5
10
15
20
25
fo (MHz)
(1) fo = 0 dBFS.
(2) fo = 6 dBFS.
(3) fo = 12 dBFS.
Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency
001aai938
16
(1)
IDDD
(mA)
(2)
12
(3)
(4)
8
4
0
0
0.1
0.2
0.3
0.4
0.5
fo/fs
(1) fs = 125 Msps.
(2) fs = 100 Msps.
(3) fs = 78 Msps.
(4) fs = 52 Msps.
Fig 12. Digital supply current as a function of fo/fs
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
13 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
001aaj032
60
IDDA
(mA)
40
20
0
0
5
10
15
20
lO (mA)
Fig 13. Analog supply current as a function of the output current
10. Application information
10.1 General description
The DAC1001D125 is a dual 10-bit DAC operating up to 125 Msps. Each DAC consists of
a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 3-bit binary
weighted sub-DAC.
Two modes are available for the digital input depending on the status of the pin MODE. In
Dual-port mode, each DAC uses its own data input line at the same frequency as the
update rate. In Interleaved mode, both DACs use the same data input line at twice the
update rate.
Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary
current outputs. This provides a full-scale output current (IO(fs)), up to 20 mA. A single
common or two independent full-scale current controls can be selected for both channels
using pin GAINCTRL. An internal reference is available for the reference current, which is
externally adjustable using pin REFIO.
The DAC1001D125 operates at 3.3 V and has separate digital and analog power
supplies. Pin PWD is used to power-down the device. The digital input is 1.8 V compliant,
3.3 V compliant and 5 V tolerant.
10.2 Input data
The DAC1001D125 input follows a straight binary coding where DA9 and DB9 are the
Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB).
The setting applied to pin MODE defines whether the DAC1001D125 operates in
Dual-port mode or in Interleaved mode (see Table 6).
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
14 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
Table 6.
Mode selection
Mode Function
DA9 to DA0
DB9 to DB0
Pin 17
Pin 18 Pin 19
Pin 20
0
Interleaved mode
active
off
IQWRT
IQCLK IQRESET
IQSEL
1
Dual-port mode
active
active
WRTA
CLKA
WRTB
CLKB
10.2.1 Dual-port mode
The data and clock circuit for Dual-port mode operation is shown in Figure 14.
DA9 to DA0
10
INPUT A 10
LATCH
DAC A
LATCH
10
INPUT B 10
LATCH
DAC B
LATCH
WRTA
CLKA
CLKB
WRTB
DB9 to DB0
001aai949
Fig 14. Dual-port mode operation
Each DAC has its own independent data and clock inputs. The data enters the input latch
on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The
output is updated on the rising edge of the CLKA/CLKB signal.
DA9 to DA0/
DB9 to DB0
N
N+1
N+2
N+3
WRTA/
WRTB
CLKA/
CLKB
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
N−2
N−1
N
N+1
N+2
001aaj064
Fig 15. Dual-port mode timing
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
15 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
10.2.2 Interleaved mode
The data and clock circuit for Interleaved mode operation is illustrated in Figure 16.
DA9 to DA0
10
INPUT A 10
LATCH
DAC A
LATCH
10
INPUT B 10
LATCH
DAC B
LATCH
IQWRT
IQSEL
IQCLK
IQRESET
÷2
001aai952
Fig 16. Interleaved mode
In Interleaved mode, both DACs use the same data and clock inputs at twice the update
rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A
or latch B, depending on the value of IQSEL. The IQSEL transition must occur when
IQWRT and IQCLK are LOW.
The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is
updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17.
DA9 to DA0/
DB9 to DB0
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
IQSEL
IQWRT
IQCLK
IQRESET
N
IOUTAP, IOUTAN
IOUTBP, IOUTBN
N+4
XX
N+2
N+1
XX
N+3
N+5
001aaj065
Fig 17. Interleaved mode timing
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
16 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
10.3 Timing
The DAC1001D125 can operate at an update rate of 125 Msps, which generates an input
data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The timing of
the DAC1001D125 is shown in Figure 18.
tsu(i)
th(i)
DA9 to DA0/
DB9 to DB0
WRTA/
WRTB
tw(WRT)
td(clk)
CLKA/
CLKB
td
tw(CLK)
90 %
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
10 %
tt
ts
001aaj066
Fig 18. Timing of the DAC1001D125
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
• A configuration resulting in the same timing for the signals WRTA/WRTB and
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them
together.
• The rising edge of the CLKA/CLKB signal can also be placed in a range from half a
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns
after the rising edge of the WRTA/WRTB signal.
A typical set-up time of 0 ns and a hold time of 0.6 ns enable the DAC1001D125 to be
easily integrated into any application.
10.4 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
(1)
I O fs = I IOUTP + I IOUTN
The output current depends on the digital input data:
DATA
I IOUTP = I O fs ----------------
1024
1023 – DATA
I IOUTN = I O fs --------------------------------------
1024
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
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DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
Table 7 shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 7.
DAC transfer function
Data
DA9/DB9 to DA0/DB0
IOUTAP/IOUTBP
IOUTAN/IOUTBN
0
...
00 0000 0000
0 mA
20 mA
...
...
...
8192
10 0000 0000
10 mA
10 mA
...
...
...
...
16383
11 1111 1111
20 mA
0 mA
10.5 Full-scale current adjustment
The DAC1001D125 integrates one 1.25 V reference and two current sources to adjust the
full-scale current in both DACs.
The internal reference configuration is shown in Figure 19.
CURRENT
SOURCE
AVIRES
RA
AGND
1.25 V REFERENCE
REFIO
100 nF
AGND
CURRENT
SOURCE
BVIRES
RB
AGND
001aai822
Fig 19. Internal reference configuration
The bias current is generated by the output of the internal regulator connected to the
inverting input of the internal operational amplifiers. The external resistors RA and RB are
connected to pins AVIRES and BVIRES, respectively. This configuration is optimal for
temperature drift compensation because the band gap can be matched with the voltage
on the feedback resistors.
The relationship between full-scale output current (IO(fs)) at the output of channel A or
channel B and the resistor is:
24V REFIO
I O fs = -----------------------RA
(2)
The output current of the two DACs is typically fixed to 20 mA when both resistors RA and
RB are set to 1.5 k. The operational range of DAC1001D125 is from 2 mA to 20 mA.
It is recommended to decouple pin REFIO with a 100 nF capacitor.
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
18 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
An external reference can also be used for applications requiring higher accuracy or
precise current adjustment. Due to the high input impedance of pin REFIO, applying an
external source disables the band gap.
10.6 Gain control
Table 8 shows how to select the different gain control modes.
Table 8.
Gain control
GAINCTRL
Mode
DAC A
full-scale control
DAC B
full-scale control
0
independent gain control
AVIRES
BVIRES
1
common gain control
AVIRES
AVIRES
In independent gain mode, both full-scale currents can be adjusted independently using
resistors RA on pin AVIRES and RB on pin BVIRES.
In Common gain mode, the full-scale current is adjusted with resistor RA on pin AVIRES
and divided by two in both DACs.
10.7 Analog outputs
See Figure 20 for the analog output circuit of one DAC. This circuit consists of a parallel
combination of PMOS current sources and associated switches for each segment.
IOUTAP/IOUTBP
IOUTAN/IOUTBN
RL
AGND
RL
AGND
001aai821
Fig 20. Equivalent analog output circuit
Cascode source configuration enables the output impedance of the source to be
increased, thus improving the dynamic performance by reducing distortion.
The DAC1001D125 can be used either with:
• a differential output, coupled to a transformer (or operational amplifier) to reduce
even-order harmonics and noise
• or a single-ended output for applications requiring unipolar voltage.
The typical configuration is to use 1 V p-p level on each output IOUTAP/IOUTBP and
IOUTAN/IOUTBN but several combinations can be used as far as they respect the voltage
compliance range.
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
19 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
10.7.1 Differential output using transformer
The use of a differentially coupled transformer output (see Figure 21) provides optimum
distortion performance. In addition, it helps to match the impedance and provides
electrical isolation.
T1-1T
IOUTAP/
IOUTBP
Rdiff
IOUTAN/
IOUTBN
Rload
1:1
001aai935
Fig 21. Differential output with transformer
The center tap is grounded to allow the DC current flow to/from both outputs. If the center
tap is open, the differential resistor must be replaced by two resistors connected to
ground.
10.7.2 Single-ended output
Using a single load resistor on one current output will provide an unipolar output range,
typically from 0 V to 0.5 V with a 20 mA full-scale current at a 50 load.
20 mA
Z = 50 Ω
IOUTAP/
IOUTBP
50 Ω
50 Ω
0 V to 0.5 V
IOUTAN/
IOUTBN
25 Ω
001aai936
Fig 22. Single-ended output
The resistor on the other current output is 25 .
10.8 Power-down function
The DAC1001D125 has a power-down function to reduce the power consumption when it
is not active.
Table 9.
Power-down
PWD
Device function
Power dissipation (typ)
0
active
185 mW
1
not active
16.5 mW
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
20 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
10.9 Alternative parts
The following alternative parts are also available.
Table 10. Alternative parts
Pin compatible
Type number
Description
Sampling frequency
DAC1401D125
dual 14-bit DAC
up to 125 Msps
DAC1201D125
dual 12-bit DAC
up to 125 Msps
10.10 Application diagram
RL
AGND
RL
AGND
AGND
AGND
AGND
1.5
kΩ
100 Ω
1.5
kΩ
100
nF
100 Ω
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
n.c.
n.c.
PWD
AGND
IOUTBP
IOUTBN
AGND
BVIRES
GAINCTRL
REFIO
AVIRES
IOUTAN
MODE
VDDA
IOUTAP
3.3 V
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
DAC1001D125
7
30
8
29
9
28
10
27
11
26
12
25
n.c.
n.c.
n.c.
n.c.
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
100 nF
DGND
3.3 V
DB8
DB9
VDDD
DGND
IQSEL
IQRESET
IQCLK
IQWRT
VDDD
DGND
n.c.
n.c.
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
DGND
3.3 V
001aaj102
Dual-port mode (MODE = 1)
DAC active (PWD = 0)
Independent channel gain (GAINCTRL = 0)
Fig 23. Application diagram
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
21 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
11. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
o
0
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 24. Package outline SOT313-2 (LQFP48)
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
22 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
12. Abbreviations
Table 11.
Abbreviations
Acronym
Description
BW
BandWidth
dBFS
deciBel Full Scale
DDS
Direct Digital frequency Synthesis
IF
Intermediate Frequency
LSB
Least Significant Bit
MSB
Most Significant Bit
SFDR
Spurious-Free Dynamic Range
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
23 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
13. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
DAC1001D125 v.3
20120702
Product data sheet
-
DAC1001D125 v.2
DAC1001D125 v.2
20120127
Product data sheet
-
DAC1001D125 v.1
Modifications:
DAC1001D125 v.1
•
•
Table 4 “Thermal characteristics” has been updated.
Section 10.6 “Gain control” has been updated.
20081124
Product data sheet
-
-
14. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
DAC1001D125 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
24 of 25
DAC1001D125
Integrated Device Technology
Dual 10-bit DAC, up to 125 Msps
15. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.2.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application information. . . . . . . . . . . . . . . . . . 14
General description . . . . . . . . . . . . . . . . . . . . 14
Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 15
10.2.2
10.3
10.4
10.5
10.6
10.7
10.7.1
10.7.2
10.8
10.9
10.10
11
12
13
14
15
DAC1001D125 3
Product data sheet
Interleaved mode . . . . . . . . . . . . . . . . . . . . . .
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC transfer function. . . . . . . . . . . . . . . . . . .
Full-scale current adjustment. . . . . . . . . . . . .
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog outputs . . . . . . . . . . . . . . . . . . . . . . . .
Differential output using transformer . . . . . . .
Single-ended output. . . . . . . . . . . . . . . . . . . .
Power-down function . . . . . . . . . . . . . . . . . . .
Alternative parts . . . . . . . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
17
18
19
19
20
20
20
21
21
22
23
24
24
25
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
25 of 25
