IDTDAC1205D650HW-C1

DAC1205D650 Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Rev. 04 — 2 July 2012 Product data sheet 1. General description The DAC1205D650 is a high-speed 12-bit dual-channel Digital-to-Analog Converter (DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1205D650 allows the complex I and Q inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO). The phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1205D650 also includes a 2, 4 and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. 2. Features and benefits  Dual 12-bit resolution  650 Msps maximum update rate           IMD3: 79 dBc; fs = 640 Msps; fo = 96 MHz  ACPR: 68 dB; 2 carriers WCDMA; fs = 614.4 Msps; fo = 115.2 MHz; PLL on Selectable 2, 4 or 8 interpolation  Typical 0.95 W power dissipation at 4 filters interpolation Input data rate up to 160 Msps  Power-down and Sleep modes Very low noise cap-free integrated PLL  Differential scalable output current from 1.6 mA to 22 mA 32-bit programmable NCO frequency  On-chip 1.29 V reference Dual-port or Interleaved data modes  External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies  Internal digital offset control LVDS compatible clock  Inverse (sin x) / x function  Fully compatible SPI port Two’s complement or binary offset data format 3.3 V CMOS input buffers  Industrial temperature range from 40 C to +85 C ® DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 3. Applications        Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number DAC1205D650HW-C1 Package Name Description Version HTQFP100 plastic thermal enhanced thin quad flat package; 100 leads; body 14  14  1 mm; exposed die pad SOT638-1 DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 2 of 41 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SDO Integrated Device Technology DAC1205D650 4 Product data sheet 5. Block diagram SCS_N SDIO 62 63 SCLK 65 64 10-BIT OFFSET CONTROL NCO SPI cos sin AUXILIARY DAC 2 3 AUXAP AUXAN mixer 10-BIT GAIN CONTROL DAC1205D650 + 18 to 25, 28 to 31 I0 to I11 12 LATCH I FIR1 FIR2 FIR3 2× 2× 2× 90 A x sin x − DAC 91 IOUTAP IOUTAN + 68 OFFSET CONTROL dual port/ interleaved data modes 41, 42, 45 to 48, 51 to 56 Q0 to Q11 LATCH Q FIR1 FIR2 FIR3 2× 2× 2× REFERENCE BANDGAP 69 CLKN + + B 12 8 9 GAPOUT mixer x sin x 86 DAC 85 + CLKP VIRES IOUTBP IOUTBN 10-BIT GAIN CONTROL CLOCK GENERATOR/PLL mixer COMPLEX MODULATOR RESET_N Fig 1. Block diagram 74 AUXILIARY DAC 73 AUXBP AUXBN 001aak157 3 of 41 © IDT 2012. All rights reserved. DAC1205D650 66 10-BIT OFFSET CONTROL Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Rev. 04 — 2 July 2012 mixer DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 6. Pinning information 77 VDDA(1V8) 76 AGND 78 AGND 79 VDDA(1V8) 80 AGND 81 VDDA(1V8) 82 AGND 83 VDDA(1V8) 84 AGND 85 IOUTBN 86 IOUTBP 87 AGND 88 n.c. 89 AGND 90 IOUTAP 91 IOUTAN 92 AGND 93 VDDA(1V8) 94 AGND 95 VDDA(1V8) 96 AGND 97 VDDA(1V8) 98 AGND 99 VDDA(1V8) 100 AGND 6.1 Pinning VDDA(3V3) 1 75 VDDA(3V3) AUXAP 2 74 AUXBP AUXAN 3 73 AUXBN AGND 4 72 AGND VDDA(1V8) 5 71 VDDA(1V8) VDDA(1V8) 6 70 VDDA(1V8) AGND 7 69 GAPOUT CLKP 8 68 VIRES CLKN 9 67 d.n.c. AGND 10 66 RESET_N VDDA(1V8) 11 65 SCS_N d.n.c. 12 64 SCLK DAC1205D650HW d.n.c. 13 63 SDIO TM1 14 62 SDO TM0 15 61 TM3 VDD(IO)(3V3) 16 60 VDD(IO)(3V3) GNDIO 17 59 GNDIO I11 18 58 n.c. AGND I10 19 56 Q0 I8 21 55 Q1 I7 22 54 Q2 VDDD(1V8) 50 DGND 49 Q6 48 Q7 47 Q8 46 Q9 45 VDDD(1V8) 44 DGND 43 Q10 42 Q11/SELIQ 41 VDDD(1V8) 40 DGND 39 TM2 38 DGND 37 VDDD(1V8) 36 n.c. 35 n.c. 34 DGND 33 VDDD(1V8) 32 I0 31 51 Q5 I1 30 I4 25 I2 29 52 Q4 I3 28 53 Q3 I5 24 DGND 27 I6 23 VDDD(1V8) 26 Fig 2. 57 n.c. I9 20 001aak156 Pin configuration DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 4 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 6.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description VDDA(3V3) 1 P analog supply voltage 3.3 V AUXAP 2 O auxiliary DAC B output current AUXAN 3 O complementary auxiliary DAC B output current AGND 4 G analog ground VDDA(1V8) 5 P analog supply voltage 1.8 V VDDA(1V8) 6 P analog supply voltage 1.8 V AGND 7 G analog ground CLKP 8 I clock input CLKN 9 I complementary clock input AGND 10 G analog ground VDDA(1V8) 11 P analog supply voltage 1.8 V d.n.c. 12 - do not connect d.n.c. 13 - do not connect TM1 14 I/O test mode 1 (to connect to DGND) TM0 15 I/O test mode 0 (to connect to DGND) VDD(IO)(3V3) 16 P input/output buffers supply voltage 3.3 V GNDIO 17 G input/output buffers ground I11 18 I I data input bit 11 (MSB) I10 19 I I data input bit 10 I9 20 I I data input bit 9 I8 21 I I data input bit 8 I7 22 I I data input bit 7 I6 23 I I data input bit 6 I5 24 I I data input bit 5 I4 25 I I data input bit 4 VDDD(1V8) 26 P digital supply voltage 1.8 V DGND 27 G digital ground I3 28 I I data input bit 3 I2 29 I I data input bit 2 I1 30 I I data input bit 1 I0 31 I I data input bit 0 (LSB) VDDD(1V8) 32 P digital supply voltage 1.8 V DGND 33 G digital ground n.c. 34 I not connected n.c. 35 I not connected VDDD(1V8) 36 P digital supply voltage 1.8 V DGND 37 G digital ground TM2 38 - test mode 2 (to connect to DGND) DGND 39 G digital ground DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 5 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 2. Pin description …continued Symbol Pin Type[1] Description VDDD(1V8) 40 P digital supply voltage 1.8 V Q11/SELIQ 41 I Q data input bit 11 (MSB) select IQ in Interleaved mode Q10 42 I Q data input bit 10 DGND 43 G digital ground VDDD(1V8) 44 P digital supply voltage 1.8 V Q9 45 I Q data input bit 9 Q8 46 I Q data input bit 8 Q7 47 I Q data input bit 7 Q6 48 I Q data input bit 6 DGND 49 G digital ground VDDD(1V8) 50 P digital supply voltage 1.8 V Q5 51 I Q data input bit 5 Q4 52 I Q data input bit 4 Q3 53 I Q data input bit 3 Q2 54 I Q data input bit 2 Q1 55 I Q data input bit 1 Q0 56 I Q data input bit 0 (LSB) n.c. 57 I not connected n.c. 58 I not connected GNDIO 59 G input/output buffers ground VDD(IO)(3V3) 60 P input/output buffers supply voltage 3.3 V TM3 61 I/O test mode 3 (to connect to DGND) SDO 62 O SPI data output SDIO 63 I/O SPI data input/output SCLK 64 I SPI clock SCS_N 65 I SPI chip select (active LOW) RESET_N 66 I general reset (active LOW) d.n.c. 67 - do not connect VIRES 68 I/O DAC biasing resistor GAPOUT 69 I/O bandgap input/output voltage VDDA(1V8) 70 P analog supply voltage 1.8 V VDDA(1V8) 71 P analog supply voltage 1.8 V AGND 72 G analog ground AUXBN 73 O complementary auxiliary DAC B output current AUXBP 74 O auxiliary DAC B output current VDDA(3V3) 75 P analog supply voltage 3.3 V AGND 76 G analog ground VDDA(1V8) 77 P analog supply voltage 1.8 V AGND 78 G analog ground VDDA(1V8) 79 P analog supply voltage 1.8 V DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 6 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 2. Pin description …continued Symbol Pin Type[1] Description AGND 80 G analog ground VDDA(1V8) 81 P analog supply voltage 1.8 V AGND 82 G analog ground VDDA(1V8) 83 P analog supply voltage 1.8 V AGND 84 G analog ground IOUTBN 85 O complementary DAC B output current IOUTBP 86 O DAC B output current AGND 87 G analog ground n.c. 88 - not connected AGND 89 G analog ground IOUTAP 90 O DAC A output current IOUTAN 91 O complementary DAC A output current AGND 92 G analog ground VDDA(1V8) 93 P analog supply voltage 1.8 V AGND 94 G analog ground VDDA(1V8) 95 P analog supply voltage 1.8 V AGND 96 G analog ground VDDA(1V8) 97 P analog supply voltage 1.8 V AGND 98 G analog ground VDDA(1V8) 99 P analog supply voltage 1.8 V AGND 100 G analog ground AGND H[2] G analog ground [1] P = power supply G = ground I = input O = output. [2] H = heatsink (exposed die pad to be soldered). DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 7 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit 0.5 +4.6 V VDDA(3V3) analog supply voltage (3.3 V) 0.5 +4.6 V VDDA(1V8) analog supply voltage (1.8 V) 0.5 +3.0 V VDDD(1V8) digital supply voltage (1.8 V) 0.5 +3.0 V VI input voltage pins CLKP, CLKN, VIRES and GAPOUT referenced to AGND 0.5 +3.0 V pins I11 to I0, Q11 to Q0, SDO, SDIO, SCLK, SCS_N and RESET_N referenced to GNDIO 0.5 +4.6 V pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to AGND 0.5 +4.6 V 55 +150 C VDD(IO)(3V3) input/output supply voltage (3.3 V) VO output voltage Tstg storage temperature Tamb ambient temperature 45 +85 C Tj junction temperature - 125 C 8. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Rth(j-a) thermal resistance from junction to ambient thermal resistance from junction to case Rth(j-c) [1] Conditions Typ Unit [1] 19.8 K/W [1] 7.7 K/W In compliance with JEDEC test board, in free air. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 8 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 9. Characteristics Table 5. Characteristics VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] VDD(IO)(3V3) input/output supply voltage (3.3 V) I 3.0 3.3 3.6 V VDDA(3V3) analog supply voltage (3.3 V) I 3.0 3.3 3.6 V VDDA(1V8) analog supply voltage (1.8 V) I 1.7 1.8 1.9 V VDDD(1V8) digital supply voltage (1.8 V) I 1.7 1.8 1.9 V IDD(IO)(3V3) input/output supply current (3.3 V) fo = 19 MHz; fs = 640 Msps; 8 interpolation; NCO on I - 5 13 mA IDDA(3V3) analog supply current fo = 19 MHz; fs = 640 Msps; (3.3 V) 8 interpolation; NCO on I - 48 26 mA IDDD(1V8) digital supply current (1.8 V) fo = 19 MHz; fs = 640 Msps; 8 interpolation; NCO on I - 270 309 mA IDDA(1V8) analog supply current fo = 19 MHz; fs = 640 Msps; (1.8 V) 8 interpolation; NCO on I - 330 358 mA IDDD digital supply current for x / (sin x) function only I - 67 - mA Ptot total power dissipation fo = 19 MHz; fs = 320 Msps; 4 interpolation; NCO off; DAC B off C - 0.53 - W fo = 19 MHz; fs = 320 Msps; 4 interpolation; NCO off C - 0.82 - W fo = 19 MHz; fs = 320 Msps; 4 interpolation; NCO on C - 0.94 - W fo = 19 MHz; fs = 640 Msps; 8 interpolation; NCO off C - 0.95 - W fo = 19 MHz; fs = 640 Msps; 8 interpolation; NCO on; All VDD I - 1.18 1.4 W fo = 19 MHz; fs = 640 Msps; 8 interpolation; NCO low-power on C - 1.07 - W full power-down; all VDD I - 0.08 0.13 W DAC A and DAC B Sleep mode; 8 interpolation; NCO on I - 0.88 - W Power-down mode DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 9 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Clock inputs (CLKP and CLKN)[2] input voltage CLKP; or CLKN Vgpd < 50 mV Vidth input differential threshold voltage Vgpd < 50 mV Ri input resistance Ci input capacitance Vi C [3] 825 - 1575 mV C [3] 100 - +100 mV D - 10 - M D - 0.5 - pF V Digital inputs (I0 to I11, Q0 to Q11) VIL LOW-level input voltage C GNDIO - 1.0 VIH HIGH-level input voltage C 2.3 - VDD(IO)(3V3) V IIL LOW-level input current VIL = 1.0 V I - 40 - A IIH HIGH-level input current VIH = 2.3 V I - 80 - A V Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N) VIL LOW-level input voltage C GNDIO - 1.0 VIH HIGH-level input voltage C 2.3 - VDD(IO)(3V3) V IIL LOW-level input current VIL = 1.0 V I - 20 - nA IIH HIGH-level input current VIH = 2.3 V I - 20 - nA C - 1.6 - mA Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN) IO(fs) full-scale output current register value = 00h default register C - 20 - mA VO output voltage compliance range C 1.8 - VDDA(3V3) V Ro output resistance D - 250 - k Co output capacitance D - 3 - pF NDAC(mono) DAC monotonicity D - 8 - bit EO offset error variation C - 6 - ppm/C EG gain error variation C - 18 - ppm/C I 1.24 1.29 1.34 V C - 117 - ppm/C D - 40 - A guaranteed Reference voltage output (GAPOUT) VO(ref) reference output voltage VO(ref) reference output voltage variation IO(ref) reference output current Tamb = 25 C external voltage 1.25 V DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 10 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) IO(aux) auxiliary output current differential outputs I - 2.2 - mA VO(aux) auxiliary output voltage compliance range C 0 - 2 V guaranteed D - 10 - bit Dual-port mode input C - - 160 MHz C 1.5 - Tdata  1.5 ns NDAC(aux)mono auxiliary DAC monotonicity Input timing (see Figure 10) fdata data rate tw(CLK) CLK pulse width th(i) input hold time C 1.1 - - ns tsu(i) input set-up time C 1.1 - - ns fs sampling frequency C - - 650 Msps ts settling time D - 20 - ns register value = 00000000h D - 0 - MHz register value = FFFFFFFFh D - 640 - MHz D - 0.149 - Hz register value = 00000000h D - 0 - MHz register value = F8000000h D - 620 - MHz D - 20 - MHz C fdata = 80 MHz; fs = 320 Msps; B = fdata / 2; fo = 35 MHz at 0 dBFS - 84 - dBc Output timing to 0.5 LSB NCO frequency range; fs = 640 Msps fNCO fstep NCO frequency step frequency Low-power NCO frequency range; fDAC = 640 MHz fNCO fstep NCO frequency step frequency Dynamic performance; PLL on SFDR spurious-free dynamic range fdata = 80 MHz; fs = 640 Msps; B = fdata / 2 fo = 4 MHz at 0 dBFS I - 76 - dBc fo = 19 MHz at 0 dBFS I - 76 - dBc - 83 - dBc C fdata = 160 MHz; fs = 640 Msps; B = fdata / 2; fo = 70 MHz at 0 dBFS SFDRRBW restricted bandwidth spurious-free dynamic range fs = 640 Msps; fo = 96 MHz at 0 dBFS; B = 30 kHz 2.51 MHz  foffset  2.71 MHz I - 91 84 dBc 2.71 MHz  foffset  3.51 MHz I - 92 - dBc 3.51 MHz  foffset  4 MHz I - 93 85 dBc I - 84 65 dBc fs = 640 Msps; fo = 96 MHz at 0 dBFS; B = 1 MHz 4 MHz  foffset  40 MHz DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 11 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] IMD3 ACPR third-order intermodulation distortion adjacent channel power ratio fo1 = 49 MHz; fo2 = 51 MHz; fs = 320 Msps; 4 interpolation C [4] - 82 - dBc fo1 = 95 MHz; fo2 = 97 MHz; fs = 320 Msps; 4 interpolation C [4] - 80 - dBc fo1 = 95 MHz; fo2 = 97 MHz; fs = 640 Msps; 8 interpolation I [4] 66 79 - dBc fo1 = 152 MHz; fo2 = 154 MHz; fs = 640 Msps; 8 interpolation C [4] - 77 - dBc fdata = 76.8 MHz; fs = 614.4 Msps; fo = 96 MHz 1 carrier; B = 5 MHz I - 70 - dB 2 carriers; B = 10 MHz C - 68 - dB 4 carriers; B = 20 MHz C - 67 - dB 1 carrier; B = 5 MHz C - 70 - dB 2 carriers; B = 10 MHz C - 68 - dB 4 carriers; B = 20 MHz C - 66 - dB 1 carrier; B = 5 MHz C - 68 - dB 2 carriers; B = 10 MHz C - 66 - dB 4 carriers; B = 20 MHz C - 65 - dB noise shaper disabled C - 149 - dBm/Hz noise shaper enabled C - 150 - dBm/Hz fdata = 153.6 MHz; fs = 614.4 Msps; fo = 115.2 MHz fdata = 153.6 MHz; fs = 614.4 Msps; fo = 153.6 MHz NSD noise spectral density fs = 640 Msps; 8 interpolation; fo = 19 MHz at 0 dBFS [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80  and 120  should be connected across the pins (see Figure 8). [3] Vgpd represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground. [4] IMD3 rejection with 6 dBFS/tone. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 12 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10. Application information 10.1 General description The DAC1205D650 is a dual 12-bit DAC operating at up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 6-bit binary weighted sub-DAC. With an input data rate of up to 160 MHz, and a maximum output sampling rate of 650 Msps, the DAC1205D650 allows more flexibility for wide bandwidth and multi-carrier systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1205D650 simplifies the frequency selection of the system. This is also possible because of the 2, 4 and 8 interpolation filters that remove undesired images. Two modes are available for the digital input. In the Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 20 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are embedded features which provide analog offset correction (internal auxiliary DACs), digital offset control and gain adjustment. All the functions can be set using a SPI. The DAC1205D650 operates at both 3.3 V and 1.8 V using separate digital and analog power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant. 10.2 Serial interface (SPI) 10.2.1 Protocol description The DAC1205D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select bar. If several DAC1205D650 devices are connected to an application on the same SPI-bus, only a 3-wire type can be used. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with between 2 to 5 bytes, depending on the content of the instruction byte (see Table 7). DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 13 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating RESET_N SCS_N SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO (optional) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 001aaj812 R/W indicates the mode access (see Table 6). Fig 3. SPI protocol Table 6. Read or Write mode access description R/W Description 0 Write mode operation 1 Read mode operation In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte. Table 7. Number of bytes to be transferred N1 N0 Number of bytes 0 0 1 byte transferred 0 1 2 bytes transferred 1 0 3 bytes transferred 1 1 4 bytes transferred A0 to A4: indicates which register is being addressed. In the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in decreasing order according to Table 9 “Register allocation map”. 10.2.2 SPI timing description The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4. tw(RESET_N) RESET_N 50 % th(SCS_N) tsu(SCS_N) SCS_N 50 % tw(SCLK) SCLK SDIO 50 % 50 % th(SDIO) tsu(SDIO) Fig 4. SPI timing diagram DAC1205D650 4 Product data sheet 001aaj813 © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 14 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating The SPI timing characteristics are given in Table 8. Table 8. SPI timing characteristics Symbol Parameter Min Typ Max Unit fSCLK SCLK frequency - - 15 MHz tw(SCLK) SCLK pulse width 30 - - ns tsu(SCS_N) SCS_N set-up time 20 - - ns th(SCS_N) SCS_N hold time 20 - - ns tsu(SDIO) SDIO set-up time 10 - - ns th(SDIO) SDIO hold time 5 - - ns tw(RESET_N) RESET_N pulse width 30 - - ns 10.2.3 Detailed descriptions of registers An overview of the details for all registers is provided in Table 9. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 15 of 41 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register allocation map R/W Bit definition Default b7 b6 b5 b4 b3 b2 b1 b0 0 00h COMMon R/W 3W_SPI SPI_RST CLK_SEL - MODE_ SEL CODING IC_PD GAP_PD 10000000 80 128 1 01h TXCFG R/W NCO_ON NCO_LP_ SEL INV_SIN_ SEL INTERPOLATION[1:0] 10000111 87 135 2 02h PLLCFG R/W PLL_PD - PLL_DIV_ PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W FREQ_NCO[15:8] 01100110 66 102 5 05h FREQNCO_UISB R/W FREQ_NCO[23:16] 01100110 66 102 6 06h FREQNCO_MSB R/W FREQ_NCO[31:24] 00100110 26 38 7 07h PHINCO_LSB R/W PH_NCO[7:0] 00000000 00 0 8 08h PHINCO_MSB R/W 00000000 00 0 9 09h DAC_A_Cfg_1 R/W DAC_A_PD 00000000 00 0 MODULATION[2:0] PLL_DIV[1:0] PLL_PHASE[1:0] Hex Dec PLL_POL 00010000 10 FREQ_NCO[7:0] 01100110 66 PH_NCO[15:8] DAC_A_ SLEEP Bin DAC_A_OFFSET[4:0] - 16 102 R/W DAC_A_GAIN_ COARSE[1:0] DAC_A_GAIN_FINE[5:0] 01000000 40 64 11 0Bh DAC_A_Cfg_3 R/W DAC_A_GAIN_ COARSE[3:2] DAC_A_OFFSET[10:5] 11000000 C0 192 12 0Ch DAC_B_Cfg_1 R/W DAC_B_PD 00000000 00 0 13 0Dh DAC_B_Cfg_2 R/W DAC_B_GAIN_ COARSE[1:0] DAC_B_GAIN_FINE[5:0] 01000000 40 64 14 0Eh DAC_B_Cfg_3 R/W DAC_B_GAIN_ COARSE[3:2] DAC_B_OFFSET[10:5] 11000000 C0 192 15 0Fh DAC_Cfg R/W 11000000 C0 0 ... ... ... ... DAC_B_ SLEEP DAC_B_OFFSET[4:0] ... ... ... ... ... 16 of 41 © IDT 2012. All rights reserved. 26 1Ah DAC_A_Aux_MSB R/W AUX_A[9:2] 27 1Bh DAC_A_Aux_LSB R/W AUX_A_PD - 28 1Ch DAC_B_Aux_MSB R/W AUX_B[9:2] 29 1Dh DAC_B_Aux_LSB R/W AUX_B_PD - ... - MINUS_ 3DB NOISE_ SHPER ... ... AUX_A[1:0] AUX_B[1:0] ... ... ... 10000000 80 128 00000000 00 0 10000000 80 128 00000000 00 0 DAC1205D650 10 0Ah DAC_A_Cfg_2 Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Rev. 04 — 2 July 2012 Address Register name Integrated Device Technology DAC1205D650 4 Product data sheet Table 9. DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.2.4 Registers detailed description Please refer to Table 9 for a register overview and their default values. In the following tables, all the values highlighted are the default values. Table 10. COMMon register (address 00h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 3W_SPI R/W 6 SPI_RST serial interface bus type 0 4 wire SPI 1 3 wire SPI R/W serial interface reset 0 no reset 1 5 3 2 1 0 CLK_SEL MODE_SEL CODING IC_PD GAP_PD performs a reset on all registers except 00h R/W data input latch 0 at CLK rising edge 1 at CLK falling edge R/W input data mode 0 dual-port 1 interleaved R/W coding 0 binary 1 two’s compliment R/W power-down 0 disabled 1 all circuits (digital and analog, except SPI) are switched off R/W internal bandgap power-down 0 power-down disabled 1 internal bandgap references are switched off Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 NCO_ON R/W 6 5 NCO_LP_SEL INV_SIN_SEL NCO 0 disabled (the NCO phase is reset to 0) 1 enabled R/W low-power NCO 0 disabled 1 NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively R/W x / (sin x) function 0 disabled 1 enabled DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 17 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 11. TXCFG register (address 01h) bit description …continued Default settings are shown highlighted. Bit Symbol Access Value Description 4 to 2 MODULATION[2:0] R/W 1 to 0 INTERPOLATION [1:0] modulation 000 dual DAC: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion 011 negative upper single sideband up-conversion 100 negative lower single sideband up-conversion R/W interpolation 01 2 10 4 11 8 Table 12. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit Symbol Access 7 PLL_PD R/W 5 PLL_DIV_PD Value Description PLL 0 switched on 1 switched off R/W PLL divider 0 1 4 to 3 PLL_DIV[1:0] R/W PLL_PHASE[1:0] 00 fs = 2  fclk 01 fs = 4  fclk R/W PLL_POL Table 13. 00 0 01 120 240 DAC clock edge (fs) R/W 0 normal 1 inverted FREQNCO_LSB register (address 03h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[7:0] R/W Table 14. - lower 8 bits for the NCO frequency setting FREQNCO_LISB register (address 04h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[15:8] R/W - DAC1205D650 4 Product data sheet fs = 8  fclk PLL phase shift of fs 10 0 switched off PLL divider factor 10 2 to 1 switched on lower intermediate 8 bits for the NCO frequency setting © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 18 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 15. FREQNCO_UISB register (address 05h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[23:16] R/W Table 16. - upper intermediate 8 bits for the NCO frequency setting FREQNCO_MSB register (address 06h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[31:24] R/W Table 17. - most significant 8 bits for the NCO frequency setting PHINCO_LSB register (address 07h) bit description Bit Symbol Access Value Description 7 to 0 PH_NCO[7:0] R/W Table 18. - lower 8 bits for the NCO phase setting PHINCO_MSB register (address 08h) bit description Bit Symbol Access Value Description 7 to 0 PH_NCO[15:8] R/W - most significant 8 bits for the NCO phase setting Table 19. DAC_A_Cfg_1 register (address 09h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 DAC_A_PD R/W 6 DAC_A_SLEEP DAC A power 0 on 1 off R/W DAC A Sleep mode 0 disabled 1 5 to 1 DAC_A_OFFSET[4:0] Table 20. R/W - DAC_A_Cfg_2 register (address 0Ah) bit description Bit Symbol Access Value Description 7 to 6 DAC_A_GAIN_COARSE[1:0] R/W - least significant 2 bits for the DAC A gain setting for coarse adjustment 5 to 0 DAC_A_GAIN_FINE[5:0] R/W - the 6 bits for the DAC A gain fine adjustment setting Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description Bit Symbol Access Value Description 7 to 6 DAC_A_GAIN_COARSE[3:2] R/W - most significant 2 bits for the DAC A gain setting for coarse adjustment 5 to 0 DAC_A_OFFSET[10:5] R/W - most significant 6 bits for the DAC A offset DAC1205D650 4 Product data sheet enabled lower 5 bits for the DAC A offset © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 19 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 DAC_B_PD R/W 6 5 to 1 DAC_B_SLEEP 0 on 1 off R/W DAC_B_OFFSET[4:0] Table 23. DAC B power DAC B Sleep mode 0 disabled 1 enabled R/W lower 5 bits for the DAC B offset DAC_B_Cfg_2 register (address 0Dh) bit description Bit Symbol Access Value Description 7 to 6 DAC_B_GAIN_COARSE[1:0] R/W - less significant 2 bits for the DAC B gain setting for coarse adjustment 5 to 0 DAC_B_GAIN_FINE[5:0] R/W - the 6 bits for the DAC B gain setting for fine adjustment Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description Bit Symbol Access Value Description 7 to 6 DAC_B_GAIN_COARSE[3:2] R/W - most significant 2 bits for the DAC B gain setting for coarse adjustment 5 to 0 DAC_B_OFFSET[10:5] R/W - most significant 6 bits for the DAC B offset Table 25. DAC_Cfg register (address 0Fh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 1 MINUS_3DB R/W NCO gain 0 NOISE_SHPER Table 26. 0 unity 1 3 dB R/W noise shaper 0 disabled 1 enabled DAC_A_Aux_MSB register (address 1Ah) bit description Bit Symbol Access Value Description 7 to 0 AUX_A[9:2] R/W most significant 8 bits for the auxiliary DAC A - Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 AUX_A_PD R/W auxiliary DAC A power 1 to 0 AUX_A[1:0] 0 on 1 off R/W DAC1205D650 4 Product data sheet lower 2 bits for the auxiliary DAC A © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 20 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 28. DAC_B_Aux_MSB register (address 1Ch) bit description Bit Symbol Access Value Description 7 to 0 AUX_B[9:2] R/W - most significant 8 bits for the auxiliary DAC B Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 AUX_B_PD R/W auxiliary DAC B power 1 to 0 AUX_B[1:0] 0 on 1 off R/W lower 2 bits for the auxiliary DAC B 10.3 Input data The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines whether the DAC1205D650 operates in the Dual-port mode or in the Interleaved mode (see Table 30). Table 30. Mode selection Bit 3 setting Function I11 to I0 Q11 to Q0 0 Dual-port mode, pin Q11 active active 1 Interleaved mode, pin SELIQ active off 10.3.1 Dual-port mode The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each DAC has its own independent data input. The data enters the input latch on the rising edge of the internal clock signal and is transferred to the DAC latch. FIR 1 In LATCH I Qn LATCH Q 2× FIR 1 2× FIR 2 2× FIR 2 2× FIR 3 2× FIR 3 2× 001aaj585 n in Qn = 0 to 11 and for In = 0 to 11. Fig 5. Dual-port mode DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 21 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.3.2 Interleaved mode The data input for Interleaved mode operation is shown in Figure 6 “Interleaved mode operation”. FIR 1 LATCH I FIR 2 2× FIR 3 2× 2× In FIR 1 LATCH Q Qn/SELIQ FIR 2 2× FIR 3 2× 2× 001aaj586 n in Qn = 11 and for In is 0 to 11. Fig 6. Interleaved mode operation In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, depending on the SELIQ signal; see Figure 7. The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and Q channels; see Figure 7 “Interleaved mode timing (8´ interpolation, latch on rising edge)”. In N N+1 N+2 N+3 N+4 N+5 SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLKdig Latch I output XX N N+2 Latch Q output XX N+1 N+3 001aaj814 Fig 7. Interleaved mode timing (8 interpolation, latch on rising edge) SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse) signal. The first data bits following the SELIQ rising edge are sent in channel I and following data bits are sent in channel Q. After this, the data is distributed alternately between both channels. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 22 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.4 Input clock The DAC1205D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see Figure 8) but it can also be interfaced with CML (see Figure 9). CLKINP LVDS LVDS Zdiff = 100 Ω 100 Ω CLKINN 001aah021 Fig 8. LVDS clock configuration VDDA(1V8) 1.1 kΩ 100 nF CLKINP 55 Ω CML Zdiff = 100 Ω LVDS 1 kΩ 55 Ω 100 nF CLKINN 2.2 kΩ AGND Fig 9. 001aah020 Interfacing CML to LVDS DAC1205D650 4 Product data sheet 100 nF © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 23 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.5 Timing The DAC1205D650 can operate at an update rate (fs) of up to 650 Msps and with an input data rate (fdata) of up to 160 MHz. The input timing is shown in Figure 10 “Input timing diagram”. th(i) tsu(i) In/Qn 90 % 90 % N CLK (CLKP-CLKN) N+1 N+2 50 % tw(CLK) 001aaj815 n in Qn = 0 to 11 and for In = 0 to 11. Fig 10. Input timing diagram The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. In Table 31 “Frequencies”, the links between internal and external clocking are defined. The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 12 “PLLCFG register (address 02h) bit description”) allows the frequency between the digital part and the DAC core to be adjusted. Table 31. Frequencies Mode CLK input Input data rate (MHz) (MHz) Interpolation Update rate (Msps) PLL_DIV[1:0] Dual-port 160 160 2 320 01 (/4) Dual-port 160 160 4 640 01 (/4) Dual-port 80 80 8 640 10 (/8) Interleaved 320 320 2 320 00 (/2) Interleaved 320 320 4 640 00 (/2) Interleaved 160 160 8 640 01 (/4) The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL (register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This occurs at the input of the DAC core and depends mainly on the sampling frequency. Some examples are given in Table 32 “Sample clock phase and polarity examples”. Table 32. Sample clock phase and polarity examples Mode Input data rate (MHz) Interpolation Update rate (Msps) PLL_PHASE [1:0] PLL_POL Dual-port 80 2 160 01 1 Dual-port 80 4 320 01 0 Dual-port 80 8 640 01 1 Interleaved 160 2 160 01 1 Interleaved 160 4 320 01 0 Interleaved 160 8 640 01 1 DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 24 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.6 FIR filters The DAC1205D650 integrates three selectable Finite Impulse Response (FIR) filters which enable the device to use interpolation rates of 2, 4 or 8. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in Table 33 “Interpolation filter coefficients”. Table 33. Interpolation filter coefficients First interpolation filter[1] Second interpolation filter[1] Third interpolation filter[1] Lower Upper Value Lower Upper Value Lower Upper Value H(1) H(55) 4 H(1) H(23) 2 H(1) H(15) 39 H(2) H(54) 0 H(2) H(22) 0 H(2) H(14) 0 H(3) H(53) 13 H(3) H(21) 17 H(3) H(13) 273 H(4) H(52) 0 H(4) H(20) 0 H(4) H(12) 0 H(5) H(51) 34 H(5) H(19) 75 H(5) H(11) 1102 H(6) H(50) 0 H(6) H(18) 0 H(6) H(10) 0 H(7) H(49) 72 H(7) H(17) 238 H(7) H(9) 4964 H(8) H(48) 0 H(8) H(16) 0 H(8) - 8192 H(9) H(47) 138 H(9) H(15) 660 - - - H(10) H(46) 0 H(10) H(14) 0 - - - H(11) H(45) 245 H(11) H(13) 2530 - - - H(12) H(44) 0 H(12) - 4096 - - - H(13) H(43) 408 - - - - - - H(14) H(42) 0 - - - - - - H(15) H(41) 650 - - - - - - H(16) H(40) 0 - - - - - - H(17) H(39) 1003 - - - - - - H(18) H(38) 0 - - - - - - H(19) H(37) 1521 - - - - - - H(20) H(36) 0 - - - - - - H(21) H(35) 2315 - - - - - - H(22) H(34) 0 - - - - - - H(23) H(33) 3671 - - - - - - H(24) H(32) 0 - - - - - - H(25) H(31) 6642 - - - - - - H(26) H(30) 0 - - - - - - H(27) H(29) 20756 - - - - - - 32768 - - - - - - H(28) [1] H(n) is the digital filter coefficient. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 25 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.7 Quadrature modulator and NCO The quadrature modulator allows the 12-bit I and Q data to be mixed with the carrier signal generated by the Numerically Controlled Oscillator (NCO). The frequency of the NCO is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion. 10.7.1 NCO in 32-bit When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M  fs f NCO = -------------32 2 (1) where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0. 10.7.2 Low-power NCO When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: M  fs f NCO = -------------5 2 (2) where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB. 10.7.3 Minus 3dB During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers. 10.8 x / (sin x) Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 34 “Inversion filter coefficients”. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 26 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 34. Inversion filter coefficients First interpolation filter[1] Lower Upper Value H(1) H(9) 2 H(2) H(8) 4 H(3) H(7) 10 H(4) H(6) 35 H(5) - 401 [1] H(n) is the digital filter coefficient. 10.9 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs: (3) I O  fs  = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O  fs    ----------------  4095  (4) 4095 – DATA I IOUTN = I O  fs    ----------------------------------   4095 (5) The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”) defines whether the DAC1205D650 operates with a binary input or a two’s complement input. Table 35 “DAC transfer function” shows the output current as a function of the input data, when IO(fs) = 20 mA. Table 35. DAC transfer function Data (Decimal) I11/Q11 to I0/Q0 Binary Two’s complement 0 0000 0000 0000 1000 0000 0000 IOUTP IOUTN 0 mA 20 mA ... ... ... ... ... 2048 1000 0000 0000 0000 0000 0000 10 mA 10 mA ... ... ... ... ... 4095 1111 1111 1111 0111 1111 1111 20 mA 0 mA 10.10 Full-scale current 10.10.1 Regulation The DAC1205D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.29 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 27 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating The reference current is generated using an external resistor of 953  (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs (see Figure 11 “Internal reference configuration”). VDDA(1V8) REF. BANDGAP 100 kΩ 100 nF AGND AGND 953 Ω (1 %) GAPOUT VIRES DAC CURRENT SOURCES ARRAY aaa-002266 Fig 11. Internal reference configuration This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit description”). 10.10.2 Full-scale current adjustment The default full-scale current (IO(fs)) is 20 mA. It can be further adjusted for each DAC using SPI. The adjustment range is between 1.6 mA and 22 mA,  10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 20 “DAC_A_Cfg_2 register (address 0Ah) bit description” and register 0Bh; see Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit description”) and to DAC_B_GAIN COARSE[3:0] (register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description” and register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define the coarse variation of the full-scale current (see Table 36 “IO(fs) coarse adjustment”). Table 36. IO(fs) coarse adjustment Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] IO(fs) (mA) Decimal Binary 0 0000 1.6 1 0001 3.0 2 0010 4.4 3 0011 5.8 4 0100 7.2 5 0101 8.6 6 0110 10.0 7 0111 11.4 DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 28 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 36. IO(fs) coarse adjustment …continued Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] IO(fs) (mA) Decimal Binary 8 1000 12.8 9 1001 14.2 10 1010 15.6 11 1011 17.0 12 1100 18.5 13 1101 20.0 14 1110 21.0 15 1111 22.0 The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 20 “DAC_A_Cfg_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0] (register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description”) define the fine variation of the full-scale current (see Table 37 “IO(fs) fine adjustment”). Table 37. IO(fs) fine adjustment Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Delta IO(fs) Decimal Two’s complement 32 10 0000 10 % ... ... ... 0 00 0000 0 ... ... ... +31 01 1111 +10 % The coding of the fine gain adjustment is two’s complement. 10.11 Digital offset adjustment When the DAC1205D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. The settings applied to DAC_A_OFFSET[10:0] (register 09h; see Table 19 “DAC_A_Cfg_1 register (address 09h) bit description” and register 0Bh; see Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit description”) and to “DAC_B_OFFSET[10:0]” (register 0Ch; see Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description” and register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define the range of variation of the digital offset (see Table 38 “Digital offset adjustment”). DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 29 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Table 38. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[10:0] Offset applied Decimal Two’s complement 1024 100 0000 0000 1024 1023 100 0000 0001 1023 ... ... ... 1 111 1111 1111 1 0 000 0000 0000 0 +1 000 0000 0001 +1 ... ... ... +1022 011 1111 1110 +1022 +1023 011 1111 1111 +1023 10.12 Analog output The DAC1205D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). Refer to Figure 12 “Equivalent analog output circuit (one DAC)” for the equivalent analog output circuit of one DAC. This circuit consists of a parallel combination of NMOS current sources, and their associated switches, for each segment. VDDA(3V3) RL RL IOUTAP/IOUTBP IOUTAN/IOUTBN AGND AGND 001aah019 Fig 12. Equivalent analog output circuit (one DAC) The cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of the DAC by introducing less distortion. The device can provide an output level of up to 2 Vo(p-p) depending on the application, the following stages and the targeted performances. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 30 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.13 Auxiliary DACs The DAC1205D650 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] define the offset data: (6) I O  AUX  = I AUXP + I AUXN The output current depends on the auxiliary DAC data: AUX  9:0  AUXP = I O  AUX    -------------------------  1023  (7) 1023 – A UX  9:0   AUXN = I O  AUX    -------------------------------------------   1023 (8) Table 39 “Auxiliary DAC transfer function” shows the output current as a function of the auxiliary DAC data. Table 39. Auxiliary DAC transfer function Default settings are shown highlighted. Data AUX_A[9:0] and AUX_B[9:0] (binary) IAUXP IAUXN 0 00 0000 0000 2.2 mA ... ... ... ... 512 10 0000 0000 1.1 mA 1.1 mA ... ... ... ... 1023 11 1111 1111 2.2 mA 0 mA DAC1205D650 4 Product data sheet 0 mA © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 31 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.14 Output configuration 10.14.1 Basic output configuration The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 13 “Differential output with transformer; Vo(dif)(p-p) = 1 V”). In addition, it helps to match the impedance and provides electrical isolation. VDDA(3V3) 50 Ω 0 mA to 20 mA 2:1 IOUTnP 50 Ω 0 mA to 20 mA IOUTnN 50 Ω VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V 001aaj817 Fig 13. Differential output with transformer; Vo(dif)(p-p) = 1 V The DAC1205D650 can operate up to 2 Vo(p-p) differential outputs. In this configuration, it is recommended to connect the center tap of the transformer to a 62  resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 14 “Differential output with transformer; Vo(dif)(p-p) = 2 V”). VDDA(3V3) 100 Ω VDDA(3V3) 62 Ω 0 mA to 20 mA 4:1 IOUTnP 50 Ω 0 mA to 20 mA IOUTnN 100 Ω VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V 001aaj818 Fig 14. Differential output with transformer; Vo(dif)(p-p) = 2 V 10.14.2 DC interface to an AQM When the system operation requires to keep the DC component of the spectrum, the DAC1205D650 can use a DC interface to connect to an Analog Quadrature Modulator (AQM). In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 32 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Figure 15 provides an example of a connection to an AQM with a 1.7 V common mode input level. AQM (Vi(cm) = 1.7 V) VDDA(3V3) 51.1 Ω (1) 51.1 Ω (2) 442 Ω IOUTnP BBP 442 Ω BBN IOUTnN 0 mA to 20 mA 768 Ω 768 Ω (1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V 001aaj541 Fig 15. An example of a DC interface to a 1.7 Vi(cm) AQM Figure 16 provides an example of a connection to an AQM with a 3.3 V common mode input level. VDDA(3V3) (1) 54.9 Ω AQM (Vi(cm) = 3.3 V) 5V 54.9 Ω 750 Ω (2) 750 Ω 237 Ω IOUTnP BBP 237 Ω IOUTnN BBN 1.27 kΩ 1.27 kΩ (1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V 001aaj542 Fig 16. An example of a DC interface to a 3.3 Vi(cm) AQM The auxiliary DACs can be used to control the offset in a precise range or with precise steps. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 33 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 V common mode input level. VDDA(3V3) 51.1 Ω (1) AQM (Vi(cm) = 1.7 V) 51.1 Ω (2) 442 Ω IOUTnP BBP 442 Ω IOUTnN BBN 0 mA to 20 mA 698 Ω 698 Ω 51.1 Ω 51.1 Ω AUXnP AUXnN 1.1 mA (typ.) (1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 36 mV 001aaj543 Fig 17. An example of a DC interface to a 1.7 Vi(cm) AQM using auxiliary DACs Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 V common mode input level. 3.3 V 54.9 Ω (1) AQM (Vi(cm) = 3.3 V) 5V 54.9 Ω 750 Ω 750 Ω (2) 237 Ω IOUTnP BBP 237 Ω IOUTnN BBN 634 Ω 634 Ω 442 Ω 442 Ω AUXnP AUXnN (1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV 001aaj544 Fig 18. An example of a DC interface to a 3.3 Vi(cm) AQM using auxiliary DACs The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the offset correction range. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 34 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.14.3 AC interface to an AQM When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground, the DAC1205D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 18 provides an example of a connection to an AQM with a 0.5 V common mode input level using auxiliary DACs. VDDA(3V3) 66.5 Ω (1) AQM (Vi(cm) = 0.5 V) 5V 66.5 Ω 2 kΩ (2) 2 kΩ 10 nF IOUTnP BBP 10 nF IOUTnN BBN 0 mA to 20 mA 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) (1) IOUTnP/IOUTnN; V o(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV 001aaj589 Fig 19. An example of an AC interface to a 0.5 Vi(cm) AQM using auxiliary DACs 10.15 Power and grounding In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with those on pins 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following pins: • VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49. • VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59. • VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98. • VDDA(3V3): pin 1 with 100 and pin 75 with 76. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 35 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10.16 Alternative parts The following alternative parts are available. Table 40. Alternative parts Type number Description Sampling frequency DAC1005D650 dual 10-bit DAC up to 650 Msps DAC1405D650 dual 14-bit DAC up to 650 Msps DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 36 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 c y exposed die pad side X Dh A 75 51 76 50 ZE e E HE Eh A A2 (A3) A1 w M θ bp Lp pin 1 index L detail X 26 100 1 25 bp e w M ZD v M A D B HD v M B 0 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. 1.2 mm A1 A2 A3 bp c D(1) Dh E(1) Eh e 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 7.1 6.1 14.1 13.9 7.1 6.1 0.5 HD HE 16.15 16.15 15.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) θ 1.15 0.85 7° 0° 1.15 0.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-02-02 MS-026 Fig 20. Package outline SOT638-1 (HTQFP100) DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 37 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 12. Abbreviations Table 41. Abbreviations Acronym Description CDMA Code Division Multiple Access CML Current Mode Logic CMOS Complementary Metal-Oxide Semiconductor DAC Digital-to-Analog Converter FIR Finite Impulse Response GSM Global System for Mobile communications IF Intermediate Frequency IMD3 Third-order Inter Modulation Distortion LISB Lower Intermediate Significant Byte LMDS Local Multipoint Distribution Service LSB Least Significant Bit LTE Long Term Evolution LVDS Low-Voltage Differential Signaling MMDS Multichannel Multipoint Distribution Service MSB Most Significant Bit NCO Numerically Controlled Oscillator NMOS Negative Metal-Oxide Semiconductor PLL Phase-Locked Loop SFDR Spurious-Free Dynamic Range SPI Serial Peripheral Interface TD-SCDMA Time Division-Synchronous Code Division Multiple Access UISB Upper Intermediate Significant Byte WCDMA Wideband Code Division Multiple Access WiMAX Worldwide Interoperability for Microwave Access DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 38 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined below. IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst 2nd order intermodulation product. IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst 3rd order intermodulation product. Restricted Bandwidth Spurious-Free Dynamic Range — The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise, including the harmonics, in a given bandwidth centered around foffset. DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 39 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 14. Revision history Table 42. Revision history Document ID Release date Data sheet status Change notice Supersedes DAC11205D650 v.4 20120702 Product data sheet - DAC1205D650 v.3 DAC11205D650 v.3 20120410 Product data sheet - DAC1205D650 v.2 Modifications: • • • • Section 2 “Features and benefits” has been updated. The values for VO(ref) in Table 5 “Characteristics” have been updated. Section 10.2.1 “Protocol description” has been updated. Section 10.10.1 “Regulation” has been updated. DAC1205D650 v.2 20100913 Product data sheet - DAC1205D650 v.1 DAC1205D650 v.1 20090728 Product data sheet - - 15. Contact information For more information or sales office addresses, please visit: http://www.idt.com DAC1205D650 4 Product data sheet © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 40 of 41 DAC1205D650 Integrated Device Technology Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.3 10.3.1 10.3.2 10.4 10.5 10.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 13 General description . . . . . . . . . . . . . . . . . . . . 13 Serial interface (SPI) . . . . . . . . . . . . . . . . . . . 13 Protocol description . . . . . . . . . . . . . . . . . . . . 13 SPI timing description . . . . . . . . . . . . . . . . . . . 14 Detailed descriptions of registers . . . . . . . . . . 15 Registers detailed description. . . . . . . . . . . . . 17 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 21 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 22 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.7 10.7.1 10.7.2 10.7.3 10.8 10.9 10.10 10.10.1 10.10.2 10.11 10.12 10.13 10.14 10.14.1 10.14.2 10.14.3 10.15 10.16 11 12 13 14 15 16 DAC1205D650 4 Product data sheet Quadrature modulator and NCO . . . . . . . . . . NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . Low-power NCO . . . . . . . . . . . . . . . . . . . . . . Minus 3dB . . . . . . . . . . . . . . . . . . . . . . . . . . . x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC transfer function. . . . . . . . . . . . . . . . . . . Full-scale current . . . . . . . . . . . . . . . . . . . . . . Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . Full-scale current adjustment. . . . . . . . . . . . . Digital offset adjustment. . . . . . . . . . . . . . . . . Analog output. . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . Output configuration. . . . . . . . . . . . . . . . . . . . Basic output configuration . . . . . . . . . . . . . . . DC interface to an AQM. . . . . . . . . . . . . . . . . AC interface to an AQM . . . . . . . . . . . . . . . . . Power and grounding. . . . . . . . . . . . . . . . . . . Alternative parts . . . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 26 26 27 27 27 28 29 30 31 32 32 32 35 35 36 37 38 39 40 40 41 © IDT 2012. All rights reserved. Rev. 04 — 2 July 2012 41 of 41