IDTQS5917T-70TQG

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • • • • • • • • • • • • • QS5917T DESCRIPTION 5V operation 2xQ output, Q/2 output, Q output Outputs tri-state while RST low Internal loop filter RC network Low noise TTL level outputs < 500ps output skew, Q0-Q4 PLL disable feature for low frequency testing Balanced Drive Outputs ± 24mA 132MHz maximum frequency (2xQ output) Functional equivalent to Motorola MC88915 ESD > 2000V Latch-up > –300mA Available in QSOP and PLCC packages The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5917T is designed for use in high-performance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL SYNC0 0 SYNC1 1 PHASE DETECTOR RST R D FEEDBACK LOCK R D R D LOOP FILTER R D D FREQ_SEL 0 1 1 VCO R PLL_EN R /2 D 0 R D Q Q Q Q Q Q Q Q Q/2 Q5 Q4 Q3 Q2 Q1 Q0 2xQ The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2006 1 © 2006 Integrated Device Technology, Inc. DSC-5227/4 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE GND 1 28 Q4 Q5 2 27 VDD RST VDD Q5 GND Q4 VDD 2xQ VDD 3 26 2xQ 4 3 2 1 28 27 26 RST 4 25 Q/2 FEEDBACK 5 24 GND REF_SEL 6 23 Q3 SYNC0 7 22 VDD AVDD 8 21 Q2 NC 9 20 GND AGND 10 19 LOCK SYNC1 11 18 PLL_EN 12 13 FREQ_SEL 12 17 GND 13 16 Q1 GND GND Q0 14 15 VDD FREQ_SEL PIN CONFIGURATION Q/2 REF_SEL 6 24 GND SYNC0 7 23 Q3 AVDD 8 22 VDD NC 9 21 Q2 AGND 10 20 GND SYNC1 11 19 LOCK ABSOLUTE MAXIMUM RATINGS(1) TSTG Rating 17 18 PLL_EN 16 GND 15 PLCC TOP VIEW QSOP TOP VIEW Symbol 14 Q1 25 VDD 5 Q0 FEEDBACK Max Unit Supply Voltage to Ground –0.5 to +7 V DC Input Voltage VIN CAPACITANCE (TA = +25°C, f = 1.0MHz, VIN = 0V) QSOP PLCC –0.5 to +7 V Parameter Typ. Max. Typ. Max. Unit AC Input Voltage (pulse width ≤ 20ns) –3 V CIN 3 4 4 6 pF Maximum Power Dissipation (TA = 85°C) 1.2 W COUT 7 9 8 10 pF –65 to +150 °C Storage Temperature Range NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Names I/O Description SYNC 0 I Reference clock input SYNC 1 I Reference clock input REF_SEL I Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0. FREQ_SEL I VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. FEEDBACK I PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Q0 -Q4 O Clock outputs Q5 O Clock output. Matched in frequency, but inverted with respect to Q. 2xQ O Clock output. Matched in phase, but frequency is double the Q frequency. Q/2 O Clock output. Matched in phase, but frequency is half the Q frequency. LOCK O PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. RST I Asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled (normal operation). PLL_EN I PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes). NC — No Connection OUTPUT FREQUENCY SPECIFICATIONS Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5% Symbol F2XQ Description – 70 – 100 – 132 Units Max Frequency, 2xQ output 70 100 132 MHz FQ Max Frequency, Q0 - Q4, Q5 outputs 35 50 66 MHz FQ/2 Max Frequency, Q/2 output 17.5 25 33 MHz 3 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE SYNC (MHz) FREQ_SEL Output Used for Feedback (allowable range) Min. Max 1 Q/2 14 F2XQ / 4 1 Q0 -Q4 28 1 Q5 28 1 2xQ Output Frequency Relationships Q5 Q Outputs Q/2 2XQ SYNC – SYNC X 2 SYNC X 2 SYNC X 4 F2XQ / 2 SYNC / 2 – SYNC SYNC SYNC X 2 F2XQ / 2 – SYNC / 2 SYNC – SYNC – SYNC X 2 56 F2XQ (1) SYNC / 4 – SYNC / 2 SYNC / 2 SYNC 0 Q/2 7 F2XQ / 8 SYNC – SYNC X 2 SYNC X 2 SYNC X 4 0 Q0 -Q4 14 F2XQ / 4 SYNC / 2 – SYNC SYNC SYNC X 2 0 Q5 14 F2XQ / 4 – SYNC / 2 SYNC – SYNC – SYNC X 2 0 2xQ 28 F2XQ / 2 SYNC / 4 – SYNC / 2 SYNC / 2 SYNC NOTE: 1. For the –132 speed grade, maximum input frequency is restricted to 100MHz. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit 2 — — V VIH Input HIGH Voltage Level Guaranteed Logic HIGH level VIL Input LOW Voltage Level Guaranteed Logic LOW level — — 0.9 V VOH Output HIGH Voltage VDD = Min., IOH = −24mA (1) 2.4 — — V VDD = Min., IOH = −100μA 3 — — 24mA (1) — — 0.55 — — 0.2 VOL Output LOW Voltage VDD = Min., IOL = VDD = Min., IOL = 100μA V IOZ Output Leakage Current VOUT = VDD or GND, VDD = Max. — — ±5 μA IIN Input Leakage Current VIN = AVDD or GND, AVDD = Max. — — ±5 μA NOTE: 1. IOL and IOH are 12mA and –12mA, respectively, for the LOCK output. POWER SUPPLY CHARACTERISTICS Symbol Test Conditions (1) Parameter ΔICC Input Power Supply Current per TTL Input HIGH (2) ICCD Dynamic Power Supply Current Typ. Max. Unit VDD = Max., VIN = 3.4V 0.4 1.5 mA VDD = Max — 0.4 mA/MHz NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. This specification does not apply to the PLL_EN input. 4 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE INPUT TIMING REQUIREMENTS Symbol t R , tF FI Description Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC0, SYNC1 (1) Min. Max. Unit — 3 ns 14 F2XQ MHz tPWC Input clock pulse, HIGH or LOW 2 — ns DH Duty cycle, SYNC0, SYNC1 25 75 % NOTE: 1. The FI specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations. SWITCHING CHARACTERISTICS(1) Symbol tSKR tSKF tSKALL Parameter Output Skew Between Rising Edges, Q0-Q4 and Q/2 (1) Min. — Max. 350 Unit ps Output Skew Between Falling Edges, Q0-Q4 (1) — 350 ps Output Skew, All Outputs — 500 ps TCY/2 − 0.65 TCY/2 + 0.65 ns TCY/2 − 0.5 TCY/2 + 0.5 ns — 0.25 ns ps (1) tPW Pulse Width, Q5, 2xQ outputs tPW Pulse Width, Q0-Q4, Q/2 outputs (1) tJ Cycle-to-Cycle Jitter, 33MHz tPD SYNC Input to Feedback Delay, 28MHz − 100 400 tPD SYNC Input to Feedback Delay, 33MHz, 50Ω to 1.5V (3) − 100 400 ps tLOCK SYNC to Phase Lock — 10 ms tPZH tPZL Output Enable Time, RST LOW to HIGH (2) 0 7 ns tPHZ tPLZ Output Disable Time, RST HIGH to LOW (2) 0 6 ns tR, tF Output Rise/Fall Times, 0.8V to 2V 0.4 1.5 ns NOTES: 1. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 2. Measured in open loop mode PLL_EN = 0. 3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input frequencies. 5 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE TEST LOAD VDD 300Ω 160Ω 7.0V OUTPUT OUTPUT 20pF 68Ω 300Ω 30pF TEST CIRCUIT 1 TEST CIRCUIT 2 TEST CIRCUIT 2 is used for output enable/disable parameters. TEST CIRCUIT 1 is used for all other timing parameters. PLL OPERATION PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, ‘propagation delay’ can even be negative! A simplified schematic of the QS5917T PLL circuit is shown below. The Phase Locked Loop (PLL) circuit included in the QS5917T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the SIMPLIFIED DIAGRAM OF QS5917T FEEDBACK Q 2xQ INPUT VCO /2 Q/2 Q /2 PHASE DETECTOR The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5917T typically provides within 150ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 6 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type XX Speed X Package X Process CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 Blank Industrial (-40°C to +85°C) Q QG J JG Quarter Size Outline Package QSOP - Green Plastic Leaded Chip Carrier PLCC - Green -70T -100T -132T 70MHz Max. Frequency 100MHz Max. Frequency 132MHz Max. Frequency 5917T Low Skew CMOS PLL Clock Driver with Integrated Loop Filter for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: logichelp@idt.com