DATASHEET
ADVANCE INFORMATION
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
General Description
Features
The VP386 is an ideal LVDS receiver that converts 4-pair
LVDS data streams into parallel 28 bits of CMOS/TTL data
with bandwidth up to 2.8 Gbps throughput or 350 Mbytes
per second.
• Wide clock frequency range from 20 MHz to 100 MHz
• Pin compatible with the National DS90CF386, THine
THC63LVDF84, TISN65LVDS94
• Converts 4-pair LVDS data streams into parallel 28 bits of
CMOS/TTL data
This chip is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces
through very low-swing LVDS signals.
•
•
•
•
•
•
•
•
Fully spread spectrum compatible
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Low-power CMOS design
Falling edge clock triggered outputs
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
RxIN0+
RED
8
GREEN
8
BLUE
RxIN0RxIN1+
LVDS to TTL
RxIN1-
De-serializer
RxOUT0...27
8
RxIN2+
HSYNC
RxIN2-
VSYNC
RxIN3+
DATA ENABLE
RxIN3-
CONTROL
RxCLKIN+
RxCLKOUT
PLL
RxCLKINPWRDWN
VP386
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Pin Assignment
RxOUT22
1
56
VCC
RxOUT23
2
55
RxOUT21
RxOUT24
3
54
RxOUT20
GND
4
53
RxOUT19
RxOUT25
5
52
GND
RxOUT26
6
51
RxOUT18
RxOUT27
7
50
RxOUT17
LVDS_GND
8
49
RxOUT16
RxIN0-
9
48
VCC
RxIN0+
10
47
RxOUT15
RxIN1-
11
46
RxOUT14
RxIN1+
12
45
RxOUT13
LVDS_VCC
13
44
GND
LVDS_GND
14
43
RxOUT12
RxIN2-
15
42
RxOUT11
RxIN2+
16
41
RxOUT10
RxCLKIN-
17
40
VCC
RxICLKN+
18
39
RxOUT9
RxIN3-
19
38
RxOUT8
RxIN3+
20
37
RxOUT7
LVDS_GND
21
36
GND
PLL_GND
22
35
RxOUT6
PLL_VCC
23
34
RxOUT5
PLL_GND
24
33
RxOUT4
PWRDWN
25
32
RxOUT3
RxCLKOUT
26
31
VCC
RxOUT0
27
30
RxOUT2
GND
28
29
RxOUT1
56-pin TSSOP
VP386
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
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IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Pin Descriptions
Pin No.
Pin Name
1
RxOUT22
2
RxOUT23
3
RxOUT24
4
GND
5
RxOUT25
6
RxOUT26
7
RxOUT27
8
LVDS_GND
9
RxIN0-
10
RxIN0+
11
RxIN1-
12
RxIN1+
13
LVDS_VCC
Power
Analog power
14
LVDS_GND
Ground
Analog ground
15
RxIN2-
LVDS input (-)
16
RxIN2+
LVDS input (+)
17
RxCLKIN-
18
RxCLKIN+
19
RxIN3-
LVDS input (-)
20
RxIN3+
LVDS input (+)
21
LVDS_GND
22
PLL_GND
23
PLL_VCC
Power
PLL power
24
PLL_GND
Ground
PLL ground
25
PWRDWN
IN
Power-down control input.
H: Nomal
L: Power down, all ouputs are pulled low.
26
RxCLKOUT
27
RxOUT0
28
GND
29
RxOUT1
30
RxOUT2
31
VCC
32
RxOUT3
33
RxOUT4
34
RxOUT5
8/28-BIT LVDS RECEIVER FOR VIDEO
Pin Type
Pin Description
OUT
Data outputs on pins (RxOUT0..27)
Ground
Digital ground
OUT
Data outputs on pins (RxOUT0..27)
Ground
Analog ground
LVDS input (-)
LVDS IN
LVDS input (+)
LVDS input (-)
LVDS input (+)
LVDS IN
Ground
OUT
Ground
OUT
LVDS input (-)
LVDS input (+)
Analog ground
PLL ground
Clock output
Data outputs on pins (RxOUT0..27)
Digital ground
Data outputs on pins (RxOUT0..27)
Power
Digital power
OUT
Data outputs on pins (RxOUT0..27)
3
IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Pin No.
Pin Name
Pin Type
Pin Description
35
RxOUT6
OUT
Data outputs on pins (RxOUT0..27)
36
GND
Ground
Digital ground
37
RxOUT7
38
RxOUT8
OUT
Data outputs on pins (RxOUT0..27)
39
RxOUT9
40
VCC
Power
Digital power
41
RxOUT10
42
RxOUT11
OUT
Data outputs on pins (RxOUT0..27)
43
RxOUT12
44
GND
Ground
Digital ground
45
RxOUT13
46
RxOUT14
OUT
Data outputs on pins (RxOUT0..27)
47
RxOUT15
48
VCC
Power
Digital power
49
RxOUT16
50
RxOUT17
OUT
Data outputs on pins (RxOUT0..27)
51
RxOUT18
52
GND
Ground
Digital ground
53
RxOUT19
54
RxOUT20
OUT
Data outputs on pins (RxOUT0..27)
55
RxOUT21
56
VCC
Power
Digital power
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
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IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings
Rating1
Item
Supply Voltage, VCC
-0.3 V to +4 V
CMOS/TTL Output Voltage
-0.3 V to (VCC+0.3 V)
LVDS Receiver Input Voltage
-0.3 V to (VCC+0.3 V)
Ambient Operating Temperature
0 to +70°C
Storage Temperature
-65 to +150°C
Junction Temperature
150°C
Soldering Temperature (10 seconds max.)
260°C
Maximum Package Power
1.61 W (VP386)
12.4 mW/°C above +25°C
Package Derating
15 mW/°C above +25°C
1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (Ta)
0
25
70
°C
3.3 V Supply Voltage (VCC)
3
3.3
3.6
V
Receiver Input Range (VIN)
0
2.4
V
100
mVpp
Supply Noise Voltage (VN)
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
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IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to 70°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
CMOS/TTL DC Specifications
Input High Voltage
VIH
2.0
VCC
V
Input Low Voltage
VIL
GND
0.8
V
Output High Voltage
VOH
IOH = -0.4 mA
3.3
VCC
V
Output Low Voltage
VOL
IOL = 2 mA
0.06
0.3
V
Input Clamp Voltage
VCL
ICL = -18mA
-0.79
-1.5
V
VCC
±15
µA
0V
±10
IOS
VOUT = 0V
-60
mA
Differential Input High Threshold
VTH
VCM = +1.2 V
+100
mV
Differential Input Low Threshold
VTL
Input Current
IIN
Input Current
Output Short Circuit Current
IIN
2.7
LVDS Receiver DC Specifications
-100
mV
VIN = +2.4 V, VCC = 3.6 V
±10
µA
VIN = 0V, VCC = 3.6 V
±15
µA
CL = 8 pF, f = 65 MHz,
worst case pattern
220
mA
CL = 8 pF, f = 100 MHz,
worst case pattern
240
mA
CL= 8 pF, f = 65 MHz, 16
Grayscale pattern
125
mA
CL= 8 pF, f = 100 MHz, 16
Grayscale pattern
140
mA
Receiver Supply Current
Receiver Supply Current (worst case)
Receiver Supply Current (16 Grayscale)
ICCRW
ICCRG
ICCRZ
Power_Down = Low,
Receiver outputs stay low
during Power-down mode
140
400
µA
CMOS/TTL Low-to-High Transition Time
CLHT
20% to 80% VCC, CL= 8
pF
2
3.5
ns
CMOS/TTL High-to-Low Transition Time
CHLT
80% to 20% VCC, CL= 8
pF
1.8
3.5
ns
CLKOUT period
RCOP
T
50
ns
CLKOUT High Time
RCOH
4T/7
ns
CLKOUT Low Time
RCOL
3T/7
ns
Data Setup to CLKOUT
RSRC
0.35T-0.3
ns
Data Hold to CLKOUT
RHRC
0.45T-1.6
ns
Receiver Supply Current (Power Down)
Receiver Switching Characteristics
8/28-BIT LVDS RECEIVER FOR VIDEO
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6
IDTVP386
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IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
Parameter
COMMERCIAL TEMPERATURE RANGE
Symbol
Conditions
Min.
25°C / 3.3 V, 85MHz
Typ.
Max.
Units
RCK+/- to CLKOUT Delay
RCCD
14.6
ns
Receiver PLL Setup Time
RPLLS
10
ms
Receiver Power Down Delay
RPDD
1
µs
Receiver Input Strobe Position for Bit0
RSPos0
-0.25
0
0.25
ns
Receiver Input Strobe Position for Bit1
RSPos1
T/7-0.25
T/7
T/7+0.25
ns
Receiver Input Strobe Position for Bit2
RSPos2
2T/7-0.25
2T/7
2T/7+0.25
ns
Receiver Input Strobe Position for Bit3
RSPos3 f = 100 MHz, T = 10 ns
3T/7-0.25
3T/7
3T/7+0.25
ns
Receiver Input Strobe Position for Bit4
RSPos4
4T/7-0.25
4T/7
4T/7+0.4
ns
Receiver Input Strobe Position for Bit5
RSPos5
5T/7-0.25
5T/7
5T/7+0.25
ns
Receiver Input Strobe Position for Bit6
RSPos6
6T/7-0.25
6T/7
6T/7+0.25
ns
RxIn Skew Margin
(see note and Figure 8)
Rskm
f = 100 MHz, T = 10 ns
250
ps
f = 65 MHz, T = 15.38 ns
500
ps
Note: The skew margins mean the maximum timing tolerance between the clock and data channel when the receiver still
works well. This margin takes into acount the receiver input setup and hold time, and internal clock jitter (i.e., internal data
sampling window - RSPos). Thyis margin allows for LVDS transmitter pulse position, interconnect skew, inter-symbol
interference and intrinsic channel mismatch which will cause the skew between clock (RC+ and RCK-) and data (RX[n]+
and RX[n]- ; n =0, 1, 2, 3) channels.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
8/28-BIT LVDS RECEIVER FOR VIDEO
Symbol
Conditions
Min.
Typ.
Max.
Units
θJA
Still air
84
°C/W
θJA
1 m/s air flow
76
°C/W
θJA
2 m/s air flow
67
°C/W
50
°C/W
θJA
7
IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Timing Diagrams
CLKIN/CLKOUT
ODD Data In/Data Out
EVEN Data In/Data Out
T
Figure 1. “Worst Case” Test Pattern
CLKOUT
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4-7, 12-15, 20-23
D24-27
Figure 2. 16-Grayscale Test-Pattern Waveforms
CMOS/TTL Output
80%
80%
20%
8 pF
20%
CLHT
CHLT
Figure 3. VP386 CMOS/TTL Output Load and Transition Time
RCOP
2.0 V
CLKOUT
0.8 V
2.0 V
2.0 V
0.8 V
RCOH
RCOL
RSRC
RHRC
D0 - D27 Out
2.0 V
SETUP
2.0 V
HOLD
Figure 4. VP386 SETUP/HOLD and High/Low Times
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
RCK
Vdiff=0V
RCOP
1.5V
CLKOUT
Figure 5. VP386 Clock In to Clock Out Delay
PWRDWN
2.0 V
3.6 V
3.0 V
VCC
RPLLS
RCK
CLKOUT
Figure 6. VP386 Phase Lock Loop Set Time
1.5 V
PWRDWN
RCK IN
RPDD
Low
Figure 7. VP386 Power Down Delay
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
ClocK
Previous Cycle
Next Cycle
Data
Rspos0 Min
Rspos0 Max
Rspos1 Min
Rspos1 Max
Rspos2 Min
Rspos2 Max
Rspos3 Min
Rspos3 Max
Rspos4 Min
Rspos4 Max
Rspos5 Min
Rspos5 Max
Rspos6 Min
Rspos6 Max
Figure 8. VP386 LVDS Input Strobe Position
RCK+/RCKSkew Margin
RX[n]+/RX[n]N = 0, 1, 2, 3
Figure 9. Receiver Input Skew Margin
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Package Outline and Package Dimensions (56-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
56
E
E1
INDEX
AREA
1
2
C
D
α
L
A2
A
A1
-CSEATING
PLANE
e
b
aaa C
SYMBOL
A
In Millimeters
COMMON DIMENSIONS
In Inches1
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
—
1.20
—
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.0032
.041
b
0.17
0.27
.007
.011
C
0.09
0.20
.0035
.008
D
13.90
14.10
.547
E
E1
8.10 BASIC
6.00
e
.555
.319 BASIC
6.20
.236
0.50 BASIC
.244
.020 BASIC
L
0.45
0.75
.018
.030
α
0°
8°
0°
8°
aaa
—
0.10
—
.004
1. For reference only. Controlling dimensions are in mm.
8/28-BIT LVDS RECEIVER FOR VIDEO
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IDTVP386
7129/3
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
COMMERCIAL TEMPERATURE RANGE
Ordering Information
IDTVP
XXXX
Device Type
XX
Package
X
X
Temp. Range Shipping
Carrier
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
8
Blank
Tape and Reel
Tube
Blank
Commercial (0°C to +70°C)
PAG
56-pin TSSOP
386
8-Bit LVDS Receiver
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: videohelp@idt.com
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology,
Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify
products or services of their respective owners.
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