ISL1208
®
I2C® Real Time Clock/Calendar
Data Sheet
July 29, 2005
Low Power RTC with Battery Backed
SRAM
Features
The ISL1208 device is a low power real time clock with
timing and crystal compensation, clock/calendar, power fail
indicator, periodic or polled alarm, intelligent battery backup
switching and battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• 15 Selectable Frequency Outputs
• Single Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
• Power Failure Detection
• On-Chip Oscillator Compensation
Ordering Information
PART NUMBER MARKING
FN8085.3
VDD
RANGE
TEMP.
RANGE
(°C)
• 2 Bytes Battery-Backed User SRAM
PACKAGE
• I2C Interface
- 400kHz Data Transfer Rate
ISL1208IU8
AGS
YWW
2.7V to
5.5V
-40 to
+85
8 Ld MSOP
ISL1208IU8-TK
AGS
YWW
2.7V to
5.5V
-40 to
+85
8 Ld MSOP
Tape and Reel
ISL1208IU8Z
(See Note)
ANW
YWW
2.7V to
5.5V
-40 to
+85
8 Ld MSOP
(Pb-free)
ISL1208IU8Z-TK
(See Note)
ANW
YWW
2.7V to
5.5V
-40 to
+85
8 Ld MSOP
Tape and Reel
(Pb-free)
ISL1208IB8
1208
YWW
2.7V to
5.5V
-40 to
+85
8 Ld SOIC
ISL1208IB8-TK
1208
YWW
2.7V to
5.5V
-40 to
+85
8 Ld SOIC
Tape and Reel
ISL1208IB8Z
(See Note)
1208
YWWZ
2.7V to
5.5V
-40 to
+85
8 Ld SOIC
(Pb-free)
• Set Top Box/Television
ISL1208IB8Z-TK
(See Note)
1208
YWWZ
2.7V to
5.5V
-40 to
+85
8 Ld SOIC
Tape and Reel
(Pb-free)
• Network Routers, Hubs, Switches, Bridges
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
* Contact Factory for availability.
• 400nA Battery Supply Current
• Same Pin Out as ST M41Txx and Maxim DS13xx Devices
• Small Package Options
- 8 Ld MSOP and SOIC Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
Pinout
• Home Appliances
ISL1208
(8-PIN MSOP, SOIC)
TOP VIEW
• Computer Products
• Other Industrial/Medical/Automotive
X1
1
8
VDD
X2
2
7
IRQ/FOUT
VBAT
3
6
SCL
GND
4
5
SDA
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL1208
Block Diagram
SDA
BUFFER
SDA
I2C
INTERFACE
SCL
BUFFER
SCL
Seconds
RTC
CONTROL
LOGIC
Minutes
Hours
Day of Week
X1
CRYSTAL
OSCILLATOR
X2
RTC
DIVIDER
Date
Month
VDD
POR
FREQUENCY
OUT
Year
ALARM
VTRIP
CONTROL
REGISTERS
USER
SRAM
SWITCH
IRQ/
FOUT
INTERNAL
SUPPLY
VBAT
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal. X1 can also be driven directly from a 32.768kHz source.
2
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
3
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the
VDD supply fails. This pin should be tied to ground if not used.
4
GND
Ground.
5
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
6
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device.
7
IRQ/FOUT
8
VDD
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The
function is set via the configuration register.
Power supply.
2
FN8085.3
July 29, 2005
ISL1208
Absolute Maximum Ratings
Voltage on VDD, VBAT, SCL, SDA, and IRQ pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Voltage on X1 and X2 pins
(respect to ground) . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode)
-0.5V to VBAT + 0.5 (VBAT Mode)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
TYP
(Note 4)
MIN
MAX
UNITS
VDD
Main Power Supply
2.7
5.5
V
VBAT
Battery Supply Voltage
1.8
5.5
V
IDD1
Supply Current
IDD2
Supply Current With I2C Active
IDD3
IBAT
VDD = 5V
2
6
µA
VDD = 3V
1.2
4
µA
VDD = 5V
40
120
µA
1, 2
Supply Current (Low Power Mode)
VDD = 5V, LPMODE = 1
1.4
5
µA
1
Battery Supply Current
VBAT = 3V
400
950
nA
1
ILI
Input Leakage Current on SCL
100
nA
ILO
I/O Leakage Current on SDA
100
nA
VTRIP
NOTES
1, 2
VBAT Mode Threshold
1.6
2.2
2.6
V
VTRIPHYS
VTRIP Hysteresis
10
30
75
mV
VBATHYS
VBAT Hysteresis
15
50
100
mV
VDD = 5V
IOL = 3mA
0.4
V
VDD = 2.7V
IOL = 1mA
0.4
V
MAX
UNITS
NOTES
10
V/ms
3
IRQ/FOUT
VOL
Output Low Voltage
Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
VDD SR-
PARAMETER
CONDITIONS
TYP
(Note 4)
MIN
VDD Negative Slewrate
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
NOTES
SERIAL INTERFACE SPECS
VIL
SDA and SCL input buffer LOW
voltage
-0.3
0.3 x
VDD
V
VIH
SDA and SCL input buffer HIGH
voltage
0.7 x
VDD
VDD +
0.3
V
SDA and SCL input buffer hysteresis
0.05 x
VDD
Hysteresis
VOL
SDA output buffer LOW voltage,
sinking 3mA
3
0
V
0.4
V
FN8085.3
July 29, 2005
ISL1208
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
Cpin
SDA and SCL pin capacitance
fSCL
SCL frequency
TEST CONDITIONS
MIN
TA = 25°C, f = 1MHz, VDD = 5V,
VIN = 0V, VOUT = 0V
TYP
(Note 4)
MAX
UNITS
10
pF
400
kHz
tIN
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec
is suppressed.
50
ns
tAA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
900
ns
tBUF
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
Clock LOW time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH time
Measured at the 70% of VDD crossing.
600
ns
tSU:STA
START condition setup time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA
START condition hold time
From SDA falling edge crossing 30% of
VDD to SCL falling edge crossing 70%
of VDD.
600
ns
tSU:DAT
Input data setup time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
100
ns
tHD:DAT
Input data hold time
From SCL falling edge crossing 30% of
VDD to SDA entering the 30% to 70%
of VDD window.
0
tSU:STO
STOP condition setup time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
600
ns
tHD:STO
STOP condition hold time
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
Output data hold time
From SCL falling edge crossing 30% of
VDD, until SDA enters the 30% to 70%
of VDD window.
0
ns
tR
SDA and SCL rise time
From 30% to 70% of VDD
20 +
0.1 x Cb
300
ns
tF
SDA and SCL fall time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
Cb
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL bus pull-up resistor offchip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
tDH
900
NOTES
ns
kΩ
NOTES:
1. IRQ & FOUT Inactive.
2. LPMODE = 0 (default).
3. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
4. Typical values are for T = 25°C and 3.3V supply voltage.
4
FN8085.3
July 29, 2005
ISL1208
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
5
FN8085.3
July 29, 2005
ISL1208
Typical Performance Curves
Temperature is 25°C unless otherwise specified
1E-6
1E-6
900E-9
800E-9
800E-9
600E-9
600E-9
IBAT(A)
IBAT (A)
700E-9
500E-9
400E-9
400E-9
300E-9
200E-9
200E-9
100E-9
000E+0
1.5
2.0
2.5
3.0 3.5 4.0
VBAT (V)
4.5
5.0
000E+0
5.5
FIGURE 1. IBAT vs VBAT
-20
0
20
40
TEMPERATURE (°C)
60
80
FIGURE 2. IBAT vs TEMPERATURE AT VBAT = 3V
2.4E-6
2.4E-06
2.2E-6
2.2E-06
2.0E-6
VCC = 5V
2.0E-06
1.8E-6
1.8E-06
1.6E-06
LPMODE = 0
1.6E-6
IDD1 (A)
IDD1 (A)
-40
1.4E-6
LPMODE = 1
1.2E-6
VCC = 3.3V
1.0E-6
1.4E-06
800.0E-9
1.2E-06
600.0E-9
40
60
80
400.0E-9
2.5
3.0
3.5
4.0
TEMPERATURE (°C)
FIGURE 5. IDD1 vs FOUT AT VDD = 3.3V
6
5.5
4096
FOUT (Hz)
32768
4096
32768
64
1024
16
32
4
8
1
2
1/2
1/4
1/8
1/16
1.3E-6
64
1.4E-6
1024
1.5E-6
1
1.6E-6
1/2
1.7E-6
1/4
IDD1 (A)
1.8E-6
1/32
IDD1 (A)
1.9E-6
3.0E-6
2.9E-6
2.8E-6
2.7E-6
2.6E-6
2.5E-6
2.4E-6
2.3E-6
2.2E-6
2.1E-6
2.0E-6
1.9E-6
1.8E-6
1/8
2.0E-6
1/16
2.1E-6
FOUT (Hz)
5.0
FIGURE 4. IDD1 vs VCC WITH LPMODE ON & OFF
1/32
FIGURE 3. IDD1 vs TEMPERATURE
1.2E-6
4.5
VCC (V)
16
20
32
0
4
-20
8
-40
2
1.0E-06
FIGURE 6. IDD1 vs FOUT AT VDD = 5V
FN8085.3
July 29, 2005
ISL1208
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V
5.0V
X1
1533Ω
SDA
AND
IRQ/FOUT
FOR VOL= 0.4V
X2
AND IOL = 3mA
100pF
FIGURE 8. RECOMMENDED CRYSTAL CONNECTION
VBAT
FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH VDD = 5.0V
General Description
The ISL1208 device is a low power real time clock with
timing and crystal compensation, clock/calendar, power fail
indicator, periodic or polled alarm, intelligent battery backup
switching, and battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL1208's powerful alarm can be set to any
clock/calendar value for a match. For example, every
minute, every Tuesday or at 5:23 AM on March 21. The
alarm status is available by checking the Status Register, or
the device can be configured to provide a hardware interrupt
via the IRQ pin. There is a repeat mode for the alarm
allowing a periodic interrupt every minute, every hour, every
day, etc.
The device also offers a backup power input pin. This VBAT
pin allows the device to be backed up by battery or
SuperCap with automatic switchover from VDD to VBAT. The
entire ISL1208 device is fully operational from 2.0V to 5.5V
and the clock/calendar portion of the device remains fully
operational down to 1.8V (Standby Mode).
Pin Description
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the ISL1208 to supply a timebase for the real
time clock. Internal compensation circuitry provides high
accuracy over the operating temperature range from
-40°C to +85°C. This oscillator compensation network can
be used to calibrate the crystal timing accuracy over
temperature either during manufacturing or with an external
temperature sensor and microcontroller for active
compensation. The device can also be driven directly from a
32.768kHz source at pin X1.
7
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event that the VDD
supply fails. This pin can be connected to a battery, a Super
Cap or tied to ground if not used.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/FOUT mode is selected via
the frequency out control bits of the control/status register.
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is
an open drain active low output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
VBAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I2C interface speeds. It is disabled
when the backup power supply on the VBAT pin is activated.
VDD, GND
Chip power supply and ground pins. The device will operate
with a power supply from 2.0V to 5.5VDC. A 0.1µF capacitor
is recommended on the VDD pin to ground.
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
FN8085.3
July 29, 2005
ISL1208
the ISL1208 for up to 10 years. Another option is to use a
Super Cap for applications where VDD is interrupted for up
to a month. See the Applications Section for more
information.
Normal Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the
following conditions must be met:
Condition 2:
VDD < VTRIP
where VTRIP ≈ 2.2V
Low Power Mode
Battery Backup Mode (VBAT) to Normal Mode
(VDD)
The ISL1208 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS ≈ 50mV
Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS ≈ 30mV
These power control situations are illustrated in Figures 9
and 10.
BATTERY BACKUP
MODE
VTRIP
2.2V
VBAT
1.8V
VBAT + VBATHYS
VBAT - VBATHYS
FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP
BATTERY BACKUP
MODE
VDD
Power Failure Detection
The ISL1208 provides a Real Time Clock Failure Bit (RTCF)
to detect total power failure. It allows users to determine if
the device has powered up after having lost all power to the
device (both VDD and VBAT).
Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS ≈ 50mV
VDD
The I2C bus is deactivated in battery backup mode to provide
lower power. Aside from this, all RTC functions are
operational during battery backup mode. Except for SCL and
SDA, all the inputs and outputs of the ISL1208 are active
during battery backup mode unless disabled via the control
register. The User SRAM is operational in battery backup
mode down to 2V.
3.0V
VTRIP
2.2V
VTRIP + VTRIPHYS
FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP
8
Low Power Mode is useful in systems where VDD is normally
higher than VBAT at all times. The device will switch from
VDD to VBAT when VDD drops below VBAT, with about 50mV
of hysteresis to prevent any switchback of VDD after
switchover. In a system with a VDD = 5V and backup lithium
battery of VBAT = 3V, Low Power Mode can be used.
However, it is not recommended to use Low Power Mode in
a system with VDD = 3.3V ±10%, VBAT ≥ 3.0V, and when
there is a finite I-R voltage drop in the VDD line.
InterSeal™ Battery Saver
The ISL1208 has the InterSeal™ Battery Saver which
prevents initial battery current drain before it is first used. For
example, battery-backed RTCs are commonly packaged on
a board with a battery connected. In order to preserve
battery life, the ISL1208 will not draw any power from the
battery source until after the device is first powered up from
the VDD source. Thereafter, the device will switchover to
battery backup mode whenever VDD power is lost.
Real Time Clock Operation
VBAT
VTRIP
The normal power switching of the ISL1208 is designed to
switch into battery backup mode only if the VDD power is
lost. This will ensure that the device can accept a wide range
of backup voltages from many types of sources while reliably
switching into backup mode. Another mode, called Low
Power Mode, is available to allow direct switching from VDD
to VBAT without requiring VDD to drop below VTRIP. Since
the additional monitoring of VDD vs VTRIP is no longer
needed, that circuitry is shut down and less power is used
while operating from VDD. Power savings are typically
600nA at VDD = 5V. Low Power Mode is activated via the
LPMODE bit in the control and status registers.
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the ISL1208
powers up after the loss of both VDD and VBAT, the clock will
FN8085.3
July 29, 2005
ISL1208
not begin incrementing until at least one byte is written to the
clock register.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer. The ISL1208 provides on-chip
crystal compensation networks to adjust load capacitance to
tune oscillator frequency from -94ppm to +140ppm. For
more detailed information see the Application Section.
Single Event and Interrupt
The alarm mode is enabled via the ALME bit. Choosing
single event or interrupt alarm mode is selected via the IM
bit. Note that when the frequency output function is enabled,
the alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ pin will be pulled low and the
alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ pin will be pulled low for 250ms and the alarm
status bit (ALM) will be set to “1”.
NOTE: The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit).
The alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see the Alarm Registers Description.
I2C Serial Interface
The ISL1208 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bidirectional data
signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL1208 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated
compensation of approximately -34ppm to +80ppm. (See
ATR description.)
2. A digital trimming register (DTR) that can be used to
adjust the timing counter by ±60ppm. (See DTR
description.)
Also provided is the ability to adjust the crystal capacitance
when the ISL1208 switches from VDD to battery backup
mode. (See Battery Mode ATR Selection for more details.)
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:13h]. The defined addresses and default values are
described in the Table 1. Address 09h is not used. Reads or
writes to 09h will not affect operation of the device but should
be avoided.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 4 sections. These are:
Frequency Output Mode
1. Real Time Clock (7 bytes): Address 00h to 06h.
The ISL1208 has the option to provide a frequency output
signal using the IRQ/FOUT pin. The frequency output mode
is set by using the FO bits to select 15 possible output
frequency values from 0 to 32kHz. The frequency output can
be enabled/disabled during battery backup mode using the
FOBATB bit.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
4. User SRAM (2 bytes): Address 12h to 13h.
There are no addresses above 13h.
General Purpose User SRAM
The ISL1208 provides 2 bytes of user SRAM. The SRAM will
continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
9
FN8085.3
July 29, 2005
ISL1208
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register.
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 4 of address 07h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
TABLE 1. REGISTER MEMORY MAP
BIT
REG
ADDR. SECTION NAME
7
6
5
4
3
2
1
0
RANGE
DEFAULT
00h
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0-59
00h
01h
MN
0
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0-59
00h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10
0-23
00h
DT
0
0
DT21
DT20
DT13
DT12
DT11
DT10
1-31
00h
04h
MO
0
0
0
MO20
MO13
MO12
MO11
MO10
1-12
00h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0-99
00h
06h
DW
0
0
0
0
0
DW2
DW1
DW0
0-6
00h
07h
SR
ARST
WRTC
Reserved
ALM
BAT
RTCF
N/A
01h
INT
IM
FOBATB
FO3
FO2
FO1
FO0
N/A
00h
N/A
00h
03h
08h
09h
0Ah
RTC
Control
and
Status
XTOSCB Reserved
ALME
LPMODE
Reserved
ATR
BMATR1
0Bh
DTR
Reserved
0Ch
SCA
ESCA
ASC22
ASC21
ASC20
0Dh
MNA
EMNA
AMN22
AMN21
HRA
EHRA
0
DTA
EDTA
10h
MOA
11h
0Eh
0Fh
12h
13h
Alarm
User
ATR2
ATR1
ATR0
N/A
00h
DTR2
DTR1
DTR0
N/A
00h
ASC13
ASC12
ASC11
ASC10
00-59
00h
AMN20
AMN13
AMN12
AMN11
AMN10
00-59
00h
AHR21
AHR20
AHR13
AHR12
AHR11
AHR10
0-23
00h
0
ADT21
ADT20
ADT13
ADT12
ADT11
ADT10
1-31
00h
EMOA
0
0
AMO20
AMO13
AMO12
AMO11
AMO10
1-12
00h
DWA
EDWA
0
0
0
0
ADW12
ADW11
ADW10
0-6
00h
USR1
USR17
USR16
USR15
USR14
USR13
USR12
USR11
USR10
N/A
00h
USR2
USR27
USR26
USR25
USR24
USR23
USR22
USR21
USR20
N/A
00h
10
BMATR0
ATR5
ATR4
ATR3
FN8085.3
July 29, 2005
ISL1208
Real Time Clock Registers
REAL TIME CLOCK FAIL BIT (RTCF)
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 0 to 59,
HR (Hour) can either be a 12-hour or 24-hour mode, DT
(Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99,
and DW (Day of the Week) is 0 to 6.
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL1208 internally) when the
device powers up after having lost all power to the device.
The bit is set regardless of whether VDD or VBAT is applied
first. The loss of only one of the supplies does not set the
RTCF bit to “1”. The first valid write to the RTC section after
a complete power failure resets the RTCF bit to “0” (writing
one byte is sufficient).
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
BATTERY BIT (BAT)
24 HOUR TIME
These bits announce if the alarm matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit can be manually reset to “0” by the user or automatically
reset by enabling the auto-reset bit (see ARST bit). A write to
this bit in the SR can only set it to “0”, not “1”.
If the MIL bit of the HR register is “1”, the RTC uses a 24hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The ISL1208
does not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR)
The Status Register is located in the memory map at
address 07h. This is a volatile register that provides either
control or status of RTC failure, battery mode, alarm trigger,
write protection of clock counter, crystal oscillator enable and
auto reset of status bits.
TABLE 2. STATUS REGISTER (SR)
ADDR
07h
Default
7
6
5
4
3
2
1
0
ARST XTOSCB reserved WRTC reserved ALM BAT RTCF
0
0
0
0
0
0
0
0
This bit is set to a “1” when the device enters battery backup
mode. This bit can be reset either manually by the user or
automatically reset by enabling the auto-reset bit (see ARST
bit). A write to this bit in the SR can only set it to “0”, not “1”.
ALARM BIT (ALM)
NOTE: An alarm bit that is set by an alarm occurring during an SR
read operation will remain set after the read operation is complete.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB)
This bit enables/disables the internal crystal oscillator. When
the XTOSCB is set to “1”, the oscillator is disabled, and the
X1 pin allows for an external 32kHz signal to drive the RTC.
The XTOSCB bit is set to “0” on powerup.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the
BAT and ALM bits.
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
11
7
08h
IM
Default
0
6
5
4
3
2
1
0
ALME LPMODE FOBATB FO3 FO2 FO1 FO0
0
0
0
0
0
0
0
FN8085.3
July 29, 2005
ISL1208
FREQUENCY OUT CONTROL BITS (FO )
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/FOUT pin. See
Table 4 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/FOUT pin.
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
TABLE 4. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT
UNITS
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
FO3
FO2
FO1
FO0
0
Hz
0
0
0
0
32768
Hz
0
0
0
1
4096
Hz
0
0
1
0
1024
Hz
0
0
1
1
64
Hz
0
1
0
0
32
Hz
0
1
0
1
16
Hz
0
1
1
0
8
Hz
0
1
1
1
4
Hz
1
0
0
0
2
Hz
1
0
0
1
1
Hz
1
0
1
0
1/2
Hz
1
0
1
1
1/4
Hz
1
1
0
0
1/8
Hz
1
1
0
1
1/16
Hz
1
1
1
0
1/32
Hz
1
1
1
1
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the FOUT/IRQ pin during battery
backup mode (i.e. VBAT power source active). When the
FOBATB is set to “1” the FOUT/IRQ pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the FOUT/IRQ pin is enabled
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD < VBAT - VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V.
(See Typical Performance Curves: IDD vs VCC with
LPMODE ON & OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/FOUT pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/FOUT pin will be
tied low until the ALM status bit is cleared to “0”.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR)
X1
CX1
Crystal
Oscillator
X2
CX2
FIGURE 11. DIAGRAM OF ATR
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
12
FN8085.3
July 29, 2005
ISL1208
and X2 pins to ground (see Figure 11). The value of CX1 and
CX2 is given by the following formula:
C
X
= ( 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 )pF
The effective series load capacitance is the combination of
CX1 and CX2:
1
C
= ----------------------------------LOAD
1
1
---------- + -----------
C
X1 C X2
C
LOAD
16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9
= ----------------------------------------------------------------------------------------------------------------------------- pF
2
For example, CLOAD(ATR=00000) = 12.5pF,
CLOAD(ATR=100000) = 4.5pF, and CLOAD(ATR=011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR )
Since the accuracy of the crystal oscillator is dependent on
the VDD/VBAT operation, the ISL1208 provides the capability
to adjust the capacitance between VDD and VBAT when the
device switches between power sources.
DELTA
CAPACITANCE
(CBAT TO CVDD)
BMATR1
BMATR0
0
0
0pF
0
1
-0.5pF (≈ +2ppm)
1
0
+0.5pF (≈ -2ppm)
1
1
+1pF (≈ -4ppm)
DIGITAL TRIMMING REGISTER (DTR )
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
• DTR2 is a sign bit. DTR2 = “0” means frequency
compensation is >0. DTR2 = “1” means frequency
compensation is
工商网监
湘ICP备2023018690号
