ISL1208IU8Z

DATASHEET ISL1208 FN8085 Rev 9.01 Jul 15, 2022 I2C Real Time Clock/Calendar, Low Power RTC with Battery Backed SRAM Features The ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user SRAM. • Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds - Day of the Week, Day, Month, and Year The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. • 15 Selectable Frequency Outputs • Single Alarm - Settable to the Second, Minute, Hour, Day of the Week, Day, or Month - Single Event or Pulse Interrupt Mode • Automatic Backup to Battery or Super Capacitor Applications • Power Failure Detection • Utility Meters • On-Chip Oscillator Compensation • HVAC Equipment • 2 Bytes Battery-Backed User SRAM • Audio/Video Components • I2C Interface - 400kHz Data Transfer Rate • Set-Top Box/Television • Modems • 400nA Battery Supply Current • Network Routers, Hubs, Switches, Bridges • Cellular Infrastructure Equipment • Same Pin Out as ST M41Txx and Maxim DS13xx Devices • Fixed Broadband Wireless Equipment • Small Package Options - 8 Ld MSOP and SOIC Packages - 8 Ld TDFN Package • Pagers/PDA • POS Equipment • Pb-Free Available (RoHS Compliant) • Test Meters/Fixtures • Office Automation (Copiers, Fax) • Home Appliances • Computer Products • Other Industrial/Medical/Automotive Vs (2.7V-5.5V) VBat (1.8V-5.5V) 0.1µ 4.7k 8 7 6 5 4.7k 32.768 kHz 1 X1 VDD 2 X2 IRQ/FOUT 3 VBAT SCL 4 GND SDA 0.1µ 4.7k 0.1µ INT SCL SDA VDD MCU GND ISL1208 FIGURE 1. TYPICAL APPLICATION FN8085 Rev 9.01 Jul 15, 2022 Page 1 of 24 © 2004-2022 Renesas Electronics ISL1208 SDA BUFFER SDA SCL BUFFER SCL SECONDS I2C INTERFACE RTC CONTROL LOGIC MINUTES HOURS DAY OF WEEK X1 CRYSTAL OSCILLATOR X2 RTC DIVIDER DATE MONTH VDD POR FREQUENCY OUT YEAR ALARM CONTROL REGISTERS VTRIP USER SRAM SWITCH IRQ/ FOUT INTERNAL SUPPLY VBAT FIGURE 2. Block Diagram Ordering Information . PART NUMBER ISL1208IU8Z PART MARKING ANW VDD RANGE (V) PACKAGE DESCRIPTION (RoHS Compliant) PKG. DWG. # CARRIER TYPE (Note 1) TEMP. RANGE 2.7 to 5.5 8 Ld MSOP M8.118 Tube -40 to +85°C ISL1208IU8Z-TK Reel, 2.5k ISL1208IU8Z-T7A ISL1208IB8Z ISL1208IB8Z-TK Reel, 250 1208 ZI 8 Ld SOIC M8.15E Reel, 1k ISL1208IB8Z-T7A ISL1208IRT8Z Tube Reel, 250 08TZ ISL1208IRT8Z-TK 8 Ld TDFN L8.3x3A Tube Reel, 1k NOTES: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL1208 device page. For more information about MSL, see TB363 FN8085 Rev 9.01 Jul 15, 2022 Page 2 of 24 ISL1208 Pinouts ISL1208 (8 LD TDFN) TOP VIEW ISL1208 (8 LD MSOP, SOIC) TOP VIEW X1 1 8 VDD X2 2 7 IRQ/FOUT VBAT 3 6 SCL 4 5 SDA GND X1 1 8 VDD X2 2 7 IRQ/FOUT VBAT 3 6 SCL GND 4 5 SDA Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. 2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 3 VBAT This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. 4 GND Ground 5 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. 6 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 7 8 IRQ/FOUT Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. VDD FN8085 Rev 9.01 Jul 15, 2022 Power supply Page 3 of 24 ISL1208 Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT, SCL, SDA, and IRQ Pins (Note 8) (respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Voltage on X1 and X2 Pins (respect to GND) . . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode) -0.5V to VBAT + 0.5 (VBAT Mode) Latchup (Note 9) ................Class II, Level B @ +85°C Thermal Resistance JA (°C/W) JC (°C/W) 108 55 SOIC Package (Notes 5, 7) . . . . . . . . . MSOP Package (Notes 5, 7) . . . . . . . . 145 55 TDFN Package (Notes 4, 6). . . . . . . . . 45 3.5 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board. See TB379. 6. For JC, the case temperature location is the center of the exposed metal pad on the package underside. 7. For JC, the case temperature location is the package top center 8. The VDD and SDA pins should not be subjected to negative voltage while the VBAT pin is biased, otherwise latchup can result. See the Applications section. 9. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a negative pulse limited to -0.5V. DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL PARAMETER CONDITIONS NOTES MIN (Note 14) TYP (Note 13) MAX (Note 14) UNITS VDD Main Power Supply 2.7 5.5 V VBAT Battery Supply Voltage 1.8 5.5 V IDD1 Supply Current 2 6 µA 1.2 4 µA IDD2 Supply Current With I2C Active VDD = 5V 10, 11 40 120 µA IDD3 Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 10 1.4 5 µA IBAT Battery Supply Current VBAT = 3V 10 400 950 nA VDD = 5V 10, 11 VDD = 3V ILI Input Leakage Current on SCL 100 nA ILO I/O Leakage Current on SDA 100 nA VTRIP VBAT Mode Threshold 1.6 2.2 2.6 V VTRIPHYS VTRIP Hysteresis 10 30 75 mV VBATHYS VBAT Hysteresis 15 50 100 mV VDD = 5V IOL = 3mA 0.4 V VDD = 2.7V IOL = 1mA 0.4 V MAX (Note 14) UNITS 10 V/ms IRQ/FOUT VOL Output Low Voltage Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL VDD SR- PARAMETER VDD Negative Slewrate FN8085 Rev 9.01 Jul 15, 2022 CONDITIONS NOTES 12 MIN (Note 14) TYP (Note 13) Page 4 of 24 ISL1208 Serial Interface Specifications SYMBOL Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS NOTES MIN (Note 14) TYP (Note 13) MAX (Note 14) UNITS SERIAL INTERFACE SPECS VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V SDA and SCL Input Buffer Hysteresis 0.05 x VDD Hysteresis VOL SDA Output Buffer LOW Voltage, Sinking 3mA CPIN SDA and SCL Pin Capacitance fSCL SCL Frequency 0 TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V 15, 16 V 0.4 V 10 pF 400 kHz tIN Pulse width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must Be Free Before SDA crossing 70% of VDD during a STOP the Start of a New Transmission condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. 20 tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 600 ns tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. 600 ns Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. 0 ns tR SDA and SCL Rise Time From 30% to 70% of VDD 15, 16 20 + 0.1 x Cb 300 ns tF SDA and SCL Fall Time From 70% to 30% of VDD 15, 16 20 + 0.1 x Cb 300 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 15, 16 10 400 pF tDH FN8085 Rev 9.01 Jul 15, 2022 900 ns Page 5 of 24 ISL1208 Serial Interface Specifications SYMBOL Rpu Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS NOTES MIN (Note 14) Maximum is determined by tR and tF. For Cb = 400pF, max is about 2k to~2.5k. For Cb = 40pF, max is about 15kto ~20k 15, 16 1 PARAMETER SDA and SCL Bus Pull-Up Resistor Off-Chip TYP (Note 13) MAX (Note 14) UNITS k NOTES: 10. IRQ and FOUT Inactive. 11. LPMODE = 0 (default). 12. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 13. Typical values are for T = +25°C and 3.3V supply voltage. 14. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 15. Parameter is not 100% tested. 16. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. SDA vs SCL Timing tF SCL tHIGH tLOW tR tSU:DAT tSU:STA SDA (INPUT TIMING) tHD:DAT tHD:STA tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance FN8085 Rev 9.01 Jul 15, 2022 Page 6 of 24 ISL1208 Typical Performance Curves Temperature is +25°C unless otherwise specified 1E-6 1E-6 900E-9 800E-9 800E-9 700E-9 IBAT (A) IBAT (A) 600E-9 500E-9 400E-9 600E-9 400E-9 300E-9 200E-9 200E-9 100E-9 000E+0 1.5 2.0 2.5 3.0 3.5 4.0 VBAT (V) 4.5 5.0 000E+0 5.5 -20 0 20 40 TEMPERATURE (°C) 60 80 FIGURE 4. IBAT vs TEMPERATURE AT VBAT = 3V FIGURE 3. IBAT vs VBAT 2.4E-6 2.4E-06 2.2E-6 2.2E-06 2.0E-6 VCC = 5V 2.0E-06 1.8E-6 IDD1 (A) IDD1 (A) -40 1.8E-06 1.6E-06 VCC = 3.3V LPMODE = 0 1.6E-6 1.4E-6 LPMODE = 1 1.2E-6 1.0E-6 1.4E-06 800.0E-9 1.2E-06 60 400.0E-9 2.5 80 3.0 3.5 4.0 TEMPERATURE (°C) FIGURE 5. IDD1 vs TEMPERATURE FIGURE 7. IDD1 vs FOUT AT VDD = 3.3V FN8085 Rev 9.01 Jul 15, 2022 5.5 4096 FOUT (Hz) 32768 64 4096 32768 64 1024 16 32 4 8 1 2 1/2 1/4 1/8 1/16 1/32 1.3E-6 1 1.4E-6 1/2 1.5E-6 1/4 1.6E-6 1/8 1.7E-6 1/16 1.8E-6 IDD1 (A) IDD1 (A) 1.9E-6 3.0E-6 2.9E-6 2.8E-6 2.7E-6 2.6E-6 2.5E-6 2.4E-6 2.3E-6 2.2E-6 2.1E-6 2.0E-6 1.9E-6 1.8E-6 1/32 2.0E-6 FOUT (Hz) 5.0 FIGURE 6. IDD1 vs VCC WITH LPMODE ON AND OFF 2.1E-6 1.2E-6 4.5 VCC (V) 1024 40 16 20 32 0 4 -20 8 -40 2 1.0E-06 600.0E-9 FIGURE 8. IDD1 vs FOUT AT VDD = 5V Page 7 of 24 ISL1208 EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V X1 1533 SDA AND IRQ/fOUT FOR VOL= 0.4V X2 AND IOL = 3mA 100pF FIGURE 10. RECOMMENDED CRYSTAL CONNECTION VBAT FIGURE 9. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V General Description The ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, and battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. The ISL1208's powerful alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or Super Capacitor with automatic switchover from VDD to VBAT. The entire ISL1208 device is fully operational from 2.0V to 5.5V and the clock/calendar portion of the device remains fully operational down to 1.8V (Standby Mode). Pin Description X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1208 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a 32.768kHz source at pin X1. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used. IRQ/fOUT (Interrupt Output/Frequency Output) This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. • Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. • Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain active low output. Serial Clock (SCL) The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. VDD, GND Chip power supply and ground pins. The device will operate with a power supply from 2.0V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. Functional Description Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1208 for up FN8085 Rev 9.01 Jul 15, 2022 Page 8 of 24 ISL1208 to 10 years. Another option is to use a Super Cap for applications where VDD is interrupted for up to a month. See the “Application Section” on page 18 for more information. Normal Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS  50mV Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL1208 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS  30mV These power control situations are illustrated in Figures 11 and 12. BATTERY BACKUP MODE VTRIP 2.2V VBAT 1.8V VBAT + VBATHYS VBAT - VBATHYS FIGURE 11. BATTERY SWITCHOVER WHEN VBAT < VTRIP BATTERY BACKUP MODE VDD 3.0V VTRIP 2.2V VTRIP + VTRIPHYS FIGURE 12. BATTERY SWITCHOVER WHEN VBAT > VTRIP The I2C bus is deactivated in battery backup mode to provide lower power. Aside from this, all RTC functions are operational FN8085 Rev 9.01 Jul 15, 2022 The ISL1208 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT). The normal power switching of the ISL1208 is designed to switch into battery backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Another mode, called Low Power Mode, is available to allow direct switching from VDD to VBAT without requiring VDD to drop below VTRIP. Since the additional monitoring of VDD vs VTRIP is no longer needed, that circuitry is shut down and less power is used while operating from VDD. Power savings are typically 600nA at VDD = 5V. Low Power Mode is activated via the LPMODE bit in the control and status registers. Low Power Mode is useful in systems where VDD is normally higher than VBAT at all times. The device will switch from VDD to VBAT when VDD drops below VBAT, with about 50mV of hysteresis to prevent any switchback of VDD after switchover. In a system with a VDD = 5V and backup lithium battery of VBAT = 3V, Low Power Mode can be used. However, it is not recommended to use Low Power Mode in a system with VDD = 3.3V ±10%, VBAT  3.0V, and when there is a finite I-R voltage drop in the VDD line. InterSeal™ Battery Saver The ISL1208 has the InterSeal™ Battery Saver which prevents initial battery current drain before it is first used. For example, battery-backed RTCs are commonly packaged on a board with a battery connected. In order to preserve battery life, the ISL1208 will not draw any power from the battery source until after the device is first powered up from the VDD source. Thereafter, the device will switchover to battery backup mode whenever VDD power is lost. Real Time Clock Operation VBAT VTRIP Power Failure Detection Low Power Mode Condition 2: VDD < VTRIP where VTRIP  2.2V VDD during battery backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL1208 are active during battery backup mode unless disabled via the control register. The User SRAM is operational in battery backup mode down to 2V. The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24-hour or AM/PM format. When the ISL1208 powers up after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock register. Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for Page 9 of 24 ISL1208 the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer. The ISL1208 provides on-chip crystal compensation networks to adjust load capacitance to tune oscillator frequency from -94ppm to +140ppm. For more detailed information. See “Application Section” on page 18. Single Event and Interrupt The alarm mode is enabled via the ALME bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, an IRQ pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to “1”. NOTE: The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery backup mode using the FOBATB bit. For more information on the alarm, See “Alarm Registers” on page 14. Frequency Output Mode The ISL1208 has the option to provide a frequency output signal using the IRQ/FOUT pin. The frequency output mode is set by using the FO bits to select 15 possible output frequency values from 0kHz to 32kHz. The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit. General Purpose User SRAM The ISL1208 provides 2 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode. FN8085 Rev 9.01 Jul 15, 2022 I2C Serial Interface The ISL1208 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bidirectional data signal (SDA) and a clock signal (SCL). Oscillator Compensation The ISL1208 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. The total possible compensation is typically -94ppm to +140ppm. Two compensation mechanisms that are available are as follows: 1. An analog trimming (ATR) register that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. The individual digital capacitor is selectable from a range of 9pF to 40.5pF (based upon 32.758kHz). This translates to a calculated compensation of approximately -34ppm to +80ppm. (See ATR description on page 18). 2. A digital trimming register (DTR) that can be used to adjust the timing counter by ±60ppm. (See DTR description on page 18). Also provided is the ability to adjust the crystal capacitance when the ISL1208 switches from VDD to battery backup mode. See “Battery Backup Mode (VBAT) to Normal Mode (VDD)” on page 9. Register Descriptions The battery-backed registers are accessible following a slave byte of “1101111x” and reads or writes to addresses [00h:13h]. The defined addresses and default values are described in Table 1. Address 09h is not used. Reads or writes to 09h will not affect operation of the device but should be avoided. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 4 sections. These are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (5 bytes): Address 07h to 0Bh. 3. Alarm (6 bytes): Address 0Ch to 11h. 4. User SRAM (2 bytes): Address 12h to 13h. There are no addresses above 13h. Page 10 of 24 ISL1208 instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 4 of address 07h) is set to “1”. A multi-byte read or write operation is limited to one section per operation. Access to another section requires a new operation. A read or write can begin at any address within the section. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers. TABLE 1. REGISTER MEMORY MAP REG ADDR. SECTION NAME BIT 7 6 5 4 3 2 1 0 RANGE DEFAULT 00h SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h 01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 00h 02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 00h 04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 00h 05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h 06h DW 0 0 0 0 0 DW2 DW1 DW0 0 to 6 00h 07h SR ARST WRTC Reserved ALM BAT RTCF N/A 01h INT IM FOBATB FO3 FO2 FO1 FO0 N/A 00h N/A 00h 03h 08h 09h 0Ah RTC Control and Status XTOSCB Reserved ALME LPMODE Reserved ATR BMATR1 0Bh DTR Reserved 0Ch SCA ESCA ASC22 ASC21 ASC20 0Dh MNA EMNA AMN22 AMN21 HRA EHRA 0 DTA EDTA 10h MOA 11h 0Eh 0Fh 12h 13h ATR2 ATR1 ATR0 N/A 00h DTR2 DTR1 DTR0 N/A 00h ASC13 ASC12 ASC11 ASC10 00 to 59 00h AMN20 AMN13 AMN12 AMN11 AMN10 00 to 59 00h AHR21 AHR20 AHR13 AHR12 AHR11 AHR10 0 to 23 00h 0 ADT21 ADT20 ADT13 ADT12 ADT11 ADT10 1 to 31 00h EMOA 0 0 AMO20 AMO13 AMO12 AMO11 AMO10 1 to 12 00h DWA EDWA 0 0 0 0 ADW12 ADW11 ADW10 0 to 6 00h USR1 USR17 USR16 USR15 USR14 USR13 USR12 USR11 USR10 N/A 00h USR2 USR27 USR26 USR25 USR24 USR23 USR22 USR21 USR20 N/A 00h Alarm User FN8085 Rev 9.01 Jul 15, 2022 BMATR0 ATR5 ATR4 ATR3 Page 11 of 24 ISL1208 Real Time Clock Registers REAL TIME CLOCK FAIL BIT (RTCF) Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as “0”. 24 HOUR TIME If the MIL bit of the HR register is “1”, the RTC uses a 24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a “1” representing PM. The clock defaults to 12-hour format time with HR21 = “0”. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL1208 does not correct for the leap year in the year 2100. Control and Status Registers Addresses [07h to 0Bh] The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers. Status Register (SR) The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure, battery mode, alarm trigger, write protection of clock counter, crystal oscillator enable and auto reset of status bits. TABLE 2. STATUS REGISTER (SR) ADDR 07h Default 7 6 5 4 3 2 1 0 ARST XTOSCB reserved WRTC reserved ALM BAT RTCF 0 0 0 0 0 0 0 0 This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL1208 internally) when the device powers up after having lost all power to the device (both VDD and VBAT go to 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). BATTERY BIT (BAT) This bit is set to a “1” when the device enters battery backup mode. This bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. ALARM BIT (ALM) These bits announce if the alarm matches the real time clock. If there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. NOTE: An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB) This bit enables/disables the internal crystal oscillator. When the XTOSCB is set to “1”, the oscillator is disabled, and the X1 pin allows for an external 32kHz signal to drive the RTC. The XTOSCB bit is set to “0” on power-up. AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the BAT and ALM status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to “0”, the user must manually reset the BAT and ALM bits. Interrupt Control Register (INT) TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR FN8085 Rev 9.01 Jul 15, 2022 7 08h IM Default 0 6 5 4 3 2 1 0 ALME LPMODE FOBATB FO3 FO2 FO1 FO0 0 0 0 0 0 0 0 Page 12 of 24 ISL1208 FREQUENCY OUT CONTROL BITS (FO ) ALARM ENABLE BIT (ALME) These bits enable/disable the frequency output function and select the output frequency at the IRQ/fOUT pin. See Table 4 for frequency selection. When the frequency mode is enabled, it will override the alarm mode at the IRQ/fOUT pin. This bit enables/disables the alarm function. When the ALME bit is set to “1”, the alarm function is enabled. When the ALME is cleared to “0”, the alarm function is disabled. The alarm function can operate in either a single event alarm or a periodic interrupt alarm (see IM bit). TABLE 4. FREQUENCY SELECTION OF fOUT PIN FREQUENCY, fOUT UNITS FO3 FO2 FO1 FO0 NOTE: When the frequency output mode is enabled, the alarm function is disabled. INTERRUPT/ALARM MODE BIT (IM) 0 Hz 0 0 0 0 32768 Hz 0 0 0 1 4096 Hz 0 0 1 0 1024 Hz 0 0 1 1 64 Hz 0 1 0 0 32 Hz 0 1 0 1 16 Hz 0 1 1 0 8 Hz 0 1 1 1 IM BIT 4 Hz 1 0 0 0 0 Single Time Event Set By Alarm 2 Hz 1 0 0 1 1 Repetitive/Recurring Time Event Set By Alarm 1 Hz 1 0 1 0 1/2 Hz 1 0 1 1 1/4 Hz 1 1 0 0 1/8 Hz 1 1 0 1 1/16 Hz 1 1 1 0 1/32 Hz 1 1 1 1 This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to “1”, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ/fOUT pin when the RTC is triggered by the alarm as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to “0”, the alarm will operate in standard mode, where the IRQ/fOUT pin will be tied low until the ALM status bit is cleared to “0”. INTERRUPT/ALARM FREQUENCY Analog Trimming Register ANALOG TRIMMING REGISTER (ATR) X1 CX1 CRYSTAL OSCILLATOR FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables the fOUT/IRQ pin during battery backup mode (i.e. VBAT power source active). When the FOBATB is set to “1” the fOUT/IRQ pin is disabled during battery backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to “0”, the fOUT/IRQ pin is enabled during battery backup mode. LOW POWER MODE BIT (LPMODE) This bit enables/disables low power mode. With LPMODE = “0”, the device will be in normal mode and the VBAT supply will be used when VDD < VBAT - VBATHYS and VDD < VTRIP. With LPMODE = “1”, the device will be in low power mode and the VBAT supply will be used when VDD < VBAT - VBATHYS. There is a supply current saving of about 600nA when using LPMODE = “1” with VDD = 5V. (See Typical Performance Curves on page 7: IDD vs VCC with LPMODE ON and OFF.) Avoid setting the device into low power mode with VDD < VBAT, the I2C communications will stop permanently. The VBAT input must be lowered below VDD to resume communications. FN8085 Rev 9.01 Jul 15, 2022 X2 CX2 FIGURE 13. DIAGRAM OF ATR Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34ppm to +80ppm to the nominal frequency compensation. The combination of analog and digital trimming can give up to -94ppm to +140ppm of total adjustment. The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 and X2 pins to ground (see Figure 11). The value of CX1 and CX2 are given in Equation 1: C X =  16  b5 + 8  b4 + 4  b3 + 2  b2 + 1  b1 + 0.5  b0 + 9 pF (EQ. 1) Page 13 of 24 ISL1208 The effective series load capacitance is the combination of CX1 and CX2 in Equation 2.: TABLE 5. DIGITAL TRIMMING REGISTERS DTR2 DTR1 DTR0 ESTIMATED FREQUENCY PPM 0 0 0 0 (default) 0 0 1 +20 0 1 0 +40 For example, CLOAD (ATR = 00000) = 12.5pF, CLOAD (ATR = 100000) = 4.5pF, and CLOAD (ATR = 011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. 0 1 1 +60 1 0 0 0 1 0 1 -20 1 1 0 -40 BATTERY MODE ATR SELECTION (BMATR ) 1 1 1 -60 1 C = ----------------------------------LOAD 1 1  ---------- + ----------- C  C X1 X2 C LOAD (EQ. 2) 16  b5 + 8  b4 + 4  b3 + 2  b2 + 1  b1 + 0.5  b0 + 9 =  ----------------------------------------------------------------------------------------------------------------------------- pF   2 Since the accuracy of the crystal oscillator is dependent on the VDD/VBAT operation, the ISL1208 provides the capability to adjust the capacitance between VDD and VBAT when the device switches between power sources. DELTA CAPACITANCE (CBAT TO CVDD) BMATR1 BMATR0 0 0 0pF 0 1 -0.5pF ( +2ppm) 1 0 +0.5pF ( -2ppm) 1 1 +1pF ( -4ppm) DIGITAL TRIMMING REGISTER (DTR ) The digital trimming bits DTR0, DTR1, and DTR2 adjust the average number of counts per second and average the ppm error to achieve better accuracy. • DTR2 is a sign bit. DTR2 = “0” means frequency compensation is >0. DTR2 = “1” means frequency compensation is