ISL22326WFV14Z

DATASHEET ISL22326 FN6176 Rev 3.00 September 9, 2015 Dual Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power, I2C™ Bus, 128 Taps The ISL22326 integrates two digitally controlled potentiometers (XDCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Two potentiometers in one package • 128 resistor taps • I2C serial interface - Three address pins, up to eight devices/bus • Non-volatile storage of wiper position • Wiper resistance: 70 typical @ VCC = 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V • 50kor 10k total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 14 Ld TSSOP or 16 Ld QFN package • Pb-free (RoHS compliant) Pinouts SHDN VCC A1 A0 ISL22326 (16 LD QFN) TOP VIEW ISL22326 (14 LD TSSOP) TOP VIEW 16 15 14 13 SHDN 2 13 A0 RH0 3 12 RH1 RL0 4 11 RL1 RH0 1 12 RH1 RW0 5 10 RW1 RL0 2 11 RL1 A2 6 9 GND 3 10 RW1 7 RW0 SCL 8 SDA NC 4 9 NC FN6176 Rev 3.00 September 9, 2015 5 6 7 8 GND A1 SDA 14 SCL 1 A2 VCC Page 1 of 17 ISL22326 Ordering Information PART NUMBER (Note) PART MARKING RESISTANCE OPTION TEMP. RANGE PACKAGE (k) (°C) (RoHS Compliant) PKG. DWG. # 22326 UFVZ ISL22326UFV14Z* (No longer available, recommended replacement: ISL22326WFR16Z-TK) 50 -40 to +125 14 Ld TSSOP M14.173 223 26UFZ ISL22326UFR16Z* (No longer available, recommended replacement: ISL22326WFR16Z-TK) 50 -40 to +125 16 Ld 4x4 QFN L16.4x4A ISL22326WFV14Z* 22326 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL22326WFR16Z* 223 26WFZ 10 -40 to +125 16 Ld 4x4 QFN L16.4x4A *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram VCC SCL SDA A0 A1 I2C INTERFACE POWER-UP INTERFACE, CONTROL AND STATUS LOGIC RH1 WR1 RW1 RL1 A2 RH0 SHDN NONVOLATILE REGISTERS WR0 RW0 RL0 GND FN6176 Rev 3.00 September 9, 2015 Page 2 of 17 ISL22326 Pin Descriptions TSSOP PIN NUMBER QFN PIN NUMBER PIN NAME 1 15 VCC 2 16 SHDN 3 1 RH0 “High” terminal of DCP0 4 2 RL0 “Low” terminal of DCP0 5 3 RW0 “Wiper” terminal of DCP0 6 5 A2 7 6 SCL Open drain I2C interface clock input 8 7 SDA Open drain Serial data I/O for the I2C interface 9 8 GND Device ground pin 10 10 RW1 “Wiper” terminal of DCP1 11 11 RL1 “Low” terminal of DCP1 12 12 RH1 “High” terminal of DCP1 13 13 A0 Device address input for the I2C interface 14 14 A1 Device address input for the I2C interface 4, 9 NC No connection EPAD* DESCRIPTION Power supply pin Shutdown active low input Device address input for the I2C interface Exposed Die Pad internally connected to GND *Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf FN6176 Rev 3.00 September 9, 2015 Page 3 of 17 ISL22326 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 3) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V Thermal Resistance (Typical, Notes 1, 2) JA (°C/W) JC (°C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . 100 N/A 16 Lead QFN . . . . . . . . . . . . . . . . . . . . 40 3.0 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions, unless otherwise stated. PARAMETER RH to RL Resistance TEST CONDITIONS MIN (Note 20) TYP (Note 4) MAX (Note 20) UNIT W option 10 k U option 50 k RH to RL Resistance Tolerance W and U option End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 17) U option ±80 ppm/°C (Note 17) Wiper Resistance VCC = 3.3V, wiper current = VCC/RTOTAL 70 VRH, VRL VRH and VRL Terminal Voltages VRH and VRL to GND CH/CL/CW (Note 19) Potentiometer Capacitance RW ILkgDCP Leakage on DCP Pins -20 +20 0 200  VCC V 10/10/25 Voltage at pin from GND to VCC 0.1 % pF 1 µA VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1) INL (Note 9) Integral Non-linearity Monotonic over all tap positions, W and U option -1 1 LSB (Note 5) DNL (Note 8) Differential Non-linearity Monotonic over all tap positions, W and U option -0.5 0.5 LSB (Note 5) ZSerror (Note 6) Zero-scale Error W option 0 1 5 U option 0 0.5 2 LSB (Note 5) FSerror (Note 7) Full-scale Error W option -5 -1 0 U option -2 -1 0 VMATCH (Note 10) DCP to DCP Matching Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals -2 TCV (Note 11) Ratiometric Temperature Coefficient DCP register set to 40 hex FN6176 Rev 3.00 September 9, 2015 2 ±4 LSB (Note 5) LSB (Note 5) ppm/°C Page 4 of 17 ISL22326 Analog Specifications SYMBOL Over recommended operating conditions, unless otherwise stated. (Continued) PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 4) MAX (Note 20) UNIT RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0 or 1) RINL (Note 15) Integral Non-linearity DCP register set between 10h and 7Fh; monotonic over all tap positions -1 1 MI (Note 12) RDNL (Note 14) Differential Non-linearity DCP register set between 10h and 7Fh; monotonic over all tap positions, W option -1 1 MI (Note 12) DCP register set between 10h and 7Fh; monotonic over all tap positions, U option -0.5 0.5 MI (Note 12) Roffset (Note 13) RMATCH (Note 16) Offset DCP to DCP Matching W option 0 1 5 MI (Note 12) U option 0 0.5 2 MI (Note 12) Any two DCPs at the same tap position with the same terminal voltages -2 2 MI (Note 12) Operating Specifications Over the recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 4) MAX (Note 20) UNIT ICC1 VCC Supply Current (Volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) 0.5 mA ICC2 VCC Supply Current (Non-volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) 3 mA VCC Current (Standby) VCC = +5.5V @ +85°C, I2C interface in standby state 5 µA VCC = +5.5V @ +125°C, I2C interface in standby state 7 µA VCC = +3.6V @ +85°C, I2C interface in standby state 3 µA VCC = +3.6V @ +125°C, I2C interface in standby state 5 µA VCC = +5.5V @ +85°C, I2C interface in standby state 3 µA VCC = +5.5V @ +125°C, I2C interface in standby state 5 µA VCC = +3.6V @ +85°C, I2C interface in standby state 2 µA VCC = +3.6V @ +125°C, I2C interface in standby state 4 µA 1 µA ISB ISD ILkgDig VCC Current (Shutdown) Leakage Current, at Pins A0, A1, A2, SHDN, SDA and SCL Voltage at pin from GND to VCC tWRT (Note 19) DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to wiper new position 1.5 µs tShdnRec (Note 19) DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs Vpor VccRamp Power-on Recall Voltage VCC Ramp Rate FN6176 Rev 3.00 September 9, 2015 Minimum VCC at which memory recall occurs -1 2.0 0.2 2.6 V V/ms Page 5 of 17 ISL22326 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL tD PARAMETER Power-up Delay TEST CONDITIONS MIN (Note 20) TYP (Note 4) VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state MAX (Note 20) UNIT 3 ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 18) 1,000,000 Temperature T < +55°C Cycles 50 Non-volatile Write Cycle Time Years 12 20 ms SERIAL INTERFACE SPECIFICATIONS VIL A2, A1, A0, SHDN, SDA, and SCL Input Buffer LOW Voltage -0.3 0.3*VCC V VIH A2, A1, A0, SHDN, SDA, and SCL Input Buffer HIGH Voltage 0.7*VCC VCC + 0.3 V SDA and SCL Input Buffer Hysteresis 0.05*VCC Hysteresis VOL Cpin (Note 19) fSCL SDA Output Buffer LOW Voltage, Sinking 4mA V 0 A2, A1, A0, SHDN, SDA, and SCL Pin Capacitance 0.4 10 SCL Frequency V pF 400 kHz tsp Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed 50 ns tAA SCL falling edge to SDA output data valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window 900 ns tBUF Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge; both crossing 70% of VCC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC to SDA rising edge crossing 30% of VCC 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge; both crossing 70% of VCC 1300 ns Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0 ns tR SDA and SCL Rise Time From 30% to 70% of VCC 20 + 0.1*Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VCC 20 + 0.1*Cb 250 ns tDH FN6176 Rev 3.00 September 9, 2015 Page 6 of 17 ISL22326 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 4) MAX (Note 20) UNIT 400 pF Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 Rpu SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k~2.5k For Cb = 40pF, max is about 15k~20k 1 k tSU:A A2, A1 and A0 Setup Time Before START condition 600 ns tHD:A A2, A1 and A0 Hold Time After STOP condition 600 ns NOTES: 4. Typical values are for TA = +25°C and 3.3V supply voltage 5. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)127 – VCC]/LSB. 8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 9. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127. 10. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. Max  V  RW  i  – Min  V  RW  i  10 6 11. TC V = ----------------------------------------------------------------------------------------------  --------------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper  Max  V  RW  i  + Min  V  RW  i    2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 14. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 127. 15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 127. 16. RMATCH = (RWi,x – RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 6  Max  Ri  – Min  Ri   10 17. TC R = ----------------------------------------------------------------  --------------------- for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is  Max  Ri  + Min  Ri    2 +165°C the minimum value of the resistance over the temperature range. 18. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. 19. Limits should be considered typical and are not production tested. 20. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN6176 Rev 3.00 September 9, 2015 Page 7 of 17 ISL22326 SDA vs SCL Timing tHIGH tF SCL tLOW tHD:STO tsp tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1, OR A2 [ Typical Performance Curves 100 1.2 80 70 1.0 60 0.8 ISB (µA) WIPER RESISITANCE () 1.4 VCC = 3.3V, T = +125°C 90 50 40 30 0.6 0.4 T = +25°C VCC = 3.3V, T = -40°C VCC = 3.3V, T = +20°C 20 0.2 10 0 T = +125°C 0 20 40 60 80 100 TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W) FN6176 Rev 3.00 September 9, 2015 120 0 2.7 3.2 3.7 4.2 4.7 5.2 VCC (V) FIGURE 2. STANDBY ICC vs VCC Page 8 of 17 ISL22326 Typical Performance Curves (Continued) 0.2 0.2 T = +25°C T = +25°C VCC = 2.7V 0.1 INL (LSB) DNL (LSB) 0.1 0 -0.1 VCC = 2.7V 0 -0.1 VCC = 5.5V -0.2 0 20 40 VCC = 5.5V 60 80 100 -0.2 120 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 0.0 1.3 10k 1.1 -0.3 ZSERROR (LSB) ZSERROR (LSB) 0.9 0.7 0.5 VCC = 2.7V VCC = 5.5V 0.3 0.1 -0.3 -40 -20 0 20 VCC = 5.5V 50k -0.6 -0.9 10k -1.2 50k -0.1 VCC = 2.7V 40 60 80 100 -1.5 -40 120 -20 0 TEMPERATURE (°C) 20 40 60 80 FIGURE 5. ZSERROR vs TEMPERATURE 0.4 T = +25°C T = +25°C VCC = 5.5V 0.2 VCC = 5.5V 0.2 0 INL (LSB) DNL (LSB) 120 FIGURE 6. FSERROR vs TEMPERATURE 0.4 -0.2 -0.4 0 -0.2 -0.4 VCC = 2.7V -0.6 16 100 TEMPERATURE (ºC) 36 56 VCC = 2.7V 76 96 116 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) FN6176 Rev 3.00 September 9, 2015 -0.6 16 36 56 76 96 TAP POSITION (DECIMAL) 116 FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) Page 9 of 17 ISL22326 Typical Performance Curves (Continued) 105 90 0.5 75 VCC = 2.7V TCv (ppm/°C) END TO END RTOTAL CHANGE (%) 1.0 50k 0.0 VCC = 5.5V 10k -0.5 60 45 50k 30 10k 15 -1.0 -40 -20 0 20 40 60 80 100 120 0 16 36 TEMPERATURE (ºC) 56 76 96 TAP POSITION (DECIMAL) FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm OUTPUT INPUT 300 TCr (ppm/°C) 250 200 150 50k 10k 100 WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5k 50 0 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz) SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FN6176 Rev 3.00 September 9, 2015 FIGURE 14. LARGE SIGNAL SETTLING TIME Page 10 of 17 ISL22326 Pin Descriptions Principles of Operation Potentiometers Pins RHI AND RLI (i = 0, 1) The high (RHi) and low (RLi) terminals of the ISL22326 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWI (i = 0,1) The ISL22326 is an integrated circuit incorporating two DCPs with their associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometers and memory. The resistor arrays are comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to the initial value. SHDN DCP Description The SHDN pin forces the resistor to end-to-end open circuit condition on RHi and shorts RWi to RLi. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. I2C interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. RH RW RL FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[6:0] = 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. While the ISL22326 is being powered up, all WRs are reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding nonvolatile Initial Value Registers (IVRs). SDA requires an external pull-up resistor, since it is an open drain input/output. The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h or 01h to access the WR of DCP0 or DCP1 respectively. SERIAL CLOCK (SCL) This is the serial clock input of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input. DEVICE ADDRESS (A2 - A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22326. A maximum of 8 ISL22326 devices may occupy the I2C serial bus. FN6176 Rev 3.00 September 9, 2015 Memory Description The ISL22326 contains seven non-volatile and three volatile 8bit registers. Memory map of ISL22326 is on Table 1. The two non-volatile registers (IVRi) at address 0 and 1, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, five non-volatile General Purpose registers from address 2 to address 6 are available. Page 11 of 17 ISL22326 and receive operations. Therefore, the ISL22326 operates as a slave device in all applications. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 8 — ACR 7 All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Reserved 6 5 4 3 2 General Purpose General Purpose General Purpose General Purpose General Purpose Not Available Not Available Not Available Not Available Not Available 1 0 IVR1 IVR0 WR1 WR0 Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22326, the SDA pin is in the input mode. The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit at access control register (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi. TABLE 2. ACCESS CONTROL REGISTER (ACR) VOL SHDN 0 WIP 0 0 0 0 If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note, value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically ANDed with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1. Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22326 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). The ISL22326 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22326 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. SHDN pin SHDN bit Mode A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (see Table 4). High 1 Normal operation TABLE 4. IDENTIFICATION BYTE FORMAT Low 1 Shutdown High 0 Shutdown Low 0 Shutdown TABLE 3. Logic values at pins A2, A1, and A0 respectively 1 (MSB) 0 1 0 A2 A1 A0 R/W (LSB) I2C Serial Interface The ISL22326 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit FN6176 Rev 3.00 September 9, 2015 Page 12 of 17 ISL22326 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 SIGNALS FROM THE SLAVE S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 18. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 SIGNALS FROM THE SLAVE S T A IDENTIFICATION R BYTE WITH T R/W = 1 S A T C O K P A C K 1 0 1 0 A2 A1 A0 1 0 0 0 0 A C K A C K A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 19. READ SEQUENCE FN6176 Rev 3.00 September 9, 2015 Page 13 of 17 ISL22326 Write Operation Read Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22326 responds with an ACK. At this time, the device enters its standby state (see Figure 18). The device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 08h, the internal pointer “rolls over” to address 00h. A Read operation consist of a three byte instruction followed by one or more Data Bytes (see Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL22326 responds with an ACK. Then the ISL22326 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and a STOP condition) following the last bit of the last Data Byte (see Figure 19). The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next nonvolatile write. Thus, non-volatile registers must be written individually. The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 08h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. FN6176 Rev 3.00 September 9, 2015 Page 14 of 17 ISL22326 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 9, 2015 FN6176.3 Updated Ordering Information table on page 2. Added Revision History and About Intersil sections. Updated Package Outline Drawing L16.4x4A to the latest revision. -Revision 2 to Revision 3 changes - Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing. Added Typical Recommended Land Pattern. Removed package option. Updated Package Outline Drawing M14.173 to the latest revision. -Revision 2 to Revision 3 changes - Updated drawing to remove table and added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2006-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6176 Rev 3.00 September 9, 2015 Page 15 of 17 ISL22326 Package Outline Drawing L16.4x4A 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 03/15 2.40 4.00 A 4X 1.50 B 6 13 PIN #1 INDEX AREA 16 6 PIN 1 INDEX AREA 12 1 4.00 12X 0.50 2.40 4 9 0.15 (4X) 5 8 TOP VIEW 0.10 M C A B 4 0.25 +0.05 -0.07 16x 0.40±0.01 BOTTOM VIEW SEE DETAIL "X" 0.90±0.10 0.10 C SEATING PLANE C 0.08 C SIDE VIEW (3.8 TYP) ( 2.40) (12x 0.50) C (16x 0.25) (16x 0.60) 0.20 REF 5 +0.03/-0.02 DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN6176 Rev 3.00 September 9, 2015 Page 16 of 17 ISL22326 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN FN6176 Rev 3.00 September 9, 2015 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. Page 17 of 17