ISL22329WFU10Z

DATASHEET OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT ISL22326 ISL22329 Dual Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power, I2C™ Bus, 128 Taps, Wiper Only The ISL22329 integrates two digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. Features • Two potentiometers in one package The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. The DCPs can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing. Pinout ISL22329 (10 LD MSOP) TOP VIEW A2 1 10 FN6330 Rev 2.00 September 4, 2009 • 128 resistor taps • I2C serial interface - Three address pins, up to eight devices/bus • Non-volatile storage of wiper position • Wiper resistance: 70 typical @ 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V • 50kor 10k total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 10 Ld MSOP • Pb-free (RoHS compliant) RW0 SCL 2 9 SHDN SDA 3 8 VCC GND 4 7 A1 RW1 5 6 A0 Ordering Information PART NUMBER (Note) PART MARKING RESISTANCE OPTION (k) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL22329UFU10Z* 329UZ 50 -40 to +125 10 Ld MSOP M10.118 ISL22329WFU10Z* 329WZ 10 -40 to +125 10 Ld MSOP M10.118 *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6330 Rev 2.00 September 4, 2009 Page 1 of 13 ISL22329 Block Diagram VCC VCC SCL SDA A0 I2C INTERFACE A1 POWER-UP INTERFACE, CONTROL AND STATUS LOGIC WR1 A2 RW1 VCC NONVOLATILE REGISTERS SHDN WR0 RW0 GND Pin Descriptions MSOP PIN SYMBOL DESCRIPTION Device address input for the I2C interface 1 A2 2 SCL Open drain I2C interface clock input 3 SDA Open drain serial data I/O for the I2C interface 4 GND Device ground pin 5 RW1 “Wiper” terminal of DCP1 6 A0 Device address input for the I2C interface 7 A1 Device address input for the I2C interface 8 VCC 9 SHDN Shutdown active low input 10 RW0 “Wiper” terminal of DCP0 FN6330 Rev 2.00 September 4, 2009 Power supply pin Page 2 of 13 ISL22329 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 2) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV Thermal Resistance (Typical, Note 1) JA (°C/W) 10 Lead MSOP package . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER End-to-End Resistance TEST CONDITIONS MIN (Note 13) TYP (Note 3) MAX (Note 13) UNIT W option 10 k U option 50 k End-to-End Resistance Tolerance W and U option End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 11) U option ±80 ppm/°C (Note 11) VCC = 3.3V @ +25°C, wiper current = VCC/RTOTAL 70  25 pF RW (Note 13) Wiper Resistance CW (Note 11) Wiper Capacitance -20 +20 % VOLTAGE DIVIDER MODE ( measured at RWi, unloaded; i = 0 or 1) INL (Note 8) Integral Non-linearity Monotonic over all tap positions -1 1 LSB (Note 4) DNL (Note 7) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB (Note 4) ZSerror (Note 5) Zero-scale Error W option 0 1 5 U option 0 0.5 2 LSB (Note 4) FSerror (Note 6) Full-scale Error W option -5 -1 0 U option -2 -1 0 VMATCH (Note 9) DCP to DCP mAtching Wipers at the same tap position -2 TCV (Note 10) Ratiometric Temperature Coefficient DCP register set to 40 hex FN6330 Rev 2.00 September 4, 2009 2 ±4 LSB (Note 4) LSB (Note 4) ppm/°C Page 3 of 13 ISL22329 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL ICC1 ICC2 ISB ISD PARAMETER TEST CONDITIONS MIN (Note 13) TYP (Note 3) MAX (Note 13) UNIT VCC Supply Current (volatile write/read) 10k DCP, fSCL = 400kHz; (for I2C active, read and write states) 1.4 mA VCC Supply Current (volatile write/read, non-volatile read) 50k DCP, fSCL = 400kHz; (for I2C active, read and write states) 450 µA VCC Supply Current ( non-volatile write/read) 10k DCP, fSCL = 400kHz; (for I2C active, read and write states) 3.5 mA VCC Supply Current (non-volatile write/read) 50k DCP, fSCL = 400kHz; (for I2C active, read and write states) 2.0 mA VCC Current (standby) VCC = +5.5V , 10k DCP, I2C interface in standby state 1.22 mA VCC = +3.6V, 10k DCP, I2C interface in standby state 800 µA VCC = +5.5V, 50k DCP, I2C interface in standby state 320 µA VCC = +3.6V, 50k DCP, I2C interface in standby state 250 µA VCC = +5.5V @ +85°C, I2C interface in standby state 3 µA VCC = +5.5V @ +125°C, I2C interface in standby state 5 µA VCC = +3.6V @ +85°C, I2C interface in standby state 2 µA VCC = +3.6V @ +125°C, I2C interface in standby state 4 µA 1 µA VCC Current (shutdown) Leakage Current, at Pins A0, A1, A2, SHDN, SDA, and SCL Voltage at pin from GND to VCC tWRT (Note 11) DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to wiper new position 1.5 µs tShdnRec (Note 11) DCP Recall Time From Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs ILkgDig Vpor Power-on Recall Voltage VccRamp VCC Ramp Rate tD Power-up Delay Minimum VCC at which memory recall occurs -1 2.0 2.6 0.2 V V/ms 3 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 12) Non-volatile Write Cycle Time FN6330 Rev 2.00 September 4, 2009 Temperature T < +55°C 1,000,000 Cycles 50 Years 12 20 ms Page 4 of 13 ISL22329 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 13) TYP (Note 3) MAX (Note 13) UNIT SERIAL INTERFACE SPECS VIL A2, A1, A0, SDA, and SCL Input Buffer Low Voltage -0.3 0.3*VCC V VIH A2, A1, A0, SDA, and SCL Input Buffer High Voltage 0.7*VCC VCC + 0.3 V Hysteresis VOL Cpin (Note 10) fSCL SDA and SCL Input Buffer Hysteresis 0.05* VCC SDA Output Buffer LOW Voltage, Sinking 4mA V 0 A2, A1, A0, SDA, and SCL Pin Capacitance 0.4 10 SCL Frequency tsp Pulse Width Suppression Time at SDA and SCL Inputs tAA SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until Valid SDA exits the 30% to 70% of VCC window Any pulse narrower than the max spec is suppressed V pF 400 kHz 50 ns 900 ns tBUF Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge; both crossing 70% of VCC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge; both crossing 70% of VCC 1300 ns Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0 ns tR SDA and SCL Rise Time From 30% to 70% of VCC 20 + 0.1*Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VCC 20 + 0.1*Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k~2.5k For Cb = 40pF, max is about 15k~20k 1 tDH FN6330 Rev 2.00 September 4, 2009 k Page 5 of 13 ISL22329 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER MIN (Note 13) TEST CONDITIONS TYP (Note 3) MAX (Note 13) UNIT tSU:A A2, A1 and A0 Setup Time Before START condition 600 ns tHD:A A2, A1 and A0 Hold Time After STOP condition 600 ns NOTES: 3. Typical values are for TA = +25°C and 3.3V supply voltage. 4. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 5. ZS error = V(RW)0/LSB. 6. FS error = [V(RW)127 – VCC]/LSB. 7. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 8. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127. 9. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. Max  V  RW  i  – Min  V  RW  i  10 6 10. TC V = ----------------------------------------------------------------------------------------------  --------------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max() is the maximum value of the wiper  Max  V  RW  i  + Min  V  RW  i    2 +165°C voltage and Min () is the minimum value of the wiper voltage over the temperature range. 11. This parameter is not 100% tested. 12. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal nonvolatile write cycle. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SDA vs SCL Timing tHIGH tF SCL tLOW tHD:STO tsp tR tSU:DAT tSU:STA SDA (INPUT TIMING) tHD:DAT tHD:STA tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0 and A1 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1 FN6330 Rev 2.00 September 4, 2009 Page 6 of 13 ISL22329 Typical Performance Curves 100 1.2 80 60 50 40 30 0.8 0.6 0.4 VCC = 3.3V, T = -40°C VCC = 3.3V, T = +20°C 20 0.2 10 0 T = +125°C 1.0 70 Isb (µA) WIPER RESISITANCE () 1.4 VCC = 3.3V, T = +125°C 90 0 20 40 60 80 100 T = +25°C 0 2.7 120 3.2 3.7 TAP POSITION (DECIMAL) 0.2 T = +25°C 0.1 0.1 INL (LSB) DNL (LSB) 5.2 0.2 T = +25°C VCC = 2.7V 0 -0.1 VCC = 2.7V 0 -0.1 VCC = 5.5V VCC = 5.5V 0 20 40 60 80 100 TAP POSITION (DECIMAL) -0.2 120 FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 1.1 40 60 80 100 TAP POSITION (DECIMAL) 120 10k -0.3 FSerror (LSB) 0.7 VCC = 2.7V VCC = 5.5V 0.3 VCC = 2.7V 50k VCC = 5.5V -0.6 -0.9 10k 0.1 -1.2 50k -0.1 -0.3 -40 20 0.0 0.9 0.5 0 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 1.3 ZSerror (LSB) 4.7 FIGURE 2. STANDBY ICC vs VCC FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W) -0.2 4.2 VCC (V) -20 0 20 40 60 TEMPERATURE (ºC) 80 FIGURE 5. ZSerror vs TEMPERATURE FN6330 Rev 2.00 September 4, 2009 100 120 -1.5 -40 -20 0 20 40 60 TEMPERATURE (ºC) 80 100 120 FIGURE 6. FSerror vs TEMPERATURE Page 7 of 13 ISL22329 Typical Performance Curves (Continued) 105 VCC = 2.7V 90 0.5 10 75 50k TCv (ppm/°C) END-TO-END RTOTAL CHANGE (%) 1.0 0.0 60 45 30 -0.5 50 10k 15 VCC = 5.5V -1.0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 7. END-TO-END RTOTAL % CHANGE vs TEMPERATURE 0 16 36 56 76 TAP POSITION (DECIMAL) 96 FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED) MOVEMENT FROM 7Fh TO 00h FIGURE 9. MIDSCALE GLITCH, CODE 3Fh TO 40h Pin Descriptions Potentiometers Pins FIGURE 10. LARGE SIGNAL SETTLING TIME is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. RWI (I = 0,1) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. RW SHDN The SHDN pin forces the resistors to end-to-end open circuit condition and shorts all RWs to GND. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. I2C interface FN6330 Rev 2.00 September 4, 2009 FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE Page 8 of 13 ISL22329 Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bi-directional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. While the ISL22329 is being powered up, all WRs are reset to 40h (64 decimal), which locates RW roughly at the center between GND and VCC. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). SDA requires an external pull-up resistor, since it is an open drain input/output. The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h or 01h to access the WR of DCP0 or DCP1 respectively. SERIAL CLOCK (SCL) Memory Description This is the serial clock input of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input. DEVICE ADDRESS (A2 - A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22329. A maximum of 8 ISL22329 devices may occupy the I2C serial bus. Principles of Operation The ISL22329 is an integrated circuit incorporating two DCPs with their associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometers and memory. The resistor arrays are comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to the initial value. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to Vcc and GND. The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0] = 00h), its wiper terminal (RW) is closest to GND. When the WR register of a DCP contains all ones (WR[6:0] = 7Fh), its wiper terminal (RW) is closest to VCC. As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to GND to the closest to VCC. FN6330 Rev 2.00 September 4, 2009 The ISL22329 contains seven non-volatile and three volatile 8bit registers. The memory map of ISL22329 is on Table 1. The two non-volatile registers (IVRi) at address 0 and 1, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, five non-volatile General Purpose registers from address 2 to address 6 are available. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 8 — ACR 7 Reserved 6 5 4 3 2 General Purpose General Purpose General Purpose General Purpose General Purpose Not Available Not Available Not Available Not Available Not Available 1 0 IVR1 IVR0 WR1 WR0 The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit at access control register (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi. TABLE 2. ACCESS CONTROL REGISTER (ACR) VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note, value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically ANDed with SHDN pin. When this bit is 0, DCPs are in Shutdown mode. Default value of SHDN bit is 1. Page 9 of 13 ISL22329 The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1. Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. TABLE 3. SHDN pin SHDN bit Mode High 1 Normal operation Low 1 Shutdown High 0 Shutdown Low 0 Shutdown All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22329 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 12). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 12). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 13). I2C Serial Interface The ISL22329 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22329 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 12). On power-up of the ISL22329 the SDA pin is in the input mode. The ISL22329 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22329 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010b as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (see Table 4). TABLE 4. IDENTIFICATION BYTE FORMAT Logic values at pins A2, A1, and A0 respectively 1 0 1 0 A2 (MSB) A1 A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS FN6330 Rev 2.00 September 4, 2009 Page 10 of 13 ISL22329 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 SIGNALS FROM THE SLAVE S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 14. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W=0 ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 SIGNALS FROM THE SLAVE S T A IDENTIFICATION R BYTE WITH T R/W = 1 S A T C O K P A C K 1 0 1 0 A2 A1 A0 1 0 0 0 0 A C K A C K A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 15. READ SEQUENCE FN6330 Rev 2.00 September 4, 2009 Page 11 of 13 ISL22329 Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22329 responds with an ACK. At this time, the device enters its standby state (See Figure 14). Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 08h, the internal pointer “rolls over” to address 00h. Non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next nonvolatile write. Thus, non-volatile registers must be written individually. The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 08h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 15). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL22329 responds with an ACK. Then the ISL22329 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 08h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received.The master terminates the read operation (issuing a ACK and STOP condition) following the last bit of the last Data Byte (See Figure 15). © Copyright Intersil Americas LLC 2006-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN6330 Rev 2.00 September 4, 2009 Page 12 of 13 ISL22329 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X  0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X  A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C -A- e D 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - -  5o 15o 5o 15o -  0o 6o 0o 6o Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only FN6330 Rev 2.00 September 4, 2009 Page 13 of 13