ISL22424WFV14Z-TK

DATASHEET ISL22424 Dual Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Bus, 256 Taps The ISL22424 integrates two digitally controlled potentiometers (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WRi) and a non-volatile Initial Value Register (IVRi) that can be directly written to and read by the user. The contents of the WRi control the position of the wiper. At power-up the device recalls the contents of the DCP’s IVRi to the corresponding WRi. The ISL22424 also has 13 General Purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22424 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FN6425 Rev 1.00 September 9, 2015 Features • Two potentiometers in one package • 256 resistor taps • SPI serial interface with write/read capability • Daisy Chain Configuration • Shutdown mode • Non-volatile EEPROM storage of wiper position • 13 General Purpose non-volatile registers • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T 55°C • Wiper resistance: 70 typical @ 1mA • Standby current DCP2 --> ... --> FN6425 Rev 1.00 September 9, 2015 DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. Daisy Chain Read Operation The read operation consists of two parts: first, send read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown on Figure 20 and Figure 21. The first part starts by HIGH to LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW to HIGH transition on CS line. The read instructions are executed during second part of read sequence. It also starts by HIGH to LOW transition on CS line, followed by N two bytes NOP instructions on SDI line and LOW to HIGH transition of CS. The data is read on every even byte during second part of read sequence while every odd byte contains instruction code + address from which the data is being read. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break within an extremely short period of time (