ISL22444UFV20Z

DATASHEET NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL22424 ISL22444 FN6426 Rev 0.00 May 24, 2007 Quad Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Bus, 256 Taps The ISL22444 integrates four digitally controlled potentiometers (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The wipers position is controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WRi) and a non-volatile Initial Value Register (IVRi) that can be directly written to and read by the user. The contents of the WRi control the position of the wiper. At power-up the device recalls the contents of the DCP’s IVRi to the corresponding WRi. The ISL22444 also has 11 General Purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22444 features a dual supply that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four potentiometers in one package • 256 resistor taps • SPI serial interface with write/read capability • Daisy Chain Configuration • Shutdown mode • Non-volatile EEPROM storage of wiper position • 11 General Purpose non-volatile registers • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T 55°C • Wiper resistance: 70 typical @ 1mA • Standby current ... --> FN6426 Rev 0.00 May 24, 2007 Page 14 of 19 ISL22444 N DCP IN A CHAIN CS SCK DCP0 MOSI MISO µC DCP1 DCP2 CS CS CS SCK SCK SCK SDI SDO SDI SDO SDI DCP(N-1) CS SCK SDO SDI SDO FIGURE 18. DAISY CHAIN CONFIGURATION CS SCK 16 CLKLS WR SDI 16 CLKS 16 CLKS D C P2 SDO 0 WR D C P1 WR D C P0 WR D C P2 WR D C P1 WR D C P2 SDO 1 SDO 2 FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR SDO DATA IN DATA OUT FIGURE 20. TWO BYTE OPERATION FN6426 Rev 0.00 May 24, 2007 Page 15 of 19 ISL22444 CS SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 16 CLKS 16 CLKS 16 CLKS 16 CLKS RD DCP0 NOP NOP NOP DCP2 OUT DCP1 OUT DCP0 OUT SDO FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP Application Example Figure 22 shows an example of using ISL22444 for gain setting and offset correction in a high side current measurement application. DCP0 applies a programmable offset voltage of ±25mV to the FB+ pin of the Instrumentation Amplifier ISL28272 to adjust output offset to zero voltages. DCP1 programs the gain of the ISL28272 from 90 to 110 with 5V output for 10A current through current sense resistor. DCP2 and DCP3 are used for another channel of dual ISL28272 correspondently (not shown in Figure 22). More application examples can be found at http://www.intersil.com/data/an/AN1145.pdf FN6426 Rev 0.00 May 24, 2007 Page 16 of 19 ISL22444 1.2V DC/DC CONVERTER OUTPUT PROCESSOR LOAD 10A, MAX 0.005 10k +5V 10k 0.1µF 16 V+ 6 IN+ 1/2 ISL28272 EN 7 VOUT 2 5 INVOUT = 0V to + 5V to ADC 3 FB+ +5V 8 RH1 RH0 RW1 R2 1k, 1% RW0 50k R4 150k, 1% 4 FB- V- R1 50k, 1% RL0 R5 309, 1% RL1 50k DCP1 (1/4 ISL22444U) DCP0 (1/4 ISL22444U) PROGRAMMABLE OFFSET ±25mV PROGRAMMABLE GAIN 90 TO 110 R3 R6 50k, 1% 1.37k, 1% -5V ISL22444UFV20Z +5V SPI BUS 16 5 6 15 14 4 7 -5V 17 Vcc SCK SDO SDI CS NC GND V- RH0 RL0 RW0 RH1 RL1 RW1 RH2 RL2 RW2 RH3 RL3 RW3 18 19 20 DCP0 13 12 11 DCP1 10 9 8 DCP2 1 2 3 DCP3 FIGURE 22. CURRENT SENSING WITH GAIN AND OFFSET CONTROL FN6426 Rev 0.00 May 24, 2007 Page 17 of 19 ISL22444 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.5x5 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - 0.02 0.05 - A2 - 0.65 1.00 9 0.38 5, 8 A3 b 0.20 REF 0.23 0.30 9 D 5.00 BSC - D1 4.75 BSC 9 D2 2.95 E E1 E2 3.10 3.25 7, 8 5.00 BSC - 4.75 BSC 2.95 e 3.10 9 3.25 7, 8 0.65 BSC - k 0.20 - - - L 0.35 0.60 0.75 8 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 9  - - 12 9 Rev. 4 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P &  are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the "b" dimension. FN6426 Rev 0.00 May 24, 2007 Page 18 of 19 ISL22444 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E 0.25(0.010) M E1 2 INCHES SYMBOL 3 0.05(0.002) -A- 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE GAUGE PLANE -B1 M20.173 B M SEATING PLANE L A D -C- e  A2 A1 b 0.10(0.004) M 0.25 0.010 c 0.10(0.004) C A M B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MIN MAX MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N  20 0o 20 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 7 8o Rev. 1 6/98 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) © Copyright Intersil Americas LLC 2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6426 Rev 0.00 May 24, 2007 Page 19 of 19