ISL22449UFV14Z

DATASHEET OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT ISL22446 ISL22449 Quad Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Bus, 128 Taps, Wiper Only The ISL22449 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. FN6333 Rev 3.00 July 17, 2009 Features • Four potentiometers in one package The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP’s IVR to the corresponding WR. The DCP can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing. Pinout • 128 resistor taps • SPI serial interface • Non-volatile storage of wiper position • Wiper resistance: 70 typical • Shutdown mode • Shutdown current 6.5µA max • Power supply: 2.7V to 5.5V • 50kor 10k total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 14 Lead TSSOP ISL22449 (14 LD TSSOP) TOP VIEW • Pb-free (RoHS compliant) RW3 1 14 RW0 NC 2 13 SHDN SCK 3 12 VCC SDO 4 11 NC GND 5 10 SDI RW2 6 9 CS RW1 7 8 NC Ordering Information PART NUMBER (Note) PART MARKING RESISTANCE OPTION (k) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL22449UFV14Z* 22449 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL22449WFV14Z* 22449 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6333 Rev 3.00 July 17, 2009 Page 1 of 13 ISL22449 Block Diagram VCC VCC WR3 SCK SDI SDO SPI INTERFACE CS POWER UP INTERFACE, CONTROL AND STATUS LOGIC RW3 VCC WR2 RW2 VCC WR1 NONVOLATILE REGISTERS SHDN RW1 VCC WR0 RW0 GND Pin Descriptions TSSOP PIN SYMBOL 1 RW3 2 NC 3 SCK SPI clock input 4 SDO SPI open drain data output 5 GND Device ground pin and the RL connection for each DCP 6 RW2 “Wiper” terminal of DCP2 7 RW1 “Wiper” terminal of DCP1 8 NC 9 CS SPI Chip Select active low input 10 SDI SPI data input 11 NC 12 VCC 13 SHDN Shutdown active low input 14 RW0 “Wiper” terminal of DCP0 FN6333 Rev 3.00 July 17, 2009 DESCRIPTION “Wiper” terminal of DCP3 Power supply pin and the RH connection for each DCP Page 2 of 13 ISL22449 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 2) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV Thermal Resistance (Typical, Note 1) JA (°C/W) 14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100 Maximum Junction Temperature (Plastic Package) . . . . . . . .+150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications SYMBOL RTOTAL RW CW (Note 13) Over recommended operating conditions unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER End-to-End resistance TEST CONDITIONS MIN TYP (Note 3) MAX UNIT W option 10 k U option 50 k End-to-End resistance tolerance W and U option End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 13) U option ±80 ppm/°C (Note 13) VCC = 3.3V @ +25°C, wiper current = VCC/RTOTAL 70 Wiper resistance -20 +20 200 25 Wiper capacitance %  pF VOLTAGE DIVIDER MODE (measured at RWi, unloaded; i = 0, 1, 2 or 3) INL (Note 8) Integral non-linearity DNL (Note 7) Differential non-linearity Monotonic over all tap positions ZSerror (Note 5) Zero-scale error W option 0 U option FSerror (Note 6) Full-scale error -1 1 LSB (Note 4) -0.5 0.5 LSB (Note 4) 1 5 LSB (Note 4) 0 0.5 2 LSB (Note 4) W option -5 -1 0 LSB (Note 4) U option -2 -1 0 LSB (Note 4) -2 2 LSB (Note 4) VMATCH (Note 9) DCP to DCP matching Any two DCPs at same tap position TCV (Note 10) Ratiometric temperature coefficient DCP register set to 40 hex FN6333 Rev 3.00 July 17, 2009 ±4 ppm/°C Page 3 of 13 ISL22449 Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL ICC1 ICC2 ISB ISD ILkgDig PARAMETER TEST CONDITIONS MIN 2.5 mA VCC Supply Current (volatile write/read) VCC = +3.6V, 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) 0.65 mA VCC Supply Current ( non-volatile write/read) VCC = +5.5V, 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) 4.0 mA VCC Supply Current ( non-volatile write/read) VCC = +5.5V, 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) 3.0 mA VCC Current (standby) VCC = +5.5V, 10k DCP, SPI interface in standby state 2.4 mA VCC = +5.5V, 50k DCP, SPI interface in standby state 525 µA VCC = +3.6V, 10k DCP, SPI interface in standby state 1.6 mA VCC = +3.6V, 50k DCP, SPI interface in standby state 350 µA VCC = +5.5V @ +85°C, SPI interface in standby state 5 µA VCC = +5.5V@ +125°C, SPI interface in standby state 6.5 µA VCC = +3.6V @ +85°C, SPI interface in standby state 4 µA VCC = +3.6V @ +125°C, SPI interface in standby state 5.5 µA 1 µA VCC Current (shutdown) Leakage current, at pins SHDN, SCK, Voltage at pin from GND to VCC SDI, SDO and CS tShdnRec (Note 13) DCP recall time from shutdown mode From rising edge of SHDN signal to wiper stored position and RH connection -1 SCK falling edge of last bit of DCP data byte to wiper new position SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection tD UNIT VCC = +3.6V, 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) DCP wiper response time VccRamp MAX VCC Supply Current (volatile write/read) tWRT (Note 13) Vpor TYP (Note 3) Power-on recall voltage Minimum VCC at which memory recall occurs Vcc ramp rate Power-up delay 1.5 µs 1.5 µs 1.5 µs 2.0 2.6 0.2 V V/ms 3 VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 11) Temperature T < +55°C 1,000,000 Cycles 50 Years Non-volatile Write cycle time 12 20 ms 0.3*VCC V SERIAL INTERFACE SPECIFICATIONS VIL SHDN, SCK, SDI, and CS input buffer LOW voltage FN6333 Rev 3.00 July 17, 2009 -0.3 Page 4 of 13 ISL22449 Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL PARAMETER VIH SHDN, SCK, SDI, and CS input buffer HIGH voltage 0.7*VCC Hysteresis SHDN, SCK, SDI, and CS input buffer hysteresis 0.05* VCC VOL TEST CONDITIONS SDO output buffer LOW voltage IOL = 4mA Rpu (Note 12) SDO pull-up resistor off-chip Maximum is determined by tRO and tFO with maximum bus load Cbus = 30pF, fSCK = 5MHz Cpin (Note 13) MIN TYP (Note 3) UNIT VCC+0.3 V V 0.4 V 2 k SHDN, SCK, SDI, SDO and CS pin capacitance 10 pF fSCK SPI frequency 5 MHz tCYC SPI clock cycle time 200 ns tWH SPI clock high time 100 ns tWL SPI clock low time 100 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SDI, SCK and CS input setup time 50 ns tH SDI, SCK and CS input hold time 50 ns tRI SDI, SCK and CS input rise time 10 ns tFI SDI, SCK and CS input fall time 10 20 ns SDO output Disable time 0 100 ns 350 ns tDIS 0 MAX tV SDO output valid time tHO SDO output hold time tRO SDO output rise time Rpu = 2k, Cbus = 30pF 60 ns tFO SDO output fall time Rpu = 2k, Cbus = 30pF 60 ns tCS CS deselect time tWRT 0 ns 2 Wiper Response Time after SPI write to WR register µs 1.5 µs NOTES: 3. Typical values are for TA = +25°C and 3.3V supply voltage. 4. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 5. ZS error = V(RW)0/LSB. 6. FS error = [V(RW)127 – VCC]/LSB. 7. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 8. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 127 9. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. Max  V  RW  i  – Min  V  RW  i  10 6 10. TC = ---------------------------------------------------------------------------------------------  ----------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V  Max  V  RW  i  + Min  V  RW  i    2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 12. Rpu is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates. 13. This parameter is not 100% tested. FN6333 Rev 3.00 July 17, 2009 Page 5 of 13 ISL22449 Timing Diagrams Input Timing tCS CS tCYC tLEAD SCK tSU tH ... tWL tRI tFI tWH ... MSB SDI tLAG LSB HIGH IMPEDANCE SDO Output Timing CS SCK ... tV tDIS ... MSB SDO SDI tHO LSB ADDR XDCP Timing (for All Load Instructions) CS SCK ... tWRT MSB SDI ... LSB VW SDO HIGH IMPEDANCE FN6333 Rev 3.00 July 17, 2009 Page 6 of 13 ISL22449 Typical Performance Curves 100 1.2 80 1.0 70 60 ISB (µA) WIPER RESISITANCE () 1.4 VCC = 3.3V, T = +125°C 90 50 40 30 0.6 0.4 T = +25°C VCC = 3.3V, T = -40°C VCC = 3.3V, T = +20°C 20 0.2 10 0 T = +125°C 0.8 0 20 40 60 80 100 0 2.7 120 3.2 3.7 TAP POSITION (DECIMAL) 4.2 4.7 5.2 VCC (V) FIGURE 2. STANDBY ICC vs VCC FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC/RTOTAL] FOR 10k (W) 0.2 0.2 T = +25°C T = +25°C VCC = 2.7V 0.1 INL (LSB) DNL (LSB) 0.1 0 -0.1 VCC = 2.7V 0 -0.1 VCC = 5.5V -0.2 0 20 40 VCC = 5.5V 60 80 100 -0.2 120 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 1.3 0.0 10k 1.1 -0.3 ZSERROR (LSB) ZSERROR (LSB) 0.9 0.7 0.5 VCC = 2.7V VCC = 5.5V 0.3 0.1 -0.3 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 5. ZSERROR vs TEMPERATURE FN6333 Rev 3.00 July 17, 2009 VCC = 5.5V 50k -0.6 -0.9 10k -1.2 50k -0.1 VCC = 2.7V 100 120 -1.5 -40 -20 0 20 40 60 80 100 TEMPERATURE (ºC) FIGURE 6. FSERROR vs TEMPERATURE Page 7 of 13 120 ISL22449 Typical Performance Curves (Continued) 105 90 0.5 75 VCC = 2.7V TCv (ppm/°C) END TO END RTOTAL CHANGE (%) 1.0 50k 0.0 VCC = 5.5V 10k -0.5 60 45 50k 30 10k 15 -1.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (ºC) FIGURE 7. END TO END RTOTAL % CHANGE vs TEMPERATURE 0 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh FIGURE 10. LARGE SIGNAL SETTLING TIME Pin Description Potentiometers Pins RWI (I = 0, 1, 2, 3) RW RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistors to end-to-end open circuit condition and shorts all RWs to GND. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with the SHDN bit in the ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE Bus Interface Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. FN6333 Rev 3.00 July 17, 2009 Page 8 of 13 ISL22449 SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22449, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22449 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. DCP2 or DCP3 respectively. The WRi and IVRi can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL22449 contains seven non-volatile and five volatile 8-bit registers. The memory map of ISL22449 is on Table 1. The four non-volatile registers (IVRi) at address 0, 1, 2 and 3, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, three non-volatile General Purpose registers from address 4 to address 6 are available. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 8 — ACR Principles of Operation 7 The ISL22449 is an integrated circuit incorporating four DCPs with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometers and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. 6 5 4 General Purpose General Purpose General Purpose Not Available Not Available Not Available 3 2 1 0 IVR3 IVR2 IVR1 IVR0 WR3 WR2 WR1 WR0 Reserved The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. The non-volatile IVRi and volatile WRi registers are accessible with the same address. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi is recalled and loaded into the corresponding WRi to set the wiper to the initial value. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access is to wiper registers WR or initial value registers IVR. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to Vcc and GND. The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to GND. When the WR register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper terminal (RW) is closest to VCC. As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to GND to the closest to VCC. While the ISL22449 is being powered up, all four WRs are reset to 40h (64 decimal), which locates RW roughly at the center between GND and VCC. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 Bit Name VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WRi is accessible. Note, value is written to IVRi register also is written to the WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically AND with SHDN pin. When this bit is 0, DCPs are in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1. Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. The SPI interface register address bits have to be set to 0000b, 0001b, 0010b or 0011b to access the WR of DCP0, DCP1, FN6333 Rev 3.00 July 17, 2009 Page 9 of 13 ISL22449 Write Operation TABLE 3. SHDN pin SHDN bit Mode High 1 Normal operation Low 1 Shutdown High 0 Shutdown Low 0 Shutdown SPI Serial Interface The ISL22449 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22449. SCK and CS lines are controlled by the host or master. The ISL22449 operates only as a slave device. A Write operation to the ISL22449 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte following by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to addresses 0000b to 0011b, the MSB at address 8 (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and nonvolatile registers. Refer to “Memory Description” on page 9 and Figure 12. Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 0110b, the internal pointer “rolls over” to address 0000b. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms. Thus, non-volatile registers must be written individually. Protocol Conventions Read Operation The first byte sent to the ISL22449 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0. A read operation to the ISL22449 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte following by “dummy” Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 13). TABLE 4. IDENTIFICATION BYTE FORMAT 0 1 0 1 0 0 0 (MSB) 0 (LSB) The next byte sent to the ISL22449 contains the instruction and register pointer information. The four MSBs are the instruction and four LSBs are register address (see Table 5). TABLE 5. IDENTIFICATION BYTE FORMAT 7 6 5 4 3 2 1 0 I3 I2 I1 I0 R3 R2 R1 R0 There are only two valid instruction sets: 1011(binary) - is a Read operation 1100(binary) - is a Write operation FN6333 Rev 3.00 July 17, 2009 The ISL22449 will provide the Data Bytes to the SDO pin as long as SCK is provided by the host from the registers indicated by an internal pointer. This pointer initial value is determined by the register address in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 0110b, the pointer “rolls over” to 0000b, and the device continues to output the data for each received SCK clock. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. Page 10 of 13 ISL22449 CS SCK SDI 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 FIGURE 12. THREE BYTE WRITE SEQUENCE CS SCK SDI DON’T CARE 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 SDO 0 D6 D5 D4 D3 FIGURE 13. THREE BYTE READ SEQUENCE Applications Information Communicating with ISL22449 Communication with ISL22449 proceeds using SPI interface through the ACR (address 1000b), IVRi (addresses 0000b, 0001b, 0010b and 0011b) and WRi (addresses 0000b, 0001b, 0010b and 0011b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 1000b to 1. The non-volatile IVRi stores the power up value of the wiper. IVRs are accessible when MSB bit at address 1000b is set to 0. Writing a new value to the IVRi register will set a new power up position for the wiper. Also, writing to this register will load the same value into the corresponding WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different. FN6333 Rev 3.00 July 17, 2009 Page 11 of 13 ISL22449 Examples: A. Writing to the IVR: This sequence will write a new value (77h) to the IVR2(non-volatile): Set the ACR (Addr 1000b) for NV write (40h) Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 (Sent to SDI) 0 0 0 0 Set the IVR (Addr 0010b) to 77h Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 (Sent to SDI) 0 1 1 1 0 1 1 0 0 (Sent to SDI) 0 0 0 0 x x x B. Reading from the WR: This sequence will read the value from the WR3 (volatile): Write to ACR first to access the volatile WRs Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 Read the data from WR3 (Addr 0011b) Send the ID byte, Instruction Byte, then Read the Data byte 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 1 x x x x x (Out on SDO) FN6333 Rev 3.00 July 17, 2009 Page 12 of 13 ISL22449 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E 0.25(0.010) M E1 2 INCHES SYMBOL 3 0.05(0.002) -A- 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE GAUGE PLANE -B1 M14.173 B M SEATING PLANE L A D -C- e  A2 A1 b 0.10(0.004) M 0.25 0.010 c 0.10(0.004) C A M B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MIN MAX MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N  14 0o 14 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 7 8o Rev. 2 4/06 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) © Copyright Intersil Americas LLC 2006-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6333 Rev 3.00 July 17, 2009 Page 13 of 13