ISL22512WFRU10Z-TK

DATASHEET ISL22512 Single Push Button Controlled Potentiometer (XDCP™) Low Noise, Low Power, 16 Taps, Push Button Controlled Potentiometer The Intersil ISL22512 is a three-terminal digitally-controlled potentiometer (XDCP) implemented by a resistor array composed of 15 resistive elements and a wiper switching network. The ISL22512 features a push button control, a shutdown mode, as well as an industry-leading µTQFN package. The push button control has individual PU and PD inputs for adjusting the wiper. To eliminate redundancy, the wiper position will automatically increment or decrement if one of these inputs is held longer than one second. Forcing both PU and PD low for more than two seconds activates shutdown mode. Shutdown mode disconnects the top of the resistor chain and moves the wiper to the lowest position, minimizing power consumption. The three terminals accessing the resistor chain naturally configure the ISL22512 as a voltage divider. A rheostat is easily formed by floating an end terminal or connecting it to the wiper. CONTROL BLOCK NC RW ASE RL VSS (GROUND) PU 1 9 VCC PD 2 µTQFN 8 ASE RH 3 (Top View) 7 RL VSS 4 6 RW 5 RH PU PD O 10 NC VCC (SUPPLY VOLTAGE) PU PD RH VSS O 1 2 SOIC 3 (Top View) 4 8 7 6 5 VCC ASE RL RW FN6679 Rev 3.00 October 12, 2015 Features • Solid-State Non-Volatile Potentiometer • Push Button Controlled • Single or Auto Increment/Decrement - Fast Mode after 1s Button Press • AUTOSTORE of Last Wiper Position or Manual Store of Wiper Position • Shutdown Mode • 16 Wiper Tap Points - Middle Scale Wiper Position on Power-Up • Low Power CMOS - VCC = 2.7V to 5.5V - Terminal Voltage, 0 to VCC - Standby Current, 3µA max • RTOTAL Value = 10k • High Reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T  +55°C • Packages - 8 Ld SOIC - 10 Ld µTQFN (2.1mmx1.6mm) • Pb-Free (RoHS Compliant) Applications • Volume Control • LED/LCD Brightness Control • Contrast Control • Programming Bias Voltages • Ladder Networks FN6679 Rev 3.00 October 12, 2015 Page 1 of 13 ISL22512 Ordering Information PART NUMBER PART MARKING RTOTAL (k) TEMP. RANGE(°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL22512WFB8Z* (Note 1) 22512 WFBZ 10 -40 to +125 8 Ld SOIC M8.15 ISL22512WFRU10Z-TK (Note 2) (No longer available, recommended replacement: ISL22512WFB8Z-TK) GE 10 -40 to +125 10 Ld µTQFN Tape and Reel L10.2.1x1.6A *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL22512 (10 LD ΜTQFN) TOP VIEW ISL22512 (8 LD SOIC) TOP VIEW RL VSS 4 5 RW PD 2 RH 3 VSS 4 PO RT 6 SU P 3 1 10 RH PU 9 VCC 8 ASE 7 RL 6 RW R ASE O 7 BL E 2 LA PD O NO 5 VCC AV AI 8 LO NG ER 1 ED NC O PU NC Pin Descriptions SOIC PIN µTQFN PIN SYMBOL 1 1 PU The PU is a falling-edge triggered input with internal pull-up. Toggling PU will move the wiper close to RH terminal. 2 2 PD The PD is a falling-edge triggered input with internal pull-up. Toggling PD will move the wiper close to RL terminal. 3 3 RH The RH and RL pins of the ISL22512 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the PU/PD input. 4 4 VSS Ground 5 6 RW The RW pin is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer. 6 7 RL The RH and RL pins of the ISL22512 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the PU/PD input. 7 8 ASE Active low AUTOSTORE enable input or Manual Store active low input 8 9 VCC Supply Voltage 5, 10 NC No connection FN6679 Rev 3.00 October 12, 2015 BRIEF DESCRIPTION Page 2 of 13 ISL22512 Block Diagrams VCC (SUPPLY VOLTAGE) PU PD 4-BIT UP/DOWN COUNTER CONTROL AND MEMORY PD 30 29 RH PU RH 31 4-BIT NONVOLATILE MEMORY RW ASE RL ASE STORE AND CONTROL RECALL CIRCUITRY 28 ONE OF THIRTY TWO DECODER TRANSFER GATES RESISTOR ARRAY RW 2 1 VSS (GROUND) GENERAL FN6679 Rev 3.00 October 12, 2015 0 DETAILED RL Page 3 of 13 ISL22512 Absolute Maximum Ratings Thermal Information Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at PU and PD Pin with Respect to GND . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance (Typical, Notes 3, 4) JA (°C/W) JC (°C/W) 10 Lead µTQFN (Notes 3, 4) . . . . . . . . 150 48.3 8 Lead SOIC (Note 3) . . . . . . . . . . . . . 125 N/A Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JC is for the location in the center of the exposed metal pad on the package underside. Potentiometer Specifications Over recommended operating conditions, unless otherwise specified. SYMBOL RTOTAL PARAMETER TEST CONDITIONS MIN (Note 18) RH to RL Resistance -20 End-to-End Temperature Coefficient RW CH/CL/CW (Note 17) ILkgDCP UNIT k +20 ±80 Wiper Resistance VCC = 3.3V, wiper current IRW = VCC/RTOTAL VRH and VRL Terminal Voltages VRH and VRL to GND Noise on Wiper Terminal From 0Hz to 10MHz 130 0 Potentiometer Capacitance Leakage on DCP Pins MAX (Note 18) 10 RH to RL Resistance Tolerance VRH, VRL TYP (Note 5) Voltage at pin from GND to VCC % ppm/°C (Note 16) 400  VCC V -80 dBV 10/10/25 pF 0.05 0.4 µA -1 1 LSB (Note 6) -0.5 0.5 LSB (Note 6) VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW unloaded) INL (Note 10) Integral Non-Linearity DNL (Note 9) Differential Non-Linearity ZSerror (Note 7) Zero-scale Error 0 0.1 2 LSB (Note 6) FSerror (Note 8) Full-scale Error -2 -0.1 0 LSB (Note 6) TCV (Note 11) fCUTOFF Monotonic over all tap positions Ratiometric Temperature Coefficient Wiper from 5 hex to 1F hex ±25 ppm/°C 3dB Cut-Off Frequency 500 kHz Wiper at the middle scale RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 15) Integral Non-Linearity RDNL (Note 14) Differential Non-Linearity Roffset (Note 13) Offset FN6679 Rev 3.00 October 12, 2015 DCP register set between 1 hex and 1F hex; monotonic over all tap positions -1.5 1.5 MI (Note 12) -0.5 0.5 MI (Note 12) 2 MI (Note 12) 0 1 Page 4 of 13 ISL22512 DC Electrical Specifications SYMBOL Over recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN (Note 18) TYP (Note 5) MAX (Note 18) UNIT ICC VCC Active Current VCC = 5.5V, perform wiper move operation 150 µA ICC VCC Current During Store Operation VCC = 5.5V, perform non-volatile store operation 2 mA ISB Standby Current 3 µA ILkg PU, PD Input Leakage Current +2 µA VIH PU, PD Input HIGH Voltage 0.6 VIL PU, PD input LOW Voltage CIN (Note 17) PU, PD Input Capacitance Rpull_up (Note 17) Pull-Up Resistor for PU and PD VIN = VSS to VCC -2 VCC x 0.7 V VCC x 0.1 VCC = 3.3V, TA = +25°C, f = 1MHz V 10 pF 1 M EEPROM SPECIFICATIONS EEPROM Endurance AC Electrical Specifications SYMBOL PARAMETER Time Between Two Separate Push Button Events tDB Debounce Time tS FAST tstdn (Note 17) tPU tR VCC Cycles 50 Years Over recommended operating conditions unless otherwise specified. tGAP tS SLOW 1,000,000 Temperature 55°C EEPROM Retention MIN (Note 18) TYP (Note 5) MAX (Note 18) 2 UNIT ms 15 28 ms Wiper Change on a Slow Mode 100 250 390 ms Wiper Change on a Fast Mode 25 50 78 ms Time to Enter Shutdown Mode (keep PU and PD LOW) 2 Power-Up to Wiper Stable VCC Power-Up Rate s 500 µs 50 V/ms 0.2 NOTES: 5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)15 – V(RW)0]/15. V(RW)31 and V(RW)0 are voltage on RW pin for the DCP register set to 0F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)31 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB -1, for i = 1 to 15; i is the DCP register setting. 10. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 15 Max  V  RW  i  – Min  V  RW  i  10 6 11. TC = ---------------------------------------------------------------------------------------------  ---------------------for i = 5 to 15 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V  Max  V  RW  i  + Min  V  RW  i    2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. MI = |RW15 – RW0|/15. MI is a minimum increment. RW15 and RW0 are the measured resistances for the DCP register set to 1F hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW15/MI, when measuring between RW and RH. 14. RDNL = (RWi – RWi-1)/MI, for i = 1 to 15. 15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 15. 6 for i = 5 to 15, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is the  Max  Ri  – Min  Ri   10 TC R = ----------------------------------------------------------------  --------------------- minimum value of the resistance over the temperature range.  Max  Ri  + Min  Ri    2 +165°C 17. Limits should be considered typical and are not production tested. 16. 18. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. FN6679 Rev 3.00 October 12, 2015 Page 5 of 13 ISL22512 Slow Mode Timing tDB tGAP PU MI* VW *MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage. Fast Mode Timing tDB PU tS FAST tS SLOW MI* VW 1s *MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage. Shutdown Mode Timing tDB 2s SHUTDOWN MODE PU PD VW AUTOSTORE Mode Timing tDB 2s 250ms 20ms PU MEMORY WRITE CYCLE PD (HIGH) ASE (LOW) WIPER POSITION N FN6679 Rev 3.00 October 12, 2015 N+1 N+2 Page 6 of 13 ISL22512 Typical Performance Curves 3.0 160 VCC = 5.5V 2.5 VCC = 5V 120 2.0 +25ºC 100 ICC (µA) WIPER RESISTANCE () 140 +125ºC 80 60 1.0 40 -40ºC 0 3 6 VCC = 2.7V 0.5 20 0 1.5 9 12 0 15 -40 -15 10 FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W) 60 85 110 FIGURE 2. STANDBY ICC vs TEMPERATURE 0.05 0.10 VCC = 5.5V 0.03 0.05 0.01 INL (LSB) DNL (LSB) 35 TEMPERATURE (°C) TAP POSITION (DECIMAL -0.01 VCC = 5.5V 0.00 VCC = 2.7V -0.05 -0.03 VCC = 2.7V -0.05 0 3 6 9 12 -0.10 0 15 3 TAP POSITION (DECIMAL FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 12 15 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 0.0030 0 VCC = 2.7V 0.0025 0.0020 VCC = 5.5V 0.0015 0.0010 0.0005 0 -40 -15 10 35 60 85 TEMPERATURE (°C) FIGURE 5. ZS ERROR vs TEMPERATURE FN6679 Rev 3.00 October 12, 2015 110 FULL SCALE ERROR (LSB) ZERO SCALE ERROR (LSB) 9 6 TAP POSITION (DECIMAL) -0.2 -0.4 VCC = 5.5V -0.6 -0.8 VCC = 2.7V -1 -40 -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 6. FS ERROR vs TEMPERATURE Page 7 of 13 ISL22512 Typical Performance Curves (Continued) 0.2 0.5 VCC = 2.7V VCC = 2.7V 0.3 RINL (LSB) RDNL (LSB) 0.1 0.0 VCC = 5.5V -0.1 -0.2 3 0 0.1 -0.1 VCC = 5.5V -0.3 6 9 12 -0.5 15 0 3 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) 9 12 15 FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) 1.2 30 VCC = 5.5V 25 0.6 TCv (ppm/ºC) RTOTAL CHANGE (%) 6 TAP POSITION (DECIMAL) VCC = 2.7V 0.0 20 VCC = 2.7V VCC = 5.5V 15 10 -0.6 5 -1.2 -40 0 -15 10 35 60 TEMPERATURE (ºC) 85 110 5 7 9 11 13 TAP POSITION (DECIMAL) FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE INPUT SINEWAVE 300 TCr (ppm/ºC) 250 200 VCC = 2.7V 150 100 VCC = 5.5V 50 0 MIDSCALE OUTPUT 5 7 3dB CUT OFF = 500kHz 9 11 13 15 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FN6679 Rev 3.00 October 12, 2015 FIGURE 12. FREQUENCY RESPONSE (500kHz) Page 8 of 13 15 ISL22512 Power-Up and Down Requirements There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VRH and VRL, i.e., VCC  VRH,VRL. The VCC ramp rate specification is always in effect. Pin Descriptions RH and RL The RH and RL pins of the ISL22512 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction. RW The RW pin is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer. PU The debounced PU input is used to increment the wiper position. An on-chip pull-up holds the PU input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent higher tap position. PD The debounced PD input is used to decrement the wiper position. An on-chip pull-up holds the PD input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent lower tap position. ASE The debounced ASE (AUTOSTORE enable) pin can be in one of two states: 1. AUTOSTORE is enabled if ASE is held LOW during power-up. 2. AUTOSTORE is disabled if ASE is held HIGH during power-up. A LOW to HIGH transition will initiate a manual store operation. This is for the user who wishes to connect a push button switch to this pin. For every valid push, the ISL22512 will store the current wiper position to the EEPROM. Device Operation There are three sections of the ISL22512: the input control, counter and decode section; the EEPROM memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch, connecting a point on the resistor array to the wiper output. Under the proper conditions, the contents of the counter can be stored in EEPROM memory and retained for future use. The resistor FN6679 Rev 3.00 October 12, 2015 array is comprised of 15 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The ISL22512 is designed to interface directly to two push button switches for effectively moving the wiper up or down. The PU and PD inputs increment or decrement a 4-bit counter respectively. The output of this counter is decoded to select one of the thirty-two wiper positions along the resistive array. The wiper increment input, PU and the wiper decrement input, PD are both connected to an internal pull-up so that they normally remain HIGH. When pulled LOW by an external push button switch or a logic LOW level input, the wiper will be switched to the next adjacent tap position. Internal debounce circuitry prevents inadvertent switching of the wiper position if PU or PD remain LOW for less than 15ms, typical. Each of the buttons can be pushed either once for a single increment/decrement or continuously for a multiple increments/decrements. The number of increments/decrements of the wiper position depends on how long the button is being pushed. When making a continuous push, after the first second, the increment/decrement speed increases. For the first second, the device will be in the slow scan mode. Then, if the button is held for longer than 1 second, the device will go into the fast scan mode. As soon as the button is released, the ISL22512 will return to a standby condition. If two or more buttons are pressed simultaneously, all commands are ignored upon release of ALL buttons, except Shutdown Mode condition. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. AUTOSTORE The value of the counter is stored in EEPROM memory after 2 seconds of no activity on PU or PD inputs while ASE is enabled (held LOW). When power is restored, the content of the memory is recalled and the counter resets to the last value stored. If AUTOSTORE is to be implemented, ASE is typically hard wired to VSS. If ASE is held HIGH during power-up and then taken LOW, the wiper will not respond to the PU or PD inputs until ASE is brought HIGH and held HIGH. Manual (Push Button) Store When ASE is not enabled (held HIGH), a push button switch may be used to pull ASE LOW for more than 15ms and released to perform a manual store of the wiper position. During memory write cycle all inputs will be ignored. Page 9 of 13 ISL22512 Shutdown Mode The ISL22512 enters into Shutdown Mode if both PU and PD inputs are kept LOW for 2 seconds. In this mode, the resistors array is totally disconnected from its RH pin and the wiper is moved to position closest to RL pin, as shown in Figure 13. Note, that PU and PD inputs must be pulled LOW within tDB time window of 15ms, see “Shutdown Mode Timing” on page 6. Otherwise all command will be ignored till both inputs will be released. RH RW RL FIGURE 13. DCP CONNECTION IN SHUTDOWN MODE Holding either PU, PD or ASE input LOW for more than 15ms will exit shutdown mode and return wiper to prior shutdown position. If PU or PD will be held LOW for more than 250ms, the ISL22512 will start auto-increment or auto-decrement of wiper position. RTOTAL with VCC Removed The end- to-end resistance of the array will fluctuate once VCC is removed. FN6679 Rev 3.00 October 12, 2015 Page 10 of 13 ISL22512 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 10/12/15 FN6679.3 Updated the Ordering Information Table on page 2. Added About Intersil section. Updated the Package Outline Drawing M8.15 to the latest revision. Changes are as follows: -Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern. -Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Changed Note 1 “1982” to “1994” 07/06/09 FN6679.2 Added reliability information on page 1 under Features and EEPROM Specifications in DC Electrical Spec Table. Changed Tja for 8 LD SOIC from “120” to “125” Added Revision History 07/17/08 FN6679.1 1. Removed U option specs from table as there is no U option for this device. 2. Updated Pb-free note to new verbiage. 03/24/08 FN6679.0 Initial Release to web About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2008-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6679 Rev 3.00 October 12, 2015 Page 11 of 13 ISL22512 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6679 Rev 3.00 October 12, 2015 Page 12 of 13 ISL22512 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D 6 INDEX AREA 2X A L10.2.1x1.6A B N 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS E SYMBOL 0.10 C 1 2X 2 0.10 C TOP VIEW C A SEATING PLANE 1 MAX 0.55 - A1 - - 0.05 - 0.127 REF - b 0.15 0.20 0.25 5 D 2.05 2.10 2.15 - E 1.55 1.60 1.65 - A1 SIDE VIEW k 0.20 - - L 0.35 0.40 0.45 4xk 2 NX L N 0.50 BSC - NX b 2 Nd 4 3 Ne 1 3 0 12 - NOTES: 5 BOTTOM VIEW CL NX (b) (A1) L 5 e SECTION "C-C" TERMINAL TIP C C 4 Rev. 3 6/06 0.10 M C A B 0.05 M C 3 (ND-1) X e - 10  e - N (DATUM B) N-1 NOTES 0.50 e (DATUM A) PIN #1 ID NOMINAL 0.45 A3 0.10 C 0.05 C MIN A FOR ODD TERMINAL/SIDE b 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 2.50 1.75 0.05 MIN L 2.00 0.80 0.275 0.10 MIN DETAIL “A” PIN 1 ID 0.25 0.50 LAND PATTERN 10 FN6679 Rev 3.00 October 12, 2015 Page 13 of 13