ISL23345UFVZ

DATASHEET NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL23325 ISL23345 FN7872 Rev 0.00 June 21, 2011 Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) The ISL23345 is a volatile, low voltage, low noise, low power, 256 tap, quad digitally controlled potentiometer (DCP) with an I2C Bus™ interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. Features Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (128 tap position). • 10k 50kor 100k total resistance The low voltage, low power consumption, and small package of the ISL23345 make it an ideal choice for use in battery operated equipment. In addition, the ISL23345 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23345 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • Four potentiometers per package • 256 resistor taps • I2C serial interface - No additional level translator for low bus supply - Three address pins allow up to eight devices per bus • Maximum supply current without serial bus activity (standby) - 5µA @ VCC and VLOGIC = 5V - 2µA @ VCC and VLOGIC = 1.7V • Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply • Wiper resistance: 70 typical @ VCC = 3.3V Applications • Power-on preset to mid-scale (128 tap position) • Power supply margining • Extended industrial temperature range: -40°C to +125°C • Trimming sensor circuits • 20 Ld TSSOP or 20 QFN packages • Gain adjustment in battery powered instruments • Pb-free (RoHS compliant) • RF power amplifier bias compensation 10000 VREF RESISTANCE (Ω) 8000 RH1 6000 1 DCP of ISL23345 4000 RW1 VREF_M + ISL28114 2000 RL1 0 0 64 128 192 256 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP FN7872 Rev 0.00 June 21, 2011 FIGURE 2. VREF ADJUSTMENT Page 1 of 19 ISL23345 Block Diagram VLOGIC VCC RH0 SCL SDA LEVEL SHIFTER I/O BLOCK A0 A1 A2 POWER UP INTERFACE CONTROL AND STATUS LOGIC WR0 VOLATILE REGISTER RW0 WR1 VOLATILE REGISTER RW1 WR2 VOLATILE REGISTER RW2 WR3 VOLATILE REGISTER RW3 RL0 RH1 RL1 RH2 RL2 RH3 RL3 GND Pin Configurations Pin Descriptions ISL23345 (20 LD TSSOP) TOP VIEW RL0 1 20 RL3 RW0 2 19 RW3 TSSOP QFN SYMBOL DESCRIPTION 1 19 RL0 DCP0 “low” terminal 2 20 RW0 DCP0 wiper terminal 3 1 VCC Analog power supply. Range 1.7V to 5.5V VCC 3 18 RH3 RH0 4 17 RL2 4 2 RH0 DCP0 “high” terminal RL1 5 16 RW2 5 3 RL1 DCP1 “low” terminal RW1 6 15 RH2 6 4 RW1 DCP1 wiper terminal RH1 7 14 SCL GND 8 13 SDA 7 5 RH1 DCP1 “high” terminal VLOGIC 9 12 A2 8 6 GND Ground pin A0 10 11 A1 9 7 VLOGIC I2C bus /logic supply. Range 1.2V to 5.5V 10 8 A0 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 11 9 A1 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 12 10 A2 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 13 11 SDA Logic Pin - Serial bus data input/open drain output 14 12 SCL Logic Pin - Serial bus clock input RL0 RL3 RW3 20 19 18 17 VCC 1 6 16 RH3 RH0 2 15 RL2 RL1 3 14 RW2 RW1 4 13 RH2 15 13 RH2 DCP2 “high” terminal RH1 5 12 SCL 16 14 RW2 DCP2 wiper terminal GND 6 11 SDA 17 15 RL2 DCP2 “low” terminal 10 18 16 RH3 DCP3 “high” terminal A2 RW0 ISL23345 (20 LD QFN) TOP VIEW 19 17 RW3 DCP3 wiper terminal 20 18 RL3 DCP3 “low” terminal FN7872 Rev 0.00 June 21, 2011 9 A1 8 A0 VLOGIC 7 Page 2 of 19 ISL23345 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING RESISTANCE OPTION (k) TEMP RANGE (°C) -40 to +125 PACKAGE (Pb-free) 20 Ld TSSOP PKG. DWG. # ISL23345TFVZ 23345 TFVZ 100 MDP0044 ISL23345UFVZ 23345 UFVZ 50 -40 to +125 20 Ld TSSOP MDP0044 ISL23345WFVZ 23325 WFVZ 10 -40 to +125 20 Ld TSSOP MDP0044 ISL23345TFRZ 345T 100 -40 to +125 20 Ld 3x4 QFN L20.3x4 ISL23345UFRZ 345U 50 -40 to +125 20 Ld 3x4 QFN L20.3x4 ISL23345WFRZ 345W 10 -40 to +125 20 Ld 3x4 QFN L20.3x4 NOTES: 1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL23345. For more information on MSL please see techbrief TB363. FN7872 Rev 0.00 June 21, 2011 Page 3 of 19 ISL23345 Absolute Maximum Ratings Thermal Information Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper Current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 6kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 20 Ld TSSOP Package (Notes 4, 6) . . . . . . 85 33 20 Ld QFN Package (Notes 5, 7) . . . . . . . . 40 4 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For JC, the “case temp” location is taken at the package top center. 7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Analog Specifications SYMBOL RTOTAL VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN MAX (Note 20) TYP (Note 8) (Note 20) UNITS W option 10 k U option 50 k T option 100 k PARAMETER RH to RL Resistance TEST CONDITIONS RH to RL Resistance Tolerance End-to-End Temperature Coefficient VRH, VRL RW -20 ±2 +20 % W option 125 ppm/°C U option 65 ppm/°C T option 45 ppm/°C DCP Terminal Voltage VRH or VRL to GND 0 VCC V Wiper Resistance RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V 70 200  VCC = 1.7V 580  32/32/32 pF CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page 9 ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC Noise Resistor Noise Density Wiper at middle point, W option 16 nV Hz Wiper at middle point, U option 49 nV Hz Wiper at middle point, T option 61 nV Hz Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB Power Supply Reject Ratio -75 dB Feed Thru PSRR FN7872 Rev 0.00 June 21, 2011 Wiper output change if VCC change ±10%; wiper at middle point -0.4 < 0.1 0.4 µA Page 4 of 19 ISL23345 Analog Specifications SYMBOL VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER TEST CONDITIONS MIN MAX (Note 20) TYP (Note 8) (Note 20) UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 13) DNL (Note 12) Integral Non-linearity, Guaranteed Monotonic Differential Non-linearity, Guaranteed Monotonic W option -1.0 ±0.5 +1.0 LSB (Note 9) U, T option -0.5 ±0.15 +0.5 LSB (Note 9) -1 ±0.4 +1 LSB (Note 9) -0.4 ±0.1 +0.4 LSB (Note 9) W option -5 -2 0 LSB (Note 9) U, T option -2 -0.5 0 LSB (Note 9) W option 0 2 5 LSB (Note 9) U, T option 0 0.4 2 LSB (Note 9) -2 ±0.5 2 LSB (Note 9) W option U, T option FSerror (Note 11) ZSerror (Note 10) Full-scale Error Zero-scale Error Vmatch (Note 22) DCP to DCP Matching DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals TCV (Notes 14) Ratiometric Temperature Coefficient W option, Wiper Register set to 80 hex 8 ppm/°C U option, Wiper Register set to 80 hex 4 ppm/°C T option, Wiper Register set to 80 hex 2.3 ppm/°C Large Signal Wiper Settling Time From code 0 to FF hex, measured from 0 to 1LSB settling of the wiper 300 ns -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz tLS_Settling fcutoff RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL (Note 18) Integral Non-linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -2.0 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V Differential Non-linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -1.0 U, T option; VCC = 1.7V FN7872 Rev 0.00 June 21, 2011 ±0.3 -1 ±0.4 +1.0 ±0.15 ±0.35 MI (Note 15) MI (Note 15) +1 ±0.6 -0.5 MI (Note 15) MI (Note 15) 2.1 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V +2.0 10.5 U, T option; VCC = 1.7V RDNL (Note 17) ±1 MI (Note 15) MI (Note 15) +0.5 MI (Note 15) MI (Note 15) Page 5 of 19 ISL23345 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER Roffset (Note 16) Offset, Wiper at 0 Position TEST CONDITIONS W option; VCC = 2.7V to 5.5V MIN MAX (Note 20) TYP (Note 8) (Note 20) 0 3 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V 5.5 MI (Note 15) 6.3 0 0.5 U, T option; VCC = 1.7V MI (Note 15) 2 MI (Note 15) 1.1 MI (Note 15) Rmatch (Note 23) DCP to DCP Matching Any two DCPs at the same tap position with the same terminal voltages TCR (Note 19) Resistance Temperature Coefficient W option; Wiper register set between 32 hex and FF hex 170 ppm/°C U option; Wiper register set between 32 hex and FF hex 80 ppm/°C T option; Wiper register set between 32 hex and FF hex 50 ppm/°C Operating Specifications SYMBOL ILOGIC ICC ILOGIC SB -2 UNITS 2 VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. PARAMETER VLOGIC Supply Current (Write/Read) VCC Supply Current (Write/Read) VLOGIC Standby Current TEST CONDITIONS MIN MAX (Note 20) TYP (Note 8) (Note 20) UNITS VLOGIC = 5.5V, VCC = 5.5V, fSCL = 400 kHz (for I2C active read and write) 200 µA VLOGIC = 1.2V, VCC = 1.7V, fSCL = 400 kHz (for I2C active read and write) 5 µA VLOGIC = 5.5V, VCC = 5.5V 18 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA VLOGIC = VCC = 5.5V, I2C interface in standby 2 µA 0.5 µA 3 µA 1.5 µA 2 µA 0.5 µA 3 µA 1.5 µA 0.4 µA VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ILOGIC VLOGIC Shutdown Current SHDN VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ILkgDig Leakage Current, at Pins A0, A1, A2, SDA, SCL FN7872 Rev 0.00 June 21, 2011 LSB (Note 9) Voltage at pin from GND to VLOGIC -0.4 2V 0.05 x VLOGIC V VLOGIC < 2V 0.1 x VLOGIC V IOL = 3mA, VLOGIC > 2V 0 IOL = 1.5mA, VLOGIC < 2V Cpin SDA, SCL Pin Capacitance fSCL SCL Frequency tsp Pulse Width Suppression Time at SDA and SCL Inputs tAA 0.4 V 0.2 x VLOGIC V 10 pF 400 kHz Any pulse narrower than the max spec is suppressed 50 ns SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VLOGIC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VLOGIC crossing 600 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC 600 ns tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VLOGIC to SDA entering the 30% to 70% of VLOGIC window 0 ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC 600 ns tHD:STO STOP Condition Hold Time for Read From SDA rising edge to SCL falling edge; both or Write crossing 70% of VLOGIC 1300 ns FN7872 Rev 0.00 June 21, 2011 Page 7 of 19 ISL23345 Serial Interface Specification SYMBOL for SCL, SDA, A0, A1, A2 Unless Otherwise Noted. (Continued) PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS 0 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF tSU:A A1, A0, A2 Setup Time Before START condition 600 ns tHD:A A1, A0, A2 Hold Time After STOP condition 600 ns NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)255 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255 Max  V  RW  i  – Min  V  RW  i  for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper 10 6 TC V = ------------------------------------------------------------------------------  --------------------voltage and Min( ) is the minimum value of the wiper voltage over the temperature range. V  RW i  +25°C   +165°C 15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 14. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255. 6 for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the  Max  Ri  – Min  Ri   10 TC R = -------------------------------------------------------  --------------------- minimum value of the resistance over the temperature range. Ri  +25°C  +165°C 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 19. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. 22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 3 and y = 0 to 3. 23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255, x = 0 to 3 and y = 0 to 3. FN7872 Rev 0.00 June 21, 2011 Page 8 of 19 ISL23345 DCP Macro Model RTOTAL RH RL CH CL CW 32pF 32pF 32pF RW Timing Diagrams SDA vs SCL Timing tHIGH tF SCL tLOW tsp tR tSU:DAT tSU:STA SDA (INPUT TIMING) tHD:DAT tHD:STA tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1 and A2 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1, A2 FN7872 Rev 0.00 June 21, 2011 Page 9 of 19 ISL23345 0.4 0.12 0.2 0.06 DNL (LSB) DNL (LSB) Typical Performance Curves 0.0 -0.06 -0.2 -0.4 0.00 0 64 128 192 -0.12 256 0 64 TAP POSITION (DECIMAL) 0.2 0.06 INL (LSB) INL (LSB) 0.12 0.0 0.00 -0.06 -0.2 0 64 128 192 -0.12 256 0 64 TAP POSITION (DECIMAL) 128 192 256 TAP POSITION (DECIMAL) FIGURE 5. 10k INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50k INL vs TAP POSITION, VCC = 3.3V, +25°C 0.4 0.10 0.2 0.05 RDNL (MI) RDNL (MI) 256 FIGURE 4. 50k DNL vs TAP POSITION, VCC = 3.3V, +25°C 0.4 0.0 -0.2 -0.4 192 TAP POSITION (DECIMAL) FIGURE 3. 10k DNL vs TAP POSITION, VCC = 3.3V, +25°C -0.4 128 0.00 -0.05 0 64 128 192 256 TAP POSITION (DECIMAL) FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 3.3V, +25°C FN7872 Rev 0.00 June 21, 2011 -0.10 0 64 128 192 256 TAP POSITION (DECIMAL) FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 3.3V, +25°C Page 10 of 19 ISL23345 (Continued) 0.8 0.50 0.4 0.25 RINL (MI) RINL (MI) Typical Performance Curves 0.0 -0.4 0.00 -0.25 -0.8 -0.50 0 64 128 192 256 0 64 FIGURE 9. 10k RINL vs TAP POSITION, VCC = 3.3V, +25°C +25°C +125°C 80 WIPER RESISTANCE (Ω) WIPER RESISTANCE (Ω) 256 120 +125°C 60 40 -40°C 20 0 64 128 192 100 +25°C 80 60 40 -40°C 20 0 256 0 64 TAP POSITION (DECIMAL) 128 192 256 TAP POSITION (DECIMAL) FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 400 80 300 60 TCv (ppm/°C) TCv (ppm/°C) 192 FIGURE 10. 50k RINL vs TAP POSITION, VCC = 3.3V, +25°C 100 0 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 200 100 40 20 0 15 0 63 111 159 207 TAP POSITION (DECIMAL) FIGURE 13. 10k TCv vs TAP POSITION, VCC = 3.3V FN7872 Rev 0.00 June 21, 2011 255 15 63 111 159 207 255 TAP POSITION (DECIMAL) FIGURE 14. 50k TCv vs TAP POSITION, VCC = 3.3V Page 11 of 19 ISL23345 (Continued) 800 200 600 150 TCr (ppm/°C) TCr (ppm/°C) Typical Performance Curves 400 50 200 0 15 100 63 111 159 207 0 15 255 63 TAP POSITION (DECIMAL) 207 255 FIGURE 16. 50k TCr vs TAP POSITION, VCC = 3.3V 40 120 30 90 TCr (ppm/°C) TCv (ppm/°C) 159 TAP POSITION (DECIMAL) FIGURE 15. 10k TCr vs TAP POSITION 20 60 30 10 0 15 111 0 63 111 159 207 TAP POSITION (DECIMAL) FIGURE 17. 100k TCv vs TAP POSITION, VCC = 3.3V 255 15 63 111 159 207 255 TAP POSITION (DECIMAL) FIGURE 18. 100k TCr vs TAP POSITION, VCC = 3.3V CH1: 20mV/DIV, 2µs/DIV CH2: 2V/DIV, 2µs/DIV SCL CLOCK RW PIN WIPER SCL 9TH CLK OF THE DATA BYTE (ACK) CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH FN7872 Rev 0.00 June 21, 2011 FIGURE 20. WIPER TRANSITION GLITCH Page 12 of 19 ISL23345 Typical Performance Curves 1V/DIV 0.2µs/DIV (Continued) VCC 0.5V/DIV 20µs/DIV SCL SCL 9TH CLOCK OF THE DATA BYTE (ACK) WIPER WIPER FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.437MHz AT MIDDLE TAP FIGURE 23. 10k -3dB CUT OFF FREQUENCY 1.8 STANDBY CURRENT ICC (µA) CH1: RH TERMINAL CH2: RW TERMINAL FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE 1.6 1.4 1.2 1.0 VCC = 5.5V, VLOGIC = 5.5V 0.8 0.6 0.4 VCC = 1.7V, VLOGIC = 1.2V 0.2 0 -40 -15 10 35 60 Bus Interface Pins Potentiometers Pins SERIAL DATA INPUT/OUTPUT (SDA) The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals of the ISL23345 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWI RWi (i = 0, 1, 3) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. VCC Power terminal for the potentiometer section analog power source. Can be any value needed to support the voltage range of the DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. FN7872 Rev 0.00 June 21, 2011 110 FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions RHI AND RLI 85 TEMPERATURE (°C) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output. DEVICE ADDRESS (A2, A1, A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input Page 13 of 19 ISL23345 pins in order to initiate communication with the ISL23345. A maximum of eight ISL23345 devices may occupy the I2C serial bus (see Table 3). VLOGIC Digital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the I2C logic source. Principles of Operation The ISL23345 is an integrated circuit incorporating four DCPs with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any of the DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the I2C logic source, which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than the DCP analog supply. ISL23345 is shown in Table 1. The Wiper Register WRi at address i contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP ADDRESS (hex) VOLATILE REGISTER NAME DEFAULT SETTING (hex) 10 ACR 40 3 WR3 80 2 WR2 80 1 WR1 80 0 WR0 80 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 NAME/ VALUE 0 SHDN 0 0 0 0 0 0 Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e. DCP is forced to end-to-end open circuit and RW is connected to RL through a 2k serial resistor, as shown in Figure 25. The default value of the SHDN bit is 1. RH DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RW) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL23345 is being powered up, all the wipers (WRi) are reset to 80h (128 decimal), which positions RWi at the center between RLi and RHi. RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE When the device enters shutdown, all current DCP WRi settings are maintained. When the device exits shutdown, the wipers will return to the previous WRi settings after a short settling time (see Figure 26). In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the wipers will be RESET to their mid positions. This is done to avoid an undefined state at the wiper outputs. The WRi can be read or written to directly using the I2C serial interface as described in the following sections. Memory Description The ISL23345 contains five volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register WR3 and Access Control Register (ACR). The memory map of FN7872 Rev 0.00 June 21, 2011 Page 14 of 19 WIPER VOLTAGE, VRW (V) ISL23345 POWER-UP All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23345 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored during the power-up of the device. MID SCALE = 80H USER PROGRAMMED AFTER SHDN SHDN ACTIVATED SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE I2C Serial Interface The ISL23345 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23345 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23345, the SDA pin is in the input mode. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 27). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 28). The ISL23345 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL23345 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010 as the four MSBs, and the following three bits are matching the logic values present at pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3). TABLE 3. IDENTIFICATION BYTE FORMAT LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY 1 0 1 0 A2 (MSB) A1 A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS FN7872 Rev 0.00 June 21, 2011 Page 15 of 19 ISL23345 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 A2A1 A0 0 SIGNALS FROM THE SLAVE S T O P DATA BYTE 0 0 0 A C K A C K A C K FIGURE 29. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE 1 0 1 0 A2A1 A0 0 SIGNALS FROM THE SLAVE A C K S A T C O K P A C K 1 0 1 0 A2A1 A0 1 0 0 0 A C K READ S T A IDENTIFICATION R BYTE WITH T R/W = 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 30. READ SEQUENCE Write Operation Read Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23345 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 28 and 29). A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 30). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23345 responds with an ACK; then the ISL23345 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30). It is possible to perform a sequential Write to all DCP channels via a single Write operation. The command is initiated by sending an additional Data Byte after the first Data byte instead of sending a STOP condition. FN7872 Rev 0.00 June 21, 2011 Page 16 of 19 ISL23345 Applications Information Wiper Transition VLOGIC Requirements When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (