DATASHEET
ISL23418
FN7901
Rev 1.00
September 24, 2015
Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
The ISL23418 is a volatile, low voltage, low noise, low power,
SPI™ bus, 128 taps, single digitally controlled potentiometer
(DCP), which integrates DCP core, wiper switches, and control
logic on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
bus interface. The potentiometer has an associated volatile
Wiper Register (WR) that can be directly written to and read by
the user. The contents of the WR controls the position of the
wiper. When powered on, the ISL23418 wiper always
commences at mid-scale (64-tap position).
The low voltage, low power consumption, and small package
size of the ISL23418 make it an ideal choice for use in battery
operated equipment. The ISL23418 has a VLOGIC pin allowing
down to 1.2V bus operation, independent from the VCC value.
This allows for low logic levels to be connected directly to the
ISL23418 without passing through a voltage level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
Features
• 128 Resistor Taps
• SPI Serial Interface
- No Additional Level Translator for Low Bus Supply
- Daisy Chaining of Multiple DCP
• Wiper Resistance: 70 Typical @ VCC = 3.3V
• Shutdown Mode: Forces DCP into End-to-end Open Circuit;
RW Shorted to RL Internally
• Power-on Preset to Mid-scale (64-tap Position)
• Shutdown and Standby Current DCP2 --> ... --> DCP(N-1).
The write instruction is executed on the rising edge of CS for all N
DCPs simultaneously.
Keeping VLOGIC powered all the time during normal operation is
recommended. In cases in which turning VLOGIC OFF is
necessary, grounding the VLOGIC pin is recommended. Grounding
the VLOGIC pin or both VLOGIC and VCC does not affect other
devices on the same bus. It is good practice to put a 1µF capacitor
in parallel with a 0.1µF decoupling capacitor close to the VLOGIC pin.
Daisy Chain Read Operation
VCC Requirements and Placement
The read operation consists of two parts. First, the read
instructions (N two-byte operations) are sent with a valid address.
Second, the requested data is read while sending NOP
instructions (N two-byte operations), as shown in
Figures 31 and 32.
Putting a 1µF capacitor in parallel with a 0.1µF decoupling capacitor
close to the VCC pin is recommended.
VLOGIC Requirements
N DCP IN A CHAIN
CS
SCK
DCP0
MOSI
MISO
µC
DCP1
DCP2
CS
CS
CS
SCK
SCK
SCK
SDI
SDO
SDI
SDO
SDI
DCP(N-1)
CS
SCK
SDO
SDI
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
FN7901 Rev 1.00
September 24, 2015
Page 16 of 20
ISL23418
CS
SCK
16 CLKLS
WR
SDI
16 CLKS
16 CLKS
D C P2
SDO 0
WR
D C P1
WR
D C P0
WR
D C P2
WR
D C P1
WR
D C P2
SDO 1
SDO 2
FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 31. TWO-BYTE READ INSTRUCTION
CS
SCK
16 CLKS
SDI
RD DCP2
SDO
16 CLKS
RD DCP1
16 CLKS
16 CLKS
16 CLKS
16 CLKS
RD DCP0
NOP
NOP
NOP
DCP2 OUT
DCP1 OUT
DCP0 OUT
FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
FN7901 Rev 1.00
September 24, 2015
Page 17 of 20
ISL23418
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
September 24, 2015
FN7901.1
Updated the Ordering Information table on page 3.
Replaced Products section with About Intersil section.
Updated Package Outline Drawing M10.118 to the latest revision. Changes are as follows:
-Updated to new POD template. Added land pattern
August 3, 2011
FN7901.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2011-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7901 Rev 1.00
September 24, 2015
Page 18 of 20
ISL23418
Package Outline Drawing
M10.118
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 4/12
5
3.0±0.05
A
DETAIL "X"
D
10
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
0.50 BSC
B
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.18 - 0.27
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to JEDEC MO-187-BA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.50)
(0.29)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN7901 Rev 1.00
September 24, 2015
Page 19 of 20
ISL23418
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
8.
PIN 1
INDEX AREA
2.10
A
B
PIN #1 ID
1
0.05 MIN.
1
8.
4
4X 0.20 MIN.
1.60
0.10 MIN.
10
5
0.80
10X 0.40
0.10
6
9
2X
6X 0.50
10 X 0.20 4
TOP VIEW
0.10 M C A B
M C
BOTTOM VIEW
(10 X 0.20)
SEE DETAIL "X"
(0.05 MIN)
PACKAGE
OUTLINE
1
MAX. 0.55
0.10 C
(10X 0.60)
C
(0.10 MIN.)
(2.00)
SEATING PLANE
0.08 C
SIDE VIEW
(0.80)
(1.30)
C
0 . 125 REF
(6X 0.50 )
(2.50)
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
FN7901 Rev 1.00
September 24, 2015
1.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2.
All Dimensions are in millimeters. Angles are in degrees.
Dimensions in ( ) for Reference Only.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Maximum package warpage is 0.05mm.
6.
Maximum allowable burrs is 0.076mm in all directions.
7.
Same as JEDEC MO-255UABD except:
No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm
Lead Length dim. = 0.45mm max. not 0.42mm.
8.
The configuration of the pin #1 identifier is optional, but must be located within
the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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