ISL23448WFVZ

DATASHEET NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL23428 ISL23448 FN7905 Rev 0.00 August 19, 2011 Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) The ISL23448 is a volatile, low voltage, low noise, low power, 128 tap, quad digitally controlled potentiometer (DCP) with an SPI Bus™ interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. Features Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (64 tap position). • SPI serial interface - No additional level translator for low bus supply - Daisy Chaining of multiple DCPs The low voltage, low power consumption, and small package of the ISL23448 make it an ideal choice for use in battery operated equipment. In addition, the ISL23448 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23448 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • Four potentiometers per package • 128 resistor taps • 10kΩ 50kΩor 100kΩ total resistance • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V SPI bus/logic power supply • Maximum supply current without serial bus activity (standby) - 5µA @ VCC and VLOGIC = 5V - 2µA @ VCC and VLOGIC = 1.7V • Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Wiper resistance: 70Ω typical @ VCC = 3.3V • Power-on preset to mid-scale (64 tap position) Applications • Extended industrial temperature range: -40°C to +125°C • Power supply margining • 20 Ld TSSOP or 20 Ld QFN packages • Trimming sensor circuits • Pb-free (RoHS compliant) • Gain adjustment in battery powered instruments • RF power amplifier bias compensation 10000 VREF RESISTANCE (Ω) 8000 6000 RH1 - 4000 1 DCP OF ISL23448 RW1 2000 VREF_M + ISL28114 RL1 0 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP FN7905 Rev 0.00 August 19, 2011 FIGURE 2. VREF ADJUSTMENT Page 1 of 21 ISL23448 Block Diagram VLOGIC VCC RH0 SDI SDO I/O BLOCK SCK LEVEL SHIFTER CS POWER UP INTERFACE CONTROL AND STATUS LOGIC WR0 VOLATILE REGISTER RW0 WR1 VOLATILE REGISTER RW1 WR2 VOLATILE REGISTER RW2 WR3 VOLATILE REGISTER RW3 RL0 RH1 RL1 RH2 RL2 RH3 RL3 GND Pin Configurations Pin Descriptions ISL23448 (20 LD TSSOP) TOP VIEW RL0 1 20 RL3 RW0 2 19 RW3 VCC 3 18 RH3 RH0 4 17 RL2 RL1 5 16 RW2 RW1 6 15 RH2 TSSOP QFN SYMBOL DESCRIPTION 1 19 RL0 DCP0 “low” terminal 2 20 RW0 DCP0 wiper terminal 3 1 VCC Analog power supply. Range 1.7V to 5.5V 4 2 RH0 DCP0 “high” terminal 5 3 RL1 DCP1 “low” terminal RH1 7 14 SCK 6 4 RW1 DCP1 wiper terminal GND 8 13 SDO 7 5 RH1 DCP1 “high” terminal VLOGIC 9 12 GND 8, 12 6, 10 GND Ground pin 9 7 VLOGIC 10 8 SDI Logic Pin - Serial bus data input 11 9 CS Logic Pin - Active low chip select 11 SDO Logic Pin - Serial bus data output (configurable) 12 SCK Logic Pin - Serial bus clock input SDI 10 11 CS ISL23448 (20 LD QFN) RW0 RL0 RL3 RW3 TOP VIEW 13 20 19 18 17 14 SPI bus/logic supply Range 1.2V to 5.5V 15 13 RH2 DCP2 “high” terminal RH0 2 15 RL2 16 14 RW2 DCP2 wiper terminal RL1 3 14 RW2 17 15 RL2 DCP2 “low” terminal RW1 4 13 RH2 18 16 RH3 DCP3 “high” terminal RH1 5 12 SCK 19 17 RW3 DCP3 wiper terminal GND 6 11 SDO 20 18 RL3 DCP3 “low” terminal FN7905 Rev 0.00 August 19, 2011 7 8 9 10 GND RH3 CS 6 16 SDI 1 VLOGIC VCC Page 2 of 21 ISL23448 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING RESISTANCE OPTION (kΩ) TEMP RANGE (°C) -40 to +125 PACKAGE (Pb-free) 20 Ld TSSOP PKG. DWG. # ISL23448TFVZ 23448 TFVZ 100 M20.173 ISL23448UFVZ 23448 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173 ISL23448WFVZ 23448 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173 ISL23448TFRZ 448T 100 -40 to +125 20 Ld 3x4 QFN L20.3x4 ISL23448UFRZ 448U 50 -40 to +125 20 Ld 3x4 QFN L20.3x4 ISL23448WFRZ 448W 10 -40 to +125 20 Ld 3x4 QFN L20.3x4 NOTES: 1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL23448. For more information on MSL please see techbrief TB363. FN7905 Rev 0.00 August 19, 2011 Page 3 of 21 ISL23448 Absolute Maximum Ratings Thermal Information Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper Current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 6kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 20 Ld TSSOP Package (Notes 4, 7) . . . . . . 85 33 20 Ld QFN Package (Notes 5, 6) . . . . . . . . 40 4 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For JC, the “case temp” location is taken at the package top center. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL RTOTAL PARAMETER RH to RL Resistance TEST CONDITIONS W option VRH, VRL RW TYP (Note 8) MAX (Note 20) 10 UNITS kΩ U option 50 kΩ T option 100 kΩ RH to RL Resistance Tolerance End-to-End Temperature Coefficient MIN (Note 20) -20 ±2 +20 % W option 125 ppm/°C U option 65 ppm/°C T option 45 ppm/°C DCP Terminal Voltage VRH or VRL to GND Wiper Resistance RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V 70 VCC = 1.7V 580 Ω 32/32/32 pF CH/CL/CW Terminal Capacitance 0 See “DCP Macro Model” on page 8 VCC V 200 Ω ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point PSRR Power Supply Reject Ratio FN7905 Rev 0.00 August 19, 2011 Wiper output change if VCC change ±10%; wiper at middle point -0.4 < 0.1 0.4 µA 61 nV/√Hz -65 dB -75 dB Page 4 of 21 ISL23448 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN (Note 20) TYP (Note 8) MAX (Note 20) W option -0.5 ±0.15 +1.0 LSB (Note 9) U, T option -0.5 ±0.15 +0.5 LSB (Note 9) W option -0.5 ±0.15 +0.5 LSB (Note 9) U, T option -0.5 ±0.15 +0.5 LSB (Note 9) -3 -1.5 0 LSB (Note 9) -1.5 -0.9 0 LSB (Note 9) W option 0 1.5 3 LSB (Note 9) U, T option 0 0.9 1.5 LSB (Note 9) Vmatch DCP to DCP Matching (Note 22) DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals -2 ±0.5 2 LSB (Note 9) TCV Ratiometric Temperature Coefficient (Note 14) W option, Wiper Register set to 40 hex 8 ppm/°C U option, Wiper Register set to 40 hex 4 ppm/°C T option, Wiper Register set to 40 hex 2.3 ppm/°C From code 0 to 7F hex, measured from 0 to 1LSB settling of the wiper 300 ns Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz SYMBOL PARAMETER TEST CONDITIONS UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity, Guaranteed (Note 13) Monotonic DNL Differential Non-linearity, Guaranteed (Note 12) Monotonic FSerror Full-scale Error (Note 11) W option U, T option ZSerror Zero-scale Error (Note 10) tLS_Settling Large Signal Wiper Settling Time fcutoff -3dB Cutoff Frequency RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-linearity, Guaranteed (Note 18) Monotonic W option; VCC = 2.7V to 5.5V -1.0 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V W option; VCC = 2.7V to 5.5V -0.5 U, T option; VCC = 1.7V FN7905 Rev 0.00 August 19, 2011 ±0.15 -0.5 ±0.15 +0.5 ±0.15 ±0.4 MI (Note 15) MI (Note 15) +0.5 ±0.4 -0.5 MI (Note 15) MI (Note 15) 1 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V +1.0 4 U, T option; VCC = 1.7V RDNL Differential Non-linearity, Guaranteed (Note 17) Monotonic ±0.5 MI (Note 15) MI (Note 15) +0.5 MI (Note 15) MI (Note 15) Page 5 of 21 ISL23448 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER Roffset Offset, wiper at 0 position (Note 16) TEST CONDITIONS W option; VCC = 2.7V to 5.5V MIN (Note 20) TYP (Note 8) MAX (Note 20) 0 1.8 3 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V MI (Note 15) 3 0 U, T option; VCC = 1.7V 0.3 MI (Note 15) 1 MI (Note 15) 0.5 -2 ±0.5 UNITS MI (Note 15) Rmatch DCP to DCP Matching (Note 23) Any two DCPs at the same tap position with the same terminal voltages 2 LSB (Note 9) TCR Resistance Temperature Coefficient (Note 19) W option; Wiper register set between 19 hex and 7F hex 170 ppm/°C U option; Wiper register set between 19 hex and 7F hex 80 ppm/°C T option; Wiper register set between 19 hex and 7F hex 50 ppm/°C Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL ILOGIC ICC ILOGIC SB PARAMETER VLOGIC Supply Current (Write/Read) VCC Supply Current (Write/Read) VLOGIC Standby Current TEST CONDITIONS MIN (Note 20) TYP (Note 8) VLOGIC = 5.5V, VCC = 5.5V, fSCK = 5MHz (for SPI active read and write) 1.5 mA VLOGIC = 1.2V, VCC = 1.7V, fSCK = 1MHz (for SPI active read and write) 30 µA VLOGIC = 5.5V, VCC = 5.5V 110 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA VLOGIC = VCC = 5.5V, SPI interface in standby 2 µA 0.5 µA 3 µA 1.5 µA 2 µA 0.5 µA 3 µA 1.5 µA 0.4 µA VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ILOGIC SHDN VLOGIC Shutdown Current VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ILkgDig Leakage Current, at Pins CS, SDO, SDI, SCK FN7905 Rev 0.00 August 19, 2011 MAX (Note 20) UNITS Voltage at pin from GND to VLOGIC -0.4 2V 0.05 x VLOGIC VLOGIC < 2V 0.1 x VLOGIC IOL = 3mA, VLOGIC > 2V V 0 IOL = 1.5mA, VLOGIC < 2V Rpu SDO Pull-up Resistor Off-chip Cpin SCK, SDO, SDI, CS Pin Capacitance fSCK SCK Frequency Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 0.4 V 0.2 x VLOGIC V 1.5 kΩ 10 pF VLOGIC = 1.7V to 5.5V 5 MHz VLOGIC = 1.2V to 1.6V 1 MHz tCYC SPI Clock Cycle Time VLOGIC ≥ 1.7V 200 ns tWH SPI Clock High Time VLOGIC ≥ 1.7V 100 ns tWL SPI Clock Low Time VLOGIC ≥ 1.7V 100 ns tLEAD Lead Time VLOGIC ≥ 1.7V 250 ns tLAG Lag Time VLOGIC ≥ 1.7V 250 ns tSU SDI, SCK and CS Input Setup Time VLOGIC ≥ 1.7V 50 ns tH SDI, SCK and CS Input Hold Time VLOGIC ≥ 1.7V 50 ns tRI SDI, SCK and CS Input Rise Time VLOGIC ≥ 1.7V 10 ns tFI SDI, SCK and CS Input Fall Time VLOGIC ≥ 1.7V 10 20 ns tDIS SDO Output Disable Time VLOGIC ≥ 1.7V 0 100 ns tSO SDO Output Setup Time VLOGIC ≥ 1.7V 50 ns tV SDO Output Valid Time VLOGIC ≥ 1.7V 150 ns tHO SDO Output Hold Time VLOGIC ≥ 1.7V 0 ns tRO SDO Output Rise Time Rpu = 1.5k, Cbus = 30pF FN7905 Rev 0.00 August 19, 2011 60 Page 7 of 21 ns ISL23448 Serial Interface Specification SYMBOL For SCK, SDI, SDO, CS unless otherwise noted. (Continued) PARAMETER tFO SDO Output Fall Time tCS CS Deselect Time MIN (Note 20) TEST CONDITIONS Rpu = 1.5k, Cbus = 30pF TYP (Note 8) MAX (Note 20) UNITS 60 ns 2 µs NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)127 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 Max  V  RW  i  – Min  V  RW  i  10 6 for i = 8 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage TC V = ------------------------------------------------------------------------------  --------------------V  RW i  +25°C   +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 14. 15. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 6 for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the  Max  Ri  – Min  Ri   10 TC R = -------------------------------------------------------  --------------------Ri  +25°C  +165°C minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 19. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. 22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. 23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. DCP Macro Model RTOTAL RH CH CL CW 32pF RL 32pF 32pF RW FN7905 Rev 0.00 August 19, 2011 Page 8 of 21 ISL23448 Timing Diagrams Input Timing tCS CS SCK tSU tH ... tWH tWL tRI tFI ... MSB SDI tLAG tCYC tLEAD LSB SDO Output Timing CS SCK ... tSO tHO tDIS ... MSB SDO LSB tV SDI ADDR XDCP™ Timing (For All Load Instructions) CS tDCP SCK SDI ... MSB ... LSB VW SDO FN7905 Rev 0.00 August 19, 2011 *When CS is HIGH SDO at Z or Hi-Z state Page 9 of 21 ISL23448 0.12 0.04 0.06 0.02 DNL (LSB) DNL (LSB) Typical Performance Curves 0.00 -0.06 -0.12 0.00 -0.02 0 32 64 96 -0.04 128 0 32 TAP POSITION (DECIMAL) 0.16 0.16 0.08 0.12 0.00 0.08 0.04 -0.08 -0.16 0 32 64 96 0.00 128 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.12 0.04 0.06 0.02 RDNL (MI) RDNL (MI) TAP POSITION (DECIMAL) 0.00 0.00 -0.02 -0.06 -0.12 128 FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C INL (LSB) INL (LSB) FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C 64 96 TAP POSITION (DECIMAL) 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FN7905 Rev 0.00 August 19, 2011 -0.04 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C Page 10 of 21 ISL23448 (Continued) 0.4 0.08 0.3 0.04 RINL (MI) RINL (MI) Typical Performance Curves 0.2 0.1 0.0 0.00 -0.04 0 32 64 96 -0.08 128 0 32 TAP POSITION (DECIMAL) FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C WIPER RESISTANCE (Ω) WIPER RESISTANCE (Ω) +125°C +25°C 60 40 -40°C 20 0 32 64 96 80 60 40 -40°C 20 0 128 +125°C +25°C 100 0 32 TAP POSITION (DECIMAL) 64 96 128 TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 200 40 150 30 TCv (ppm/°C) TCv (ppm/°C) 128 120 80 100 50 0 96 FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 100 0 64 TAP POSITION (DECIMAL) 20 10 15 43 71 99 TAP POSITION (DECIMAL) FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V FN7905 Rev 0.00 August 19, 2011 127 0 15 43 71 99 127 TAP POSITION (DECIMAL) FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V Page 11 of 21 ISL23448 Typical Performance Curves (Continued) 400 100 80 TCr (ppm/°C) TCr (ppm/°C) 300 200 100 0 40 20 15 43 71 99 TAP POSITION (DECIMAL) 0 15 127 FIGURE 15. 10kΩ TCr vs TAP POSITION 43 71 99 TAP POSITION (DECIMAL) 127 FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V 100 20 80 TCr (ppm/°C) 15 TCv (ppm/°C) 60 10 5 60 40 20 0 15 43 71 99 TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V 127 0 15 43 71 99 127 TAP POSITION (DECIMAL) FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V CH1: 20mV/DIV, 2µs/DIV CH2: 2V/DIV, 2µs/DIV SCK CLOCK WIPER CS RISING RW PIN CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH FN7905 Rev 0.00 August 19, 2011 FIGURE 20. WIPER TRANSITION GLITCH Page 12 of 21 ISL23448 Typical Performance Curves (Continued) 1V/DIV 0.2µs/DIV VCC 0.5V/DIV 20µs/DIV CS WIPER WIPER FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME 1.8 STANDBY CURRENT ICC (µA) CH1: RH TERMINAL CH2: RW TERMINAL FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE 1.6 1.4 1.2 1.0 VCC = 5.5V, VLOGIC = 5.5V 0.8 0.6 0.4 VCC = 1.7V, VLOGIC = 1.2V 0.2 0 -40 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.437MHz AT MIDDLE TAP -15 Power Pins Potentiometers Pins VCC RWI RWi (i = 0, 1, 2, 3) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. FN7905 Rev 0.00 August 19, 2011 60 85 110 FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals of the ISL23448 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. 35 TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY RHI AND RLI 10 Power terminal for the potentiometer section analog power source. Can be any value needed to support the voltage range of the DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. Bus Interface Pins SERIAL CLOCK (SCK) This input is the serial clock of the SPI serial interface. SERIAL DATA INPUT (SDI) The SDI is a serial data input pin for SPI interface. It receives operation code, wiper address and data from the SPI remote host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. Page 13 of 21 ISL23448 SERIAL DATA OUTPUT (SDO) The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. The output type is configured through ACR[1] bit for Push-Pull or Open Drain operation. The default setting for this pin is Push-Pull. An external pull-up resistor is required for Open Drain output operation. When CS is HIGH, the SDO pin is in tri-state (Z) or high-tri-state (Hi-Z) depending on the selected configuration. CHIP SELECT (CS) CS LOW enables the ISL23448, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power-up. When CS is HIGH, the ISL23448 is deselected and the SDO pin is at high impedance, and the device will be in the standby state. VLOGIC Digital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the SPI logic source. Principles of Operation The ISL23448 is an integrated circuit incorporating four DCPs with its associated registers and an SPI serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any of the DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the SPI logic source, which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than the DCP analog supply. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WR of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RLi to the position closest FN7905 Rev 0.00 August 19, 2011 to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL23448 is being powered up, all the WRi are reset to 40h (64 decimal), which positions RWi at the center between RLi and RHi. The WRi can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL23448 contains five volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register WR3 and Access Control Register (ACR). The memory map of ISL23448 is shown in Table 1. The Wiper Register WRi at address i, contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP ADDRESS (hex) VOLATILE REGISTER NAME DEFAULT SETTING (hex) 10 ACR 40 3 WR3 40 2 WR2 40 1 WR1 40 0 WR0 40 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 NAME/ VALUE 0 SHDN 0 0 0 0 SDO 0 The SDO bit (ACR[1]) configures the type of SDO output pin. The default value of SDO bit is 0 for Push-Pull output. The SDO pin can be configured as Open Drain output for some applications. In this case, an external pull-up resistor is required. Reference the “Serial Interface Specification” on page 7. Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., each DCP is forced to end-to-end open circuit and each RW shorted to RL through a 2kΩ serial resistor, as shown in Figure 25. The default value of the SHDN bit is 1. RH RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE Page 14 of 21 ISL23448 When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). WIPER VOLTAGE, VRW (V) In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2 to 0.4µs the wipers will be RESET to their mid position. This is done to avoid an undefined state at the wiper outputs. Protocol Conventions The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL23448 is the Data Byte. TABLE 3. INSTRUCTION BYTE FORMAT BIT # 7 6 5 4 3 2 1 0 I2 I1 I0 R4 R3 R2 R1 R0 Table 4 contains a valid instruction set for ISL23448. POWER-UP If the [R4:R0] bits are zero, one, two or three then the read or write is to the WRi register. If the [R4:R0] are 10000, then the operation is to the ACR. MID SCALE = 40H USER PROGRAMMED AFTER SHDN SHDN ACTIVATED SHDN RELEASED Write Operation WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE SPI Serial Interface The ISL23448 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL23448. The SCK and CS lines are controlled by the host or master. The ISL23448 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. A write operation to the ISL23448 is a two or more bytes operation. First, it requires that the CS transition from HIGH-to-LOW. Then, the host sends a valid Instruction Byte, followed by one or more Data Bytes to the SDI pin. The host terminates the write operation by pulling the CS pin from LOW-to-HIGH. Instruction is executed on the rising edge of CS (see Figure 27). Read Operation A Read operation to the ISL23448 is a four byte operation. First, it requires that the CS transition from HIGH-to-LOW. Then, the host sends a valid Instruction Byte, followed by a “dummy” Data Byte, NOP Instruction Byte and another “dummy” Data Byte to the SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from the SDO pin on the rising edge of SCK during the third and fourth bytes, respectively. The host terminates the read by pulling the CS pin from LOW-to-HIGH (see Figure 28). TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRTE 1 0 0 R4 R3 R2 R1 R0 WRi or ACR READ 1 1 0 R4 R3 R2 R1 R0 WRi or ACR WRTE Where X means “do not care”. FN7905 Rev 0.00 August 19, 2011 Page 15 of 21 ISL23448 CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK WR INSTRUCTION SDI DATA BYTE ADDR SDO FIGURE 27. TWO BYTE WRITE SEQUENCE CS 1 8 16 24 32 SCK SDI RD NOP ADDR RD SDO ADDR READ DATA FIGURE 28. FOUR BYTE READ SEQUENCE Applications Information Daisy Chain Write Operation Communicating with ISL23448 The write operation starts by a HIGH-to-LOW transition on the CS line, followed by N number of two bytes write instructions on the SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown in Figure 30, where N is a number of DCPs in chain. The serial data is going through DCPs from DCP0 to DCP(N-1) as follows: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. Communication with ISL23448 proceeds using SPI interface through the ACR (address 10000b), WR0 (addresses 00000b), WR1 (addresses 00001b), WR2 (addresses 00010b), WR3 (addresses 00011b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position. Daisy Chain Configuration When an application needs more than one ISL23448, it can communicate with all of them without additional CS lines by daisy chaining the DCPs, as shown in Figure 29. In Daisy Chain configuration, the SDO pin of the previous chip is connected to the SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of SCK and CS pins of microcontroller; for larger number of SPI devices, buffering of SCK and CS lines is required. FN7905 Rev 0.00 August 19, 2011 Daisy Chain Read Operation The read operation consists of two parts: first, send the read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation), as shown in Figures 31 and 32. The first part starts by a HIGH-to-LOW transition on the CS line, followed by N two bytes read instruction on the SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by a LOW-to-HIGH transition on the CS line. The read instructions are executed during the second part of the read sequence. It also starts by a HIGH-to-LOW transition on the CS line, followed by N number of two bytes NOP instructions on the SDI line and LOW-to-HIGH transition of CS. The data is read on every even byte during the second part of the read sequence while every odd byte contains code 111b followed by the address from which the data is being read. Page 16 of 21 ISL23448 Wiper Transition VLOGIC Requirements When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (