ISL26325FVZ

DATASHEET ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 12-Bit, 250kSPS Low-Power ADCs with Single-Ended and Differential Inputs and Multiple Input Channels The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 family of sampling SAR-type ADCs feature excellent linearity over supply and temperature variations, and offer versions with 1-, 2-, 4- and 8-channel single-ended inputs, and 1-, 2- and 4-channel differential inputs. A proprietary input multiplexer and combination buffer amplifier reduces the input drive requirements, resulting in lower cost and reduced board space. Specified measurement accuracy is maintained with input signals up to VDD. Members of the The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 family of Low-Power ADCs offer pinout intercompatibility, differing only in the analog inputs, to support quick replication of proven layouts across multiple design platforms. The serial digital interface is SPI compatible and is easily interfaced to popular FPGAs and microcontrollers. Power consumption is limited to 15mW at a sampling rate of 250kSPS, and an operating current of just 8µA typical between conversions, when configured for Auto Power-down mode. FN8273 Rev 1.00 September 5, 2013 Features • Pin-compatible family allows easy design upgrades • Excellent differential non-linearity (0.7LSB max) • Low THD: -86dB (typ) • Simple SPI-compatible serial digital interface • Low 3mA operating current • Power-down current between conversions 8µA (typ) • +5.25V to +2.7V supply • Excellent ESD survivability: 5kV HBM, 350V MM, 2kV CDM Applications • Industrial process control • Energy measurement • Multichannel data acquisition systems • Pressure sensors • Flow controllers The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 feature up to 5kV Human Body Model ESD survivability and are available in the popular SOIC and TSSOP packages. Performance is specified for operation over the full industrial temperature range (-40°C to +125°C). VDD VREF BUFFER ANALOG INPUTS DIFFERENTIAL/ SINGLE-ENDED MUX CNV ADC SPI SCLK SDO SDI OSC POR GND FIGURE 1. FUNCTIONAL BLOCK DIAGRAM FN8273 Rev 1.00 September 5, 2013 Page 1 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Application Block Diagram I2 C Bus RTC ANALOG SIGNAL INPUT MODULEs MUX and ADC Pressure/Strain Gage Sensor VREF RS-485 Precision Amps Gain Amplifiers DCP +V Precision Amps Precision Amps -V -V RTC VREF POWER Voltage Supervisor & Sequencers V Temperature Sensor LDO’s DCP System Power Thermistor +V Precision Amps -V Thermocouple +V Precision Amps Active Filters V Precision Amps Filters -V ISO-Thermal Block LDO Switching Controller Switching Regulators -V +V Active -V Core & I/O Power Switching Regulator +V Precision Amps Master μC RS-485 μC ADC M U X Active Filters +V VREF RS-232 Actuators +V Motors Control loops Buffer, Filters, Span Drivers +V Precision Amps Precision Amps -V -V M U X +V High Voltage Input Rail ~24V DAC VREF ANALOG SIGNAL OUTPUT MODULE Flow Sensor Single Ended Controller -V Loop Supply Gain Amplifiers Differential Pressure Transducer w/ ¥ Extractor +V Iout 4 -20mA Vin Active Filters Isolator +V Precision Amps Precision Amps -V -V Isolated Power Pin-Compatible Family RESOLUTION (Bits) SPEED (kHz) ANALOG INPUT INPUT CHANNELS ISL26310 12 125 Differential 1 ISL26311 12 125 Single-Ended 1 ISL26312 12 125 Differential 2 ISL26313 12 125 Single-Ended 2 ISL26314 12 125 Differential 4 ISL26315 12 125 Single-Ended 4 ISL26319 12 125 Single-Ended 8 ISL26320 12 250 Differential 1 ISL26321 12 250 Single-Ended 1 ISL26322 12 250 Differential 2 ISL26323 12 250 Single-Ended 2 ISL26324 12 250 Differential 4 ISL26325 12 250 Single-Ended 4 ISL26329 12 250 Single-Ended 8 MODEL FN8273 Rev 1.00 September 5, 2013 Page 2 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Ordering Information DESCRIPTION PART NUMBER (Notes 1, 2, 3) PART MARKING RESOLUTION (Bits) SPEED (kHz) INPUT (SE/DIFF) INPUT CHANNELS TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG DWG # ISL26320FBZ 26320 FBZ 12 250 Diff 1 -40 to +125 8 Ld SOIC M8.15 ISL26321FBZ 26321 FBZ 12 250 SE 1 -40 to +125 8 Ld SOIC M8.15 ISL26322FVZ 26322 FVZ 12 250 Diff 2 -40 to +125 16 Ld TSSOP M16.173 ISL26323FBZ 26323 FBZ 12 250 SE 2 -40 to +125 8 Ld SOIC M8.15 ISL26324FVZ 26324 FVZ 12 250 Diff 4 -40 to +125 16 Ld TSSOP M16.173 ISL26325FVZ 26325 FVZ 12 250 SE 4 -40 to +125 16 Ld TSSOP M16.173 ISL26329FVZ 26329 FVZ 12 250 SE 8 -40 to +125 16 Ld TSSOP M16.173 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329. For more information on MSL please see techbrief TB363. FN8273 Rev 1.00 September 5, 2013 Page 3 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Pin Configurations ISL26321 (8 LD SOIC) TOP VIEW ISL26320 (8 LD SOIC) TOP VIEW VDD 1 8 CNV VDD 1 8 CNV GND 2 7 SCLK GND 2 7 SCLK AIN+ 3 6 SDO VREF 3 6 SDO AIN- 4 5 SDI AIN0 4 5 SDI ISL26323 (8 LD SOIC) TOP VIEW VDD 1 8 CNV GND 2 7 SCLK AIN0 3 6 SDO AIN1 4 5 SDI ISL26324 (16 LD TSSOP) TOP VIEW ISL26322 (16 LD TSSOP) TOP VIEW VDD 1 16 CNV VDD 1 16 CNV GND 2 15 S C LK GND 2 15 SCLK V R EF 3 14 SDO VREF 3 14 SDO GND 4 13 SDI GND 4 13 SDI A IN0+ 5 12 NC AIN0+ 5 12 AIN3+ A IN 0- 6 11 NC AIN0- 6 11 AIN3- A IN 1+ 7 10 NC AIN1+ 7 10 AIN2+ A IN 1- 8 9 NC AIN1- 8 9 AIN2- ISL26329 (16 LD TSSOP) TOP VIEW ISL26325 (16 LD TSSOP) TOP VIEW VDD 1 16 CNV VDD 1 16 CNV G ND 2 15 SCLK GND 2 15 SCLK VREF 3 14 SDO VREF 3 14 SDO G ND 4 13 SDI GND 4 13 SDI AIN0 5 12 AIN3 AIN0 5 12 AIN7 NC 6 11 NC AIN1 6 11 AIN6 AIN1 7 10 AIN2 AIN2 7 10 AIN5 NC 8 9 NC AIN3 8 9 AIN4 FN8273 Rev 1.00 September 5, 2013 Page 4 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Pin Descriptions PIN NUMBER PIN NAME ISL26320 ISL26321 ISL26322 ISL26323 ISL26324 ISL26325 ISL26329 DESCRIPTION VDD 1 1 1 1 1 1 1 GND 2 2 2, 4 2 2, 4 2, 4 2, 4 VREF - 3 3 - 3 3 3 Reference Voltage Input AIN0+ - - 5 - 5 - - Differential Analog Input, Positive AIN0- - - 6 - 6 - - Differential Analog Input, Negative AIN1+ - - 7 - 7 - - Differential Analog Input, Positive AIN1- - - 8 - 8 - - Differential Analog Input, Negative AIN2+ - - - - 10 - - Differential Analog Input, Positive AIN2- - - - - 9 - - Differential Analog Input, Negative AIN3+ - - - - 12 - - Differential Analog Input, Positive AIN3- - - - - 11 - - Differential Analog Input, Negative AIN0 - 4 - 3 - 5 5 Single-Ended Analog Input AIN1 - - - 4 - 7 6 Single-Ended Analog Input AIN2 - - - - - 10 7 Single-Ended Analog Input AIN3 - - - - - 12 8 Single-Ended Analog Input AIN4 - - - - - - 9 Single-Ended Analog Input AIN5 - - - - - - 10 Single-Ended Analog Input AIN6 - - - - - - 11 Single-Ended Analog Input AIN7 - - - - - - 12 Single-Ended Analog Input SDI 5 5 13 5 13 13 13 Serial Interface Data Input SDO 6 6 14 6 14 14 14 Serial Interface Data Output SCLK 7 7 15 7 15 15 15 Serial Interface Clock Input CNV 8 8 16 8 16 16 16 Conversion Control Input NC - - 9, 10, 11, 12 - - 6, 8, 9, 11 - No Connect AIN+ 3 - - - - - - Differential Analog Input, Positive AIN- 4 - - - - - - Differential Analog Input, Negative FN8273 Rev 1.00 September 5, 2013 Positive Supply Voltage Ground Page 5 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Absolute Maximum Ratings Thermal Information AIN+, AIN-, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 to VDD + 0.3V Digital Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 to VDD + 0.3V VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 to + 0.3V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . .5000V Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . . 350V Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . 2000V Latch-up (Tested per JESD-78B; Class 2, Level A). . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 8 Ld SOIC (Notes 4, 5) . . . . . . . . . . . . . . . . . 98 48 16 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 92 29 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to +5.25V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER TEST LEVEL OR NOTES MIN (Note 6) TYP MAX (Note 6) UNITS ANALOG INPUTS Number of Input Channels Input Voltage Range Common Mode Input Voltage Range ISL26320, ISL26321 1 ISL26322 2 ISL26323 2 ISL26324, ISL26325 4 ISL26329 8 Differential Inputs (AINX+ - AINX-) is -VREF (Min) and +VREF (Max) 0 VREF V AINX, Single-Ended Inputs 0 VREF V VREF/2 + 0.2 V Differential Inputs VREF/2 – 0.2 Average Input Current CIN Input Capacitance Channel-Channel Crosstalk fIN = 100kHz VIN = FS, other channels = 0V VREF/2 2.5 µA 4 pF -86 dB VOLTAGE REFERENCE VREFEX External Reference Input Voltage Range IREFIN Average Input Current CREFIN Effective Input Capacitance 2 2.5 VDD V 200 220 µA 10 pF DC ACCURACY Resolution (No Missing Codes) 12 DNL Differential Nonlinearity Error -0.7 +0.7 LSB INL Integral Nonlinearity Error -0.7 +0.7 LSB Gain Error -6 6 LSB Gain Error Matching -2 2 LSB Offset Error -6 6 LSB FN8273 Rev 1.00 September 5, 2013 Bits Page 6 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER TEST LEVEL OR NOTES Offset Error Matching PSRR MIN (Note 6) TYP -2 Power Supply Rejection Ratio MAX (Note 6) UNITS 2 LSB 70 dB 73.4 dB DYNAMIC PERFORMANCE Signal-to-Noise Notes: VIN = FS - 0.1dB, fIN = 10kHz Differential Inputs Single-Ended Inputs 73.4 dB SINAD Signal-to-Noise + Distortion Notes: VIN = FS - 0.1dB, fIN = 10kHz Differential Inputs 73.1 dB Single-Ended Inputs 73.1 dB THD Total Harmonic Distortion Notes: VIN = FS - 0.1dB, fIN = 10kHz Differential Inputs -86 dB Single-Ended Inputs -86 dB Spurious-free Dynamic Range Notes: VIN = FS - 0.1dB fIN = 20kHz 96 dB SNR SFDR BW -3dB Input Bandwidth 2.5 MHz tAD Sampling Aperture Delay 12 ns tjit Sampling Aperture Jitter 25 ps POWER SUPPLY REQUIREMENTS VDD Supply Voltage IDD Supply Current PD Power Consumption IPD Istby 2.7 5.25 V 3 3.5 mA Normal Operation 15 17.5 mW Power-down Current Auto Power-Down Mode 8 50 µA Standby Mode Current Auto Sleep Mode 0.4 mA DIGITAL INPUTS VIH 0.7 VDD V VIL 0.2 VDD VOH IOH = -1mA VOL IOL = 1mA IIH, IIL Input Leakage Current VDD-0.4 V V -100 Serial Clock Frequency 0.2 VDD V 100 nA 20 MHz TIMING SPECIFICATIONS (Note 7) tSCLK SCLK Period (in RAC Mode) 50 tSCLK SCLK Period (in RSC, RDC Modes) 50 tDATA Safe Data Transfer Time After Conversion State Begins tCSB_SCLK CSB Falling Low to SCLK Rising Edge ns 100 ns 1.6 µs 40 ns tSDI_SU SDI Setup Time with Respect to Positive Edge of SCLK 10 ns tSDI_H SDI Hold Time with Respect to Positive Edge of SCLK 10 ns tSDO_V SDOUT Valid Time with Respect to Negative Edge of SCLK tSDOZ_D SDOUT to High Impedance State After CNV (Note 8) Rising Edge (or last SCLK falling edge) tACQ Acquisition Time when Fully Powered Up FN8273 Rev 1.00 September 5, 2013 25 85 400 ns ns ns Page 7 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER TEST LEVEL OR NOTES MIN (Note 6) TYP MAX (Note 6) UNITS tACQ Acquisition Time in Auto Sleep Mode 1.7 µs tACQ Acquisition time in Auto Power Down Mode 150 µs tSCLKH SCLK High Time 20 ns tSCLKL SCLK Low Time 20 ns tCNV CNV Pulse Width 100 ns NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. The device may become nonresponsive if the minimum acquisition times are not met in their respective modes, requiring a power cycle to restore normal operation. 8. Transition time to high impedance state is dominated by RC loading on the SDOUT pin. Specified value is measured using equivalent loading shown in Figure 2. VDD RL 2k OUTPUT PIN CL 10pF FIGURE 2. EQUIVALENT LOAD CIRCUIT FOR DIGITAL OUTPUT TESTING FN8273 Rev 1.00 September 5, 2013 Page 8 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Typical Performance Characteristics TA = +25°C, VDD = 5V, VREF = 5V, fSAMPLE = 250kHz, fSCLK = 20MHz, 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0.25 INL (LSBs) DNL (LSBs) unless otherwise specified. 0 -0.25 0 -0.25 -0.50 -0.50 -0.75 -0.75 -1.00 -2000 -1000 0 1000 2000 -1.00 -2000 -1000 0 FIGURE 3. DIFFERENTIAL NONLINEARITY (DNL) vs CODE 1.0 0.8 POSITIVE DNL 0.6 0.6 0.4 0.4 0.2 0.2 INL DNL 0.8 0.0 -0.2 -0.4 -0.4 -0.6 POSITIVE INL 0.0 -0.2 -0.6 NEGATIVE DNL -0.8 -20 0 20 40 60 80 100 NEGATIVE INL -0.8 -1.0 -40 120 -20 0 20 TEMPERATURE (°C) 0.0 80 100 120 2.7V -0.1 1.5 -0.2 1.0 OFFSET ERROR (LSB) GAIN ERROR (LSB) 60 FIGURE 6. INL DISTRIBUTION vs TEMPERATURE 2.0 0.5 2.7V 3.3V -0.5 -1.0 -20 0 20 5.25V -0.4 3.3V 5.0V 5.25V -0.5 -0.6 -0.7 40 60 -0.9 80 100 120 TEMPERATURE (°C) FIGURE 7. GAIN ERROR vs SUPPLY VOLTAGE AND TEMPERATURE FN8273 Rev 1.00 September 5, 2013 -0.3 -0.8 5.0V -1.5 -2.0 -40 40 TEMPERATURE (°C) FIGURE 5. DNL DISTRIBUTION vs TEMPERATURE 0.0 2000 FIGURE 4. INTEGRAL NONLINEARITY (INL) vs CODE 1.0 -1.0 -40 1000 CODE CODE -1.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 8. OFFSET ERROR vs SUPPLY VOLTAGE AND TEMPERATURE Page 9 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Typical Performance Characteristics unless otherwise specified. (Continued) 25 4.0 3.5 SUPPLY CURRENT (mA) 20 APERTURE DELAY (ns) TA = +25°C, VDD = 5V, VREF = 5V, fSAMPLE = 250kHz, fSCLK = 20MHz, 15 10 5 3.0 5.25V 5.0V 2.5 2.0 1.5 1.0 3.3V 2.7V 0.5 0 2.7 3.2 3.7 4.2 4.7 0.0 -40 5.2 -20 0 SUPPLY VOLTAGE FIGURE 9. APERTURE DELAY vs SUPPLY VOLTAGE 20 40 60 TEMPERATURE (°C) 80 100 120 FIGURE 10. SUPPLY CURRENT vs VOLTAGE AND TEMPERATURE 2.5 50 45 SHUTDOWN CURRENT (µA) SUPPLY CURRENT (mA) 2.0 1.5 NORMAL MODE AUTO POWER DOWN MODE 1.0 AUTO SLEEP MODE 0.5 40 35 5.25V 30 25 5.0V 20 15 3.3V 10 5 0.0 100 1k 10k SAMPLE RATE (Sps) 0 -40 100k FIGURE 11. SUPPLY CURRENT vs SAMPLING RATE (VDD = 5V) -20 0 20 40 60 TEMPERATURE (°C) 80 100 120 FIGURE 12. SHUTDOWN CURRENTS vs VOLTAGE AND TEMPERATURE -80 75 5.25V 5.0V 74 -82 73 -84 THD (dB) SNR/SINAD (dB) 2.7V 72 5.25V 5.0V -86 3.3V 2.7V -88 71 70 -40 2.7V -20 0 20 40 60 TEMPERATURE (°C) 80 100 120 FIGURE 13. SNR AND SINAD vs SUPPLY VOLTAGE AND TEMPERATURE FN8273 Rev 1.00 September 5, 2013 -90 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 3.3V 100 FIGURE 14. THD vs SUPPLY VOLTAGE AND TEMPERATURE Page 10 of 23 120 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Typical Performance Characteristics TA = +25°C, VDD = 5V, VREF = 5V, fSAMPLE = 250kHz, fSCLK = 20MHz, unless otherwise specified. (Continued) 0 75 -10 SNR -20 -30 SINAD THD (dB) SNR/SINAD (dB) 70 65 -40 -50 -60 -70 60 -80 -90 55 100 1k 10k 100k INPUT FREQUENCY (Hz) -100 100 1M 1k FIGURE 15. SNR AND SINAD vs INPUT FREQUENCY 1M FIGURE 16. THD vs INPUT FREQUENCY 70,000 0 SNR = 73.6dB THD = -87.6dB SINAD = 73.4dB SFDR = 89.1dB ENOB = 11.4 -20 -40 60,000 65,536 CODES 50,000 -60 HITS AMPLITUDE (dB) 10k 100k INPUT FREQUENCY (Hz) -80 40,000 30,000 -100 20,000 -120 10,000 -140 -160 0 25000 50000 75000 FREQUENCY (Hz) FIGURE 17. SINGLE-TONE FFT FN8273 Rev 1.00 September 5, 2013 100000 125000 0 0 CODES -3 -2 -1 0 CODES 0 1 2 3 CODE FIGURE 18. SHORTED INPUT HISTOGRAM Page 11 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Circuit Description The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 families of 12-bit ADCs are low-power Successive Approximation-type (SAR) ADCs with 1-, 2-, 4-, or 8-channels and a choice of single-ended or differential inputs. The high-impedance buffered input simplifies interfacing to sensors and external circuitry. The entire ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 families follow the same base pinout and differs only in the analog input pins, allowing the user to replicate the basic board layout across multiple platforms with a minimum redesign effort. The simple serial digital interface is compatible with popular FPGAs and microcontrollers and allows direct conversion control by the CNV pin. Functional Description The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 devices are SAR (Successive Approximation Register) analog-to-digital converters that use capacitor-based charge redistribution as their conversion method. These devices include an on-chip power-on reset (POR) circuit to initialize the internal digital logic when power is applied. An on-chip oscillator provides the master clock for the conversion logic. The CNV signal controls when the converter enters into its signal acquisition time (CNV = 0), and when it begins the conversion sequence after the signal has been captured (CNV = 1). The converters include a configuration register that can be accessed via the serial port. The configuration register has various bits to indicate which channel (where applicable) is selected, to activate the auto-power-down feature where the ADC is shut down between conversions, or to output the configuration register contents along with the data conversion word whenever a conversion word is read from the serial port. The serial port The ISL26320, the ISL26322, and the ISL26324 feature differential inputs with output data coding in two's complement format (see Table 1). The size of one LSB in these devices is (2*VREF)/4096. Figure 21 illustrates the ideal transfer function for these devices. The ISL26321, ISL26323, ISL26325, and ISL26329 feature single-ended inputs with output coding in binary format (see Table 2). The size of one LSB in these devices is VREF/4096. Figure 22 illustrates the ideal transfer function for these devices. BUFFER ACQ ACQ VCM ACQ CNV VREF COMPARATOR CNV ACQ AIN CNV SAR LOGIC CS BUFFER ACQ CS ACQ CNV VCM ACQ CNV CNV FIGURE 19. ARCHITECTURAL BLOCK DIAGRAM, DIFFERENTIAL INPUT FN8273 Rev 1.00 September 5, 2013 DAC CNV CS COMPARATOR SAR LOGIC CS DAC ACQ AIN– ADC Transfer Function VREF DAC CNV AIN+ Figures 19 and 20 illustrate simplified representations of the converter analog section for differential and single-ended inputs, respectively. During the acquisition phase (CNV = 0) the input signal is presented to the Cs samples capacitors. To properly sample the signal, the CNV signal must remain low for the specified time. When CNV is taken high (CNV = 1), the switches that connect the sampling capacitors to the input are opened and the control logic begins the successive approximation sequence to convert the captured signal into a digital word. The conversion sequence timing is determined by the on-chip oscillator. DAC VREF supports three different modes of reading the conversion data. These will be discussed later in this data sheet. FIGURE 20. ARCHITECTURAL BLOCK DIAGRAM, SINGLE-ENDED Page 12 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 1LSB = 2•V REF/4096 1LSB = V REF/4096 111...111 011...110 111...110 000...001 100...001 ADC CODE ADC CODE 011...111 000...000 111...111 100...000 011...111 100...010 000...010 100...001 000...001 100...000 000...000 –V REF + ½LSB 0V +V REF +V REF – 1½LSB – 1LSB 0 = + ½LSB ANALOG INPUT AIN+ – (AIN–) ANALOG INPUT FIGURE 21. IDEAL TRANSFER CHARACTERISTICS, DIFFERENTIAL INPUT FIGURE 22. IDEAL TRANSFER CHARACTERISTICS, SINGLE-ENDED INPUT Analog Inputs V Some members of the ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 family feature a fully differential input with a nominal full-scale range equal to twice the applied VREF voltage. Those devices with differential inputs have a nominal full scale range equal to twice the applied VREF voltage. Each input swings VREF volts (peak-to-peak), 180° out of phase from one another for a total differential input of 2*VREF (refer to Figures 23 and 24). VREF (P-P) 5.0 4.0 AIN– 3.0 VREF (P-P) 2.5Vp-p ALLOWABLE VCM RANGE 1.0 t AIN+ AIN- AIN+ 2.0 VREF = 2.5V V ISL2631X/32X VCM FS = +VREF-1LSB 5.0 AIN– 5Vp-p AIN+ 4.0 FIGURE 23. DIFFERENTIAL INPUT SIGNALING VCM 3.0 Differential signaling offers several benefits over a single-ended input, such as: • Doubling of the full-scale input range (and therefore the dynamic range) • Improved even order harmonic distortion • Better noise immunity due to common mode rejection Figure 24 shows the relationship between the reference voltage and the full-scale differential input range for two different values of VREF. Note that the common-mode input voltage must be maintained within ±200mV of VREF/2 for differential inputs. ALLOWABLE VCM RANGE 2.0 1.0 t VREF = 5V FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE FOR DIFFERENTIAL INPUTS Those devices with singled-ended inputs have a ground-referenced peak-to-peak input voltage span equal to the reference voltage. FN8273 Rev 1.00 September 5, 2013 Page 13 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Voltage Reference Input V 5.0 4.0 3.0 2.5Vp-p AIN 2.0 1.0 t VREF = 2.5V Figures 27 and 28 illustrate possible voltage reference options for these ADCs. Figure 27 uses the precision ISL21090 voltage reference, which exhibits exceptionally low drift and low noise. The ISL21090 must be powered from a supply greater than 4.7V. V 5Vp-p 5.0 An external reference voltage must be supplied to theVREF pin to set the full-scale input range of the converter. The VREF input on these devices can accept voltages ranging from 2V (nominal) to VDD, however, they are specified with VREF at a voltage of 5V with VDD at 5V. Note that exceeding VDD by more than 100mV can forward bias the ESD protection diodes and degrade measurement accuracy due to leakage current. A lower value voltage reference must be used if the device is operated with VDD at voltages lower than 5V. If the VREF pin is tied to the VDD pin, the VREF pin should be decoupled with a local 1µF ceramic capacitor as described in a later paragraph. AIN 4.0 Figure 28 illustrates the ISL21010 voltage reference used with these ADCs. The ISL21010 series voltage references have higher noise and drift than the ISL21090 devices, but operate at lower supply voltages. Therefore, these devices can readily be used when these SAR ADCs operate with VDD at voltages less than 5V. 3.0 2.0 1.0 t VREF = 5V FIGURE 25. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE FOR SINGLE-ENDED INPUTS Input Multiplexer The input of the multiplexer connects the selected analog input pins to the ADC input. A proprietary sampling circuit significantly reduces the input drive requirements, resulting in lower overall cost and board space in addition to improved performance. Note that the input capacitance is only 2-3pF during the Sampling phase, changing to 40pF during the Settling phase, resulting in an average input current of 2.5µA and an effective input capacitance of only 4pF (see Figure 26). AC ERROR INPUT VOLTAGE TOTAL DC ERROR ERROR SETTLING ERROR AND NOISE OFFSET ERROR The outputs of ISL21090 or the ISL21010 devices should be decoupled with a 1µF ceramic capacitor. A 1µF, 6.3 V, X7R, 0603 (1608 metric) MLCC type capacitor is recommended for its high frequency performance. The trace length from the VREF pin to this capacitor and the voltage reference output should be as short as possible. The ISL26320 and ISL26323 devices (packaged in 8 pin SOIC packages) derive their voltage reference from the VDD pin. To achieve best performance, the VDD pin of these devices should be bypassed with the 1µF ceramic capacitor mentioned above. Power-Down/Standby Modes In order to reduce power consumption between conversions, a number of user-selectable modes can be utilized by setting the appropriate bits in the Configuration Register. Auto Power-down (PD0 = 0) reduces power consumption by shutting down all portions of the device except the oscillator and digital interface after completion of a conversion. There is a short recovery period after CNV is asserted Low (150µs with external reference). In Auto Sleep mode (PD1 = 1), the device will automatically enter the low-power Sleep mode at the end of the current conversion. Recovery from this mode involves only 2.1µs and may offer an alternative to Power-down mode in some applications. Output Data Format SAMPLING PHASE ETTING PHASE FIGURE 26. INPUT SAMPLING OPERATION The converter output word is delivered in two’s complement format in differential input mode, and straight binary in single-ended input mode of operation respectively, all MSB-first. Input exceeding the specified full-scale voltage results in a clipped output which will not return to in-range values until after the input signal has returned to the specified allowable voltage range. Data must be read prior to the completion of the current conversion to avoid conflict and loss of data, due to overwriting of the new conversion data into the output register. FN8273 Rev 1.00 September 5, 2013 Page 14 of 23 ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 5V + BULK 0.1µF 0.1µF 1 DNC DNC 8 2 VIN DNC 7 3 COMP VOUT 6 4 GND 5 TRIM ISL2631X ISL2632X 2.5V VDD VREF 1µF (SEE VOLTAGE REFERENCE INPUT) ISL21090 FIGURE 27. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY +2.7V TO +3.6V OR +5V + VIN 1 VOUT 2 GND 3 BULK 0.1µF 0.1µF ISL2631X VDD ISL2632X VREF 1.25, 2.048 OR 2.5V 1µF (SEE VOLTAGE REFERENCE INPUT) ISL21010 FIGURE 28. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY +2.7V TO +5V BULK 1µF (SEE VOLTAGE REFERENCE INPUT) ISL26320 ISL26323 VDD FIGURE 29. VOLTAGE REFERENCE FOR ISL26320/ISL26323 IS DERIVED FROM VDD TABLE 1. OUTPUT CODES - DIFFERENTIAL Input Voltage Two’s Complement (12-bit) >(VFS-1.5 LSB) 7FF VFS-1.5 LSB 7FF ... 7FE -0.5 LSB -VFS +0.5 LSB 000 … FFF 801 … 800 NOTE: VFS in the table above equals the voltage between AIN+ and AIN-. Differential full scale is equal to 2* VREF. FN8273 Rev 1.00 September 5, 2013 TABLE 2. OUTPUT CODES - SINGLE-ENDED Input Voltage Binary (12 bit) >AIN-1.5 LSB FFF AIN-1.5 LSB FFF … FFE 0.5 LSB 001 … 000