DATASHEET
ISL267450
FN8341
Rev 0.00
August 10, 2012
12-Bit, 1MSPS SAR ADCs
The ISL267450 is a 12-bit, 1MSPS sampling SAR-type ADC
with a differential input span of 2*VREF volts. The ISL267450
features excellent linearity over supply and temperature
variations and is drop-in compatible with the AD7450. The
device can operate from a supply voltage of either 5V or 3V
and maintain measurement accuracy with input signals up to
the supply rails.
Features
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Power
dissipation is 9.0mW at a sampling rate of 1MSPS, and just
5µW between conversions utilizing Auto Power-Down mode
(with a 3V supply).
• 1MHz Sampling Rate
• Drop-in Compatible with AD7450
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 3V or 5V Operation
• Low Operating Current
- 1.25mA at 833kSPS with 3V Supplies
- 1.7mA at 1MSPS with 5V Supplies
The ISL267450 is available in 8 Ld SOIC or MSOP packages,
and are specified for operation over the Industrial temperature
range (–40°C to +85°C).
• Power-down Current between Conversions: 1µA
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOIC and MSOP Packages
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
Block Diagram
+VDD
VIN+
VIN-
VREF
ADC
SERIAL
INTERFACE
SCLK
SDATA
CS
GND
FN8341 Rev 0.00
August 10, 2012
Page 1 of 19
ISL267450
Typical Connection Diagram
VREF
0.1µF
0.1µF
VREF
VDD
VREF(P-P)
VIN+
SCLK
VREF(P-P)
VIN–
SDATA
+
10µF
+3V/5V
SUPPLY
µP/µC
CS
GND
SERIAL
INTERFACE
Pin Configuration
ISL267450
(8 LD SOIC, MSOP)
TOP VIEW
VREF
1
8
VDD
VIN+
2
7
SCLK
VIN-
3
6
SDATA
GND 4
5
CS
Pin Description
ISL267450
PIN NAME
PIN NUMBER
VDD
8
Supply voltage, +2.7V to 5.25V.
SCLK
7
Serial clock input. Controls digital I/O timing and clocks the conversion.
SDATA
6
Digital conversion output.
CS
5
Chip select input. Controls the start of a conversion when going low.
GND
4
Ground
VIN–
3
Negative analog input.
VIN+
2
Positive analog input.
VREF
1
Reference voltage.
FN8341 Rev 0.00
August 10, 2012
DESCRIPTION
Page 2 of 19
ISL267450
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(PB-free)
PKG.
DWG. #
ISL267450IBZ
267450 IBZ
2.7 to 5.25
-40 to +85
8 Ld SOIC
M8.15
ISL267450IUZ
67450
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL267450. For more information on MSL please see techbrief TB363.
FN8341 Rev 0.00
August 10, 2012
Page 3 of 19
ISL267450
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Converter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal-to-(Noise + Distortion) Ratio (SINAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Integral Nonlinearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8341 Rev 0.00
August 10, 2012
Page 4 of 19
ISL267450
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld SOIC Package (Notes 4, 5). . . . . . . . . .
120
64
8 Ld MSOP Package (Notes 4, 5). . . . . . . . .
165
64
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VDD = +4.75V to
+5.25V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
DYNAMIC PERFORMANCE
SINAD
THD
SFDR
IMD
Signal-to (Noise + Distortion) Ratio
VDD = 5V
70
dB
VDD = 3V
67
dB
Total Harmonic
Distortion
VDD = 5V
-80
-75
dB
VDD = 3V
-78
-73
dB
Spurious Free Dynamic Range
VDD = 5V
-82
-75
dB
VDD = 3V
-80
-73
dB
2nd Order Terms
–89
dB
3rd Order Terms
-85
dB
Intermodulation Distortion
tpd
Aperture Delay
10
ns
tpd
Aperture Jitter
50
ps
3dB
Full Power Bandwidth
@ –3dB
20
MHz
@ –0.1dB
2.5
MHz
-87
dB
PSRR
Power Supply Rejection Ratio
DC ACCURACY
N
Resolution
12
INL
Integral Nonlinearity
-1
1
LSB
DNL
Differential Nonlinearity
Guaranteed no missed codes to 12 bits
-0.95
0.95
LSB
Zero-Code Error
VDD = 5V
-3
3
LSB
VDD = 3V
-6
6
LSB
VDD = 5V
-3
3
LSB
VDD = 3V
-6
6
LSB
VDD = 5V
-3
3
LSB
VDD = 3V
-6
6
LSB
OFFSET
GAIN
Positive Gain Error
Negative Gain Error
FN8341 Rev 0.00
August 10, 2012
Bits
Page 5 of 19
ISL267450
Electrical Specifications VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VDD = +4.75V to
+5.25V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
ANALOG INPUT (Note 7)
|AIN|
VIN+, VIN–
Full-Scale Input Span
2 x VREF
Absolute Input Voltage Range
VCM = VREF
VIN+ - VIN–
V
V
VIN+
VCM ±
VREF/2
V
VIN–
VCM ±
VREF/2
V
ILEAK
Input Leakage Current
CVIN
Input Capacitance
-1
1
µA
Track Mode
12
pF
Hold Mode
6
pF
VDD = 5V (±1% tolerance for specified
performance)
2.5
V
VDD = 3V (±1% tolerance for specified
performance)
1.25
V
REFERENCE INPUT
VREF
VREF Input Voltage Range
ILEAK
DC Leakage Current
CVREF
VREF Input Capacitance
-1
1
19
A
pF
LOGIC INPUTS
VIH
Input High Voltage
VIL
Input Low Voltage
ILEAK
CIN
2.4
Input Leakage Current
V
-1
Input Capacitance
0.8
V
1
µA
10
pF
LOGIC OUTPUTS
VOH
Output High Voltage
ISOURCE = 200µA
VOL
Output Low Voltage
ISINK = 200µA
ILEAK
Floating-State Leakage Current
COUT
Floating-State Output Capacitance
VDD - 0.3
V
-1
Output Coding
0.4
V
1
µA
10
pF
Two’s Complement
CONVERSION RATE
tCONV
Conversion Time
888ns with FSCLK = 18MHz
16
SCLK Cycles
1.07µs with FSCLK = 15MHz
16
SCLK Cycles
tACQ
Acquisition Time (Note 8)
Sine Wave Input
200
ns
Fmax
Throughput Rate
VDD = 5V
1
MSPS
VDD = 3V
833
kSPS
POWER REQUIREMENTS
VDD
Positive Supply Voltage Range
FN8341 Rev 0.00
August 10, 2012
3.3V ± 10%
3.0
3.6
V
5V ± 5%
4.75
5.25
V
Page 6 of 19
ISL267450
Electrical Specifications VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VDD = +4.75V to
+5.25V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
IDD
PD
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
1
µA
Positive Supply Input Current
Static
VDD = 3V/5V; SCLK ON or OFF
Dynamic
VDD = 5V; fS = 1MSPS
1.7
mA
VDD = 3V; fS = 833kSPS
1.25
mA
5
µW
Power Dissipation
Static Mode
VDD = 3V/5V; SCLK ON or OFF
Dynamic
VDD = 5V; fS = 1MSPS
8.5
mW
VDD = 3V; fS = 833kSPS
3.75
mW
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must not exceed VDD.
8. Read about “Acquisition Time” on page 14 for a discussion of this parameter.
Electrical Specifications Limits established by characterization and are not production tested. VDD = +4.75V to +5.25V,
FSCLK = 18MHz, FS = 1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
fSCLK
Clock Frequency
tSCLK
Clock Period
tCONVERT
tQUIET
tCSS
tDISABLE
TEST CONDITIONS
MIN
(Note 6)
TYP
0.05
MAX
(Note 6)
UNITS
18
MHz
55
Conversion Time
ns
16 x tSCLK
888
ns
Quiet Time Before Sample
25
ns
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish
10
35
ns
Data Access Time after SCLK Falling Edge
tSWH
SCLK High Pulsewidth
0.4 x tSCLK
0.6 x tSCLK
ns
tSWL
SCLK Low Pulsewidth
0.4 x tSCLK
0.6 x tSCLK
ns
40
ns
tCLKDV
SCLK Falling Edge to SDATA Valid
tSDH
SCLK Falling Edge to SDATA Hold
tACQ
Acquisition Time (Note 8)
tCSW
CS Pulse Width
tCDV
CS Falling Edge to SDATA Valid
10
ns
ns
10
ns
20
ns
Electrical Specifications Limits established by characterization and are not production tested. VDD = +3.0V to +3.3V, FSCLK = 15MHz,
FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VREF = 2.5V; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
fSCLK
Clock Frequency
tSCLK
Clock Period
tCONVERT
Conversion Time
FN8341 Rev 0.00
August 10, 2012
TEST CONDITIONS
MIN
(Note 6)
0.05
TYP
MAX
(Note 6)
UNITS
15
MHz
55
16 x tSCLK
ns
1.07
µs
Page 7 of 19
ISL267450
Electrical Specifications Limits established by characterization and are not production tested. VDD = +3.0V to +3.3V, FSCLK = 15MHz,
FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VREF = 2.5V; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
tQUIET
tCSS
tDISABLE
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Quiet Time Before Sample
25
ns
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish
10
35
µs
tSWH
SCLK High Pulsewidth
0.4 x tSCLK
0.6 x tSCLK
ns
tSWL
SCLK Low Pulsewidth
0.4 x tSCLK
0.6 x tSCLK
ns
40
ns
tCLKDV
SCLK Falling Edge to SDATA Valid
tSDH
SCLK Falling Edge to SDATA Hold
tACQ
Acquisition Time (Note 8)
tCSW
CS Pulse Width
tCDV
CS Falling Edge to SDATA Valid
10
ns
ns
10
ns
20
ns
NOTE:
9. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 2 on page 8) and the equivalent timing using the
AD7450 loading (50pF) is calculated.
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85k
OUTPUT
PIN
CL
10 pF
FIGURE 2. EQUIVALENT LOAD CIRCUIT
FN8341 Rev 0.00
August 10, 2012
Page 8 of 19
ISL267450
Typical Performance Characteristics
0
-40
-60
-80
-100
-120
-140
-160
8192-POINT FFT
fSAMPLE = 833kSPS
fIN = 300kHz
SINAD = 69.83dB
THD = -82.02dB
SFDR = 82.93dB
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
0
8192-POINT FFT
fSAMPLE = 1MSPS
fIN = 300kHz
SINAD = 71.55dB
THD = -80.88dB
SFDR = 84.08dB
-40
-60
-80
-100
-120
-140
0
100
200
300
400
-160
500
0
100
FREQUENCY (kHz)
200
300
400
FREQUENCY (kHz)
FIGURE 3. DYNAMIC PERFORMANCE AT 1MSPS WITH VDD = 5V
FIGURE 4. DYNAMIC PERFORMANCE AT 833KSPS WITH VDD = 3V
1.0
74
0.8
72
0.6
0.4
68
2.7V
DNL (LSB)
SINAD (dBc)
70
3.3V
66
4.75V
0.0
-0.2
-0.4
5.25V
64
0.2
-0.6
62
-0.8
60
10
100
-1.0
1k
0
1024
TEST FREQUENCY (Hz)
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
-0.2
0.0
-0.4
-0.6
-0.6
-0.8
-0.8
1024
2048
CODE
3072
FIGURE 7. TYPICAL DNL FOR VDD = 3V
FN8341 Rev 0.00
August 10, 2012
4096
-0.2
-0.4
0
3072
FIGURE 6. TYPICAL DNL FOR VDD = 5V
INL (LSB)
DNL (LSB)
FIGURE 5. SINAD vs ANALOG FREQUENCY FROM VARIOUS SUPPLY
VOLTAGES
-1.0
2048
CODE
4096
-1.0
0
1024
2048
3072
4096
CODE
FIGURE 8. TYPICAL INL FOR VDD = 5V
Page 9 of 19
ISL267450
Typical Performance Characteristics
(Continued)
1.0
3.0
0.8
2.5
0.6
2.0
1.5
0.2
DNL (LSB)
INL (LSB)
0.4
0.0
-0.2
1.0
POS DNL
0.5
0.0
-0.4
-0.6
-0.5
-0.8
-1.0
-1.0
0
1024
2048
3072
NEG DNL
-1.5
0.0
4096
0.5
1.0
CODE
3.0
1.5
2.0
1.0
POS DNL
INL (LSB)
DNL (LSB)
1.0
0.5
0.0
3.5
0.0
NEG INL
NEG DNL
-2.0
0.5
1.0
1.5
2.0
-3.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VREF (V)
VREF (V)
FIGURE 11. CHANGE IN DNL vs VREF FOR VDD = 3.3V
FIGURE 12. CHANGE IN INL vs VREF FOR VDD = 5V
2.5
1.0
2.0
0.0
3.3V VDD
-1.0
1.5
-2.0
1.0
POS INL
ZCE (LSB)
INL (LSB)
3.0
POS INL
-1.0
-1.0
0.5
0.0
-0.5
-3.0
-5.0
-6.0
NEG INL
-1.0
-7.0
-8.0
0.0
0.5
1.0
1.5
VREF (V)
2.0
FIGURE 13. CHANGE IN INL vs VREF FOR VDD = 3.3V
FN8341 Rev 0.00
August 10, 2012
5V VDD
-4.0
-1.5
-2.0
2.5
FIGURE 10. CHANGE IN DNL vs VREF FOR VDD = 5V
2.0
-1.5
0.0
2.0
VREF (V)
FIGURE 9. TYPICAL INL FOR VDD = 3V
-0.5
1.5
2.5
-9.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 14. CHANGE IN OFFSET ERROR vs VREF FOR VDD = 5V
AND 3.3V
Page 10 of 19
ISL267450
(Continued)
70000
70000
60000
60000
COUNT FREQUENCY
COUNT FREQUENCY
Typical Performance Characteristics
50000
40000
30000
20000
10000
0
50000
40000
30000
20000
10000
2044
2045
2046
2047
2048
2049
0
2050
2044
2045
2046
OUTPUT CODE
2047
2048
2049
2050
OUTPUT CODE
FIGURE 15. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT
FOR VDD = 5V
FIGURE 16. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT
FOR VDD = 3V
-40
12.0
11.5
-50
11.0
-60
5V VDD
10.0
PSRR (dB)
ENOB (BITS)
10.5
3.3V VDD
9.5
9.0
8.5
-80
-90
8.0
-100
7.5
7.0
-70
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-110
10
100
FIGURE 17. CHANGE IN ENOB vs VREF FOR VDD = 5V AND 3.3V
1k
10k
FREQUENCY (kHz)
VREF (V)
FIGURE 18. CMRR vs INPUT FREQUENCY FOR VDD = 5V AND 3V
FN8341 Rev 0.00
August 10, 2012
CONV
VIN+
VIN-
ACQ
ACQ
CONV
VREF
CS
ACQ
CONV
SAR
LOGIC
CS
DAC
The ISL267450 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital-to-analog converters (DACs). Figure 19 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
DAC
Functional Description
FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
Page 11 of 19
ISL267450
An external clock must be applied to the SCLK pin to generate a
conversion result. The allowable frequency range for SCLK is
50kHz to 18MHz. Serial output data is transmitted on the falling
edge of SCLK. The receiving device (FPGA, DSP or
Microcontroller) may latch the data on the rising edge of SCLK to
maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range and common-mode voltage.
See “Voltage Reference Input” on page 13 for more details.
ADC Transfer Function
The output coding for the ISL267450 is two’s complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size of the ISL267450 is
2*VREF/4096. The ideal transfer characteristic of the ISL267450
is shown in Figure 20.
011...111
V
5.0
VIN-
4.0
2.0VP-P
3.0
VIN+
VCM
2.0
1.0
t
VREF = 2V
1LSB = 2•V REF/4096
V
011...110
ADC CODE
5.0
VIN-
000...001
000...000
4.0
111...111
2.5VP-P
VIN+
VCM
3.0
100...010
100...001
2.0
100...000
–VREF
+ ½LSB
0V
+VREF +VREF
– 1½LSB – 1LSB
ANALOG INPUT
VIN+ – (VIN–)
t
FIGURE 20. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL267450 features a fully differential input with a nominal
full-scale range equal to twice the applied VREF voltage. Each
input swings VREF VP-P, 180° out-of-phase from one another for
a total differential input of 2*VREF (see Figure 21).
VREF(P-P)
VIN+
ISL267450
VCM
VREF(P-P)
1.0
VIN-
FIGURE 21. DIFFERENTIAL INPUT SIGNALING
Differential signaling offers several benefits over a single-ended
input, such as:
VREF = 2.5V
FIGURE 22. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE
Figure 22 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited for
larger values of VREF in order to keep the absolute maximum and
minimum voltages on the VIN+ and VIN– pins within specification.
Figures 23 and 24 illustrate this relationship for 5V and 3V
operation, respectively. The dashed lines show the theoretical
VCM range based solely on keeping the VIN+ and VIN– pins within
the supply rails. Additional restrictions are imposed due to the
required headroom of the input circuitry, resulting in practical
limits shown by the shaded area.
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
FN8341 Rev 0.00
August 10, 2012
Page 12 of 19
ISL267450
Voltage Reference Input
VCM
The voltage magnitude applied to the VREF pin defines the full
scale span of the ADC as 2* VREF. The device is specified with a
voltage reference of 2.5V for 5V operation and with a voltage
reference of 2.0V for 3V operation. But, VREF input accepts
voltages ranging from 0.1V to 3.5V for operation from 5 V VDD
and voltages ranging from 0.1V to 2.2V for operation from a 3V
VDD.
5.0
4.0
3.0
2.0
1.0
Figures 25 and 26 illustrate possible voltage reference options
for the ISL267450. Figure 25 uses the ISL21090 precision
voltage reference, which exhibits exceptionally low drift and low
noise. The ISL21090 must use a power supply greater than 4.7V.
The VREF input pin on the ISL267450 uses very low current, so
the decoupling capacitor can be small (0.1µF).
VREF
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 23. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V
VCM
Figure 26 illustrates the ISL21010 voltage reference. The
ISL21010 is available in various output voltages. It has higher
noise and drift than the ISL26090, but consumes very low
operating current, which makes it an excellent choice for
battery-powered applications.
3.0
2.5
2.0
1.5
1.0
0.5
V R EF
0.5
1.0
1.5
2.0
2.5
FIGURE 24. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V
5V
+
BULK
0.1µF
0.1µF
1 DNC
DNC
8
2 VIN
DNC
7
3 COMP VOUT
6
4 GND
5
TRIM
VDD
ISL267450
VREF
2.5V
0.1µF
ISL21090
FIGURE 25. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+3.0V TO +3.3V
OR +5V
+
VIN
1
VOUT
2
GND
3
BULK
0.1µF
0.1µF
ISL267450 VDD
VREF
1.25, 2.048 OR 2.5V
ISL21010
0.1µF
FIGURE 26. VOLTAGE REFERENCE FOR +3.0V TO +3.3V, OR FOR +5V SUPPLY
FN8341 Rev 0.00
August 10, 2012
Page 13 of 19
ISL267450
FIGURE 27. NORMAL MODE OPERATION
CONVERTER OPERATION
The ISL267450 is designed to minimize power consumption by
only powering up the SAR comparator during conversion time.
When the converter is in track mode (its sample capacitors are
tracking the input signal), the SAR comparator is powered down.
The state of the converter is dictated by the logic state of CS.
When CS is high, the SAR comparator is powered down while the
sampling capacitor array is tracking the input. When CS
transitions low, the capacitor array immediately captures the
analog signal that is being tracked. After CS is taken low, the
SCLK pin is toggled 16 times. For the first 3 clocks, the
comparator is powered up and auto-zeroed, then the SAR
decision process is begun. This process uses 12 SCLK cycles.
Each SAR decision is presented to the SDATA output on the next
clock cycle after the SAR decision is performed. The SAR process
(12 bits) is completed on SCLK cycle 15. At this point in time, the
SAR comparator is powered down and the capacitor array is
placed back into Track mode. The last SAR comparator decision
is output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
SCLK value than 18MHz, the minimum acquisition time is 200ns.
This minimum acquisition time also applies to the device when
operated at 3V supply or if short cycling is utilized.
SHORT CYCLING
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all 12 bits are clocked out. This is
referred to as short cycling, and it can be used to further optimize
power dissipation. In this mode, a lower resolution result will be
output, but the ADC will enter static mode sooner and exhibit a
lower average power consumption than if the complete
conversion cycle were carried out. The minimum acquisition time
(tACQ) requirement of 200ns must be met for the next
conversion to be valid.
POWER vs THROUGHPUT RATE
The ISL267450 provides reduced power consumption at lower
conversion rates by automatically switching into a low-power
mode after completing a conversion. The average power
consumption of the ADC decreases at lower throughput rates.
Figure 28 shows the typical power consumption over a wide
range of throughput rates.
Figure 27 illustrates the serial port system timing for the
ISL267450.
100
POWER-ON RESET
ACQUISITION TIME
To achieve the maximum sample rate (1MSps) in the ISL267450
device, the maximum acquisition time is 200ns. For slower
conversion rates, or for conversions performed using a slower
FN8341 Rev 0.00
August 10, 2012
10
POWER (mW)
When power is first applied, the ISL267450 performs a power-on
reset that requires approximately 2.5ms to execute. After this is
complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track
and hold. The dummy conversion cycle will take 889ns with an
18MHz SCLK. Once the dummy cycle is complete, the ADC mode
will be determined by the state of CS. Regular conversions can be
started immediately after this dummy cycle is completed and
time has been allowed for proper acquisition.
VDD = 5V
1
VDD = 3V
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
FIGURE 28. POWER CONSUMPTION vs THROUGHPUT RATE
Page 14 of 19
ISL267450
Serial Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
A falling edge on the CS signal initiates a conversion by placing
the part into the acquisition (ACQ) phase. After tACQ has elapsed,
the part enters the conversion (CONV) phase and begins
outputting the conversion result starting with a null bit followed
by the most significant bit (MSB) and ending with the least
significant bit (LSB). The CS pin can be pulled high at this point to
put the device into Standby mode and reduce the power
consumption. If CS is held low after the LSB bit has been output,
the conversion result will be repeated in reverse order until the
MSB is transmitted, after which the serial output enters a high
impedance state. The ISL267450 will remain in this state,
dissipating typical dynamic power levels, until CS transitions high
then low to initiate the next conversion.
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Signal-to-(Noise + Distortion) = 6.02 N + 1.76 dB
(EQ. 1)
Thus, for a 12-bit converter this is 74dB, and for a 10-bit it is
62dB.
INPUT
VOLTAGE
DIGITAL OUTPUT
–Full Scale
–VREF
1000 0000 0000
–Full Scale + 1LSB
–VREF + 1LSB
1000 0000 0001
Total Harmonic Distortion
Midscale
0
0000 0000 0000
+Full Scale – 1LSB
+VREF – 1LSB
0111 1111 1110
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267450, it is defined
as Equation 2:
+Full Scale
+VREF
0111 1111 1111
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL267450 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267450 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267450 to avoid
noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed-through through the board. A
FN8341 Rev 0.00
August 10, 2012
V 22 + V 32 + V 42 + V 52 + V 62
THD dB = 20 log ----------------------------------------------------------------------V 12
(EQ. 2)
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the sixth
harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of the
fundamental. It is also referred to as Spurious Free Dynamic
Range (SFDR). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
Page 15 of 19
ISL267450
The ISL267450 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is as
per the THD specification, where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+ – VIN– (i.e., +VREF – 1 LSB), after
the zero code error has been adjusted out.
Negative Gain Error
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (i.e., -VREF + 1 LSB), after
the zero code error has been adjusted out.
Full Power Bandwidth
Track and Hold Acquisition Time
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1dB or 3dB for a full-scale input.
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 200mVP-P sine wave applied to the common-mode voltage of
VIN+ and VIN– of frequency fs as shown by Equation 3.:
CMRR dB = 10 log Pfl Pfs
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC VDD
supply of frequency fS. The frequency of this input varies from
1kHz to 1MHz.
PSRR dB = 10 log Pf Pfs
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8341 Rev 0.00
August 10, 2012
Page 16 of 19
ISL267450
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
August 10, 2012
FN8341.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL267450
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
FN8341 Rev 0.00
August 10, 2012
Page 17 of 19
ISL267450
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN8341 Rev 0.00
August 10, 2012
Page 18 of 19
ISL267450
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN8341 Rev 0.00
August 10, 2012
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
Page 19 of 19
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