DATASHEET
ISL28005
FN6973
Rev 5.00
October 24, 2013
Micropower, Rail-to-Rail Input Current Sense Amplifier with Voltage Output
The ISL28005 is a micropower, uni-directional high-side and
low-side current sense amplifier featuring a proprietary rail-torail input current sensing amplifier. The ISL28005 is ideal for
high-side current sense applications where the sense voltage
is usually much higher than the amplifier supply voltage. The
device can be used to sense voltages as high as 28V when
operating from a supply voltage as low as 2.7V. The
micropower ISL28005 consumes only 50µA of supply current
when operating from a 2.7V to 28V supply.
The ISL28005 features a common-mode input voltage range
from 0V to 28V. The proprietary architecture extends the input
voltage sensing range down to 0V, making it an excellent
choice for low-side ground sensing applications. The benefit of
this architecture is that a high degree of total output accuracy
is maintained over the entire 0V to 28V common mode input
voltage range.
The ISL28005 is available in fixed (100V/V, 50V/V and 20V/V)
gains in the space saving 5 Ld SOT-23 package. The parts
operate over the extended temperature range from -40°C to
+125°C.
Features
• Low Power Consumption. . . . . . . . . . . . . . . . . . . . . . .50µA,Typ
• Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 28V
• Wide Common Mode Input. . . . . . . . . . . . . . . . . . . . 0V to 28V
• Fixed Gain Versions
- ISL28005-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V/V
- ISL28005-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V/V
- ISL28005-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/V
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ld SOT-23
Applications
• Power Management/Monitors
• Power Distribution and Safety
• DC/DC, AC/DC Converters
• Battery Management/Charging
• Automotive Power Distribution
Related Literature
• See AN1531 for “ISL28005 Evaluation Board User’s Guide”
• See AN1567 for “ISL28005, ISL28006 Unidirectional
Current Sense Amplifiers”
SENSE
RSENSE
SENSE
+5VDC
RSENSE
+12VDC
OUTPUT
+5VDC
ISL28005
+
-
ISENSE
+12VDC
1.6
+5VDC
OUTPUT
1.2
+5VDC
ISL28005
+
ISENSE
+5VDC
SENSE
+1.0VDC
RSENSE
MULTIPLE
OUTPUT
POWER SUPPLY
+5VDC
ISL28005
+
GND
FIGURE 1. TYPICAL APPLICATION
FN6973 Rev 5.00
October 24, 2013
1.8
+1.0VDC
OUTPUT
ISENSE
+1.0VDC
VRS+
1.4
VOLTS (V)
+12VDC
VTH(L-H) = 1.52V
VTH(H-L) = 1.23V
1.0
0.8
VOUT (G=100)
0.6
G100, VOUT = 1V
G50, VOUT = 500mV
G20, VOUT = 200mV
0.4
0.2
0
0
0.2
0.4
0.6
0.8 1.0 1.2
TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 2. HIGH-SIDE AND LOW-SIDE THRESHOLD VOLTAGE
Page 1 of 16
ISL28005
Block Diagram
VCC
I = 2.86µA
VSENSE
RS+
R1
HIGH-SIDE
AND
LOW-SIDE
SENSING
gmHI
RSR2
+
1.35V
-
OUT
Rf
VCC
IMIRROR
R3
R5
gmLO
Rg
VSENSE
R4
GND
Pin Descriptions
Pin Configuration
ISL28005
(5 LD SOT-23)
TOP VIEW
GND 1
OUT 2
VCC 3
ISL28005
(5 ld SOT-23)
PIN
NAME
1
GND
Power Ground
2
OUT
Amplifier Output
3
VCC
Positive Power Supply
4
RS+
Sense Voltage Non-inverting Input
5
RS-
Sense Voltage Inverting Input
5 RSFIXED
GAIN
4 RS+
DESCRIPTION
VCC
RS-
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
RS+
GND
FN6973 Rev 5.00
October 24, 2013
Page 2 of 16
ISL28005
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
GAIN
PART MARKING
PACKAGE
Tape & Reel
(Pb-Free)
PKG.
DWG. #
ISL28005FH100Z-T7
100V/V
BDEA (Note 4)
5 Ld SOT-23
P5.064A
ISL28005FH100Z-T7A
100V/V
BDEA (Note 4)
5 Ld SOT-23
P5.064A
ISL28005FH50Z-T7
50V/V
BDDA (Note 4)
5 Ld SOT-23
P5.064A
ISL28005FH50Z-T7A
50V/V
BDDA (Note 4)
5 Ld SOT-23
P5.064A
ISL28005FH20Z-T7
20V/V
BDCA (Note 4)
5 Ld SOT-23
P5.064A
ISL28005FH20Z-T7A
20V/V
BDCA (Note 4)
5 Ld SOT-23
P5.064A
ISL28005FH-100EVAL1Z
100V/V Evaluation Board
ISL28005FH-50EVAL1Z
50V/V Evaluation Board
ISL28005FH-20EVAL1Z
20V/V Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28005. For more information on MSL please see techbrief TB363.
4. The part marking is located on the bottom of the part.
FN6973 Rev 5.00
October 24, 2013
Page 3 of 16
ISL28005
Absolute Maximum Ratings
Thermal Information
Max Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..28V
Max Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
Max Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.5V
Max Input Voltage (RS+, RS-) . . . . . . . . . . . . . . . . . . . . . . . GND-0.5V to 30V
Max Input Current for Input Voltage 2V, VSENSE = 5mV
50
59
62
µA
Gain = 50, 20
Supply Current
VRS+ > 2V, VSENSE = 5mV
50
62
63
µA
VCC
Supply Voltage
Guaranteed by PSRR
2.7
28
V
SR
Gain = 100 Slew Rate
Pulse on RS+ pin,
VOUT = 8VP-P
(see Figure 25)
0.58
0.76
V/µs
Gain = 50 Slew Rate
Pulse on RS+ pin,
VOUT = 8VP-P
(see Figure 25)
0.58
0.67
V/µs
Gain = 20 Slew Rate
Pulse on RS+ pin,
VOUT = 3.5VP-P
(see Figure 25)
0.50
0.67
V/µs
Gain = 100
-3dB Bandwidth
VRS+ = 12V, 0.1V, VSENSE = 100mV
110
kHz
Gain = 50
-3dB Bandwidth
VRS+ = 12V, 0.1V, VSENSE = 100mV
160
kHz
Gain = 20
-3dB Bandwidth
VRS+ = 12V, 0.1V, VSENSE = 100mV
180
kHz
BW-3dB
FN6973 Rev 5.00
October 24, 2013
Page 5 of 16
ISL28005
Electrical Specification VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1MΩ, TA = +25°C unless otherwise specified. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER
ts
DESCRIPTION
Output Settling Time to 1% of Final Value
ts Power-up
MIN
(Note 7)
CONDITIONS
MAX
(Note 7)
TYP
UNIT
VCC = VRS+ = 12V, VOUT = 10V step,
VSENSE >7mV
15
µs
VCC = VRS+ = 0.2V, VOUT = 10V step,
VSENSE >7mV
20
µs
Capacitive-Load Stability
No sustained oscillations
300
pF
Power-Up Time to 1% of Final Value
VCC = VRS+ = 12V, VSENSE = 100mV
15
µs
VCC = 12V, VRS+ = 0.2V
VSENSE = 100mV
50
µs
VCC = VRS+ = 12V, VSENSE = 100mV,
overdrive
10
µs
Saturation Recovery Time
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. DEFINITION OF TERMS:
• VSENSEA = VSENSE @100mV
• VSENSEB = VSENSE @20mV
• VOUTA = VOUT@VSENSEA = 100mV
• VOUTB = VOUT@VSENSEB = 20mV
V OUT A – V OUT B
• G = GAIN = --------------------------------------------------------------
V SENSE A – V SENSE B
V OUT A
9. VOS is extrapolated from the gain measurement. V OS = V SENSE A – -------------------G
G MEASURED – G EXPECTED
10. % Gain Accuracy = GA = ------------------------------------------------------------------------------ 100
G EXPECTED
VOUT MEASURED – VOUT EXPECTED
11. Output Accuracy % VOA = ---------------------------------------------------------------------------------------------------------- 100 where VOUT = VSENSE X GAIN and VSENSE = 100mV
– VOUT EXPECTED
Typical Performance Curves VCC = 12V, RL = 1M, unless otherwise specified.
12
12
GAIN 100
10
10
8
8
VOUT (V)
VOUT (V)
GAIN 100
6
6
4
4
2
2
0
0
10
20
30
40
50
60
70
80
90
100
TIME (µs)
FIGURE 3. LARGE SIGNAL TRANSIENT RESPONSE VRS+ = 0.2V,
VSENSE = 100mV
FN6973 Rev 5.00
October 24, 2013
0
0
10
20
30
40
50
60
TIME (µs)
70
80
90
100
FIGURE 4. LARGE SIGNAL TRANSIENT RESPONSE VRS+ = 12V,
VSENSE = 100mV
Page 6 of 16
ISL28005
Typical Performance Curves VCC = 12V, RL = 1M, unless otherwise specified. (Continued)
VRS+
2.0
1.4
VTH(L-H) = 1.52V
0.8
VOUT (G = 100)
0.6
0.2
1.2
0
0
0.2
0.4
0.6
0.8 1.0 1.2
TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 5. HIGH-SIDE and LOW-SIDE THRESHOLD VOLTAGE
VRS+(L-H) and VRS+(H-L), VSENSE = 10mV
4
0
0.2
0.4
0.6
0.8
1.0 1.2
TIME (ms)
2
1.4
1.6
1.8
0
2.0
FIGURE 6. VOUT vs VRS+, VSENSE = 20mV TRANSIENT RESPONSE
45
GAIN 100
35
0.0
GAIN 100
25
-0.2
GAIN (dB)
VOA PERCENT ACCURACY (%)
0.2
6
G100, VOUT = 2V
G50, VOUT = 1V
G20, VOUT = 400mV
0.4
0
8
RL = 1M
VCC = 12V
0.8
G100, VOUT = 1V
G50, VOUT = 500mV
G20, VOUT = 200mV
0.4
10
VOUT (G = 100)
1.6
VTH(H-L) = 1.23V
1.0
VRS+ (V)
VOLTS (V)
1.2
+25°C
-0.4
-40°C
-0.6
+125°C
10µ
100µ
IOUT(A)
1m
10m
50
VRS+ = 12V
1k
10k
FREQUENCY (Hz)
100k
180
1000pF
30
1M
100
PHASE (°)
NO CL
10
10nF
0
VCC = 5V
VRS- = 3V
AV = 100
VOUT = 400mVP-P
-40
1k
10k
20
FIGURE 9. CAPACITIVE LOAD DRIVE GAIN vs FREQUENCY
10nF
-60
-180
1M
4.7nF
-20
-140
FREQUENCY (Hz)
FN6973 Rev 5.00
October 24, 2013
60
-100
100k
NO CL
100pF
1000pF
140
100pF
4.7nF
20
-30
-5
220
40
-20
VRS+= 100mV
5
FIGURE 8. GAIN vs FREQUENCY VRS+= 100mV/12V,
VSENSE = 100mV, VOUT = 250mVP-P
FIGURE 7. NORMALIZED VOA vs IOUT
-10
15
VCC = 12V
-15 V
SENSE = 100mV
AV = 100
-25
RL = 1M
-35
10
100
-0.8
-1.0
1µ
GAIN (dB)
12
2.4
VRS+
1.6
VOUT (V)
1.8
-220
1k
VCC = 5V
VRS- = 3V
AV = 100
VOUT = 400mVP-P
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. CAPACITIVE LOAD DRIVE PHASE vs FREQUENCY
Page 7 of 16
ISL28005
Typical Performance Curves VCC = 12V, RL = 1M, unless otherwise specified. (Continued)
45
GAIN 50
0.0
25
-0.2
-0.4
+25°C
-0.6
-40°C
+125°C
10µ
100µ
IOUT(A)
1m
10m
1k
10k
100k
VCC = 5V
180 V
RS- = 3V
140 AV = 50
100 VOUT = 400mVP-P
1000pF
30
100pF
4.7nF
20
PHASE (°)
GAIN (dB)
VRS+ = 12V
1M
220
40
NO CL
10
10nF
0
-30
-5
FIGURE 12. GAIN vs FREQUENCY VRS+= 100mV/12V,
VSENSE = 100mV, VOUT = 250mVP-P
50
-20
VRS+= 100mV
5
FREQUENCY (Hz)
FIGURE 11. NORMALIZED VOA vs IOUT
-10
15
VCC = 12V
-15 V
SENSE = 100mV
-25 AV = 50
RL = 1M
-35
10
100
-0.8
-1.0
1µ
VCC = 5V
VRS- = 3V
AV = 50
VOUT = 400mVP-P
-40
1k
60
20
1000pF
NO CL
100pF
4.7nF
10nF
-20
-60
-100
-140
-180
10k
100k
-220
1k
1M
FREQUENCY (Hz)
FIGURE 13. CAPACITIVE LOAD DRIVE GAIN vs FREQUENCY
0.2
10k
100k
FREQUENCY (Hz)
1M
FIGURE 14. CAPACITIVE LOAD DRIVE PHASE vs FREQUENCY
45
GAIN 20
GAIN 20
35
0.0
25
-0.2
-40°C
-0.4
GAIN (dB)
VOA PERCENT ACCURACY (%)
GAIN 50
35
GAIN (dB)
VOA PERCENT ACCURACY (%)
0.2
+25°C
-0.6
-0.8
-1.0
1µ
+125°C
10µ
100µ
1m
IOUT(A)
FIGURE 15. NORMALIZED VOA vs IOUT
FN6973 Rev 5.00
October 24, 2013
10m
15
5
-5
VCC = 12V
-15 V
SENSE = 100mV
AV = 20
-25
RL = 1M
-35
10
100
VRS+= 100mV
VRS+ = 12V
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 16. GAIN vs FREQUENCY VRS+ = 100mV/12V,
VSENSE = 100mV, VOUT = 250mVP-P
Page 8 of 16
ISL28005
Typical Performance Curves VCC = 12V, RL = 1M, unless otherwise specified. (Continued)
220
40
30
PHASE (°)
4.7nF
0
-10
10nF
VCC = 5V
VRS- = 3V
-30 AV = 20
VOUT = 400mVP-P
-40
1k
10k
NO CL
100
NO CL
10
100pF
140
100pF
20
GAIN (dB)
180
1000pF
-20
100k
1M
4.7nF
60
20
10nF
-20
-60
-100 VCC = 5V
V
= 3V
-140 RSAV = 20
-180 V
OUT = 400mVP-P
-220
1k
10k
FIGURE 17. CAPACITIVE LOAD DRIVE GAIN vs FREQUENCY
20
10
15
IRS+
INPUT BIAS CURRENT (uA)
INPUT BIAS CURRENT (uA)
1M
FIGURE 18. CAPACITIVE LOAD DRIVE PHASE vs FREQUENCY
15
5
0
-10
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
-5
1000pF
VCC = 12V
VRS- = 0V
AV = 20
RL = 1M
IRS+
IRS+
10
VCC = 12V
VRS- = 12V
AV = 20
RL = 1M
5
0
-5
IRS+
-10
-15
0
50
100
150
200
250
0
FIGURE 19. LOW-SIDE CURRENT SENSING INPUT BIAS CURRENTS
50
100
150
200
250
DIFFERENTIAL VOLTAGE RS+ TO RS- (mV)
DIFFERENTIAL VOLTAGE RS+ TO RS- (mV)
FIGURE 20. HIGH-SIDE CURRENT SENSING INPUT BIAS
CURRENTS
Test Circuits and Waveforms
VCC
VR1
ICC
+
+
VRS+
VSENSE
RS+
R1
OUT
+
VRS+
GND
1M
RS+
+
RS-
-
VCC
RL VOUT
VSENSE
OUT
RS-
R2
GND
-
1M
RL VOUT
VR2
FIGURE 21. ICC, VOS, VOA, CMRR, PSRR, GAIN ACCURACY
FN6973 Rev 5.00
October 24, 2013
FIGURE 22. INPUT BIAS CURRENT, LEAKAGE CURRENT
Page 9 of 16
ISL28005
Test Circuits and Waveforms (Continued)
SIGNAL
GENERATOR
VCC
RS+
OUT
RS+
RS-
VRS+
VRS-
GND
1M
VCC
VRS+
RL VOUT
VSENSE
OUT
RSGND
1M
RL VOUT
PULSE
GENERATOR
FIGURE 23. SLEW RATE, ts, SATURATION RECOVERY TIME
FIGURE 24. GAIN vs FREQUENCY
VCC
RS+
OUT
RS-
VRS+
GND
1M
RL VOUT
PULSE
GENERATOR
FIGURE 25. SLEW RATE
Applications Information
Functional Description
The ISL28005-20, ISL28005-50 and ISL28005-100 are single
supply, uni-directional current sense amplifiers with fixed gains
of 20V/V, 50V/V and 100V/V respectively.
The ISL28005 is a 2-stage amplifier. Figure 26 shows the active
circuitry for high-side current sense applications where the sense
voltage is between 1.35V to 28V. Figure 27 shows the active
circuitry for ground sense applications where the sense voltage is
between 0V to 1.35V.
supply current from the input source through the RS+ terminal.
When the sense voltage at RS+ drops below the 1.35V threshold,
the gmLO amplifier is enabled for Low Side current sensing. The
gmLO input bias current reverses, flowing out of the RS- pin.
Since the gmLO amplifier is sensing voltage around ground, it
cannot source current to R5. A current mirror referenced off Vcc
supplies the current to the second stage for generating a ground
referenced output voltage. See Figures 19 and 20 for typical
input bias currents for High and Low side current sensing.
The first stage is a bi-level trans-conductance amp and level
translator. The gm stage converts the low voltage drop (VSENSE)
sensed across an external milli-ohm sense resistor, to a current
(@ gm = 21.3µA/V). The trans-conductance amplifier forces a
current through R1 resulting to a voltage drop across R1 that is
equal to the sense voltage (VSENSE). The current through R1 is
mirrored across R5 creating a ground-referenced voltage at the
input of the second amplifier equal to VSENSE.
The second stage is responsible for the overall gain and
frequency response performance of the device. The fixed gains
(20, 50, 100) are set with internal resistors Rf and Rg. The only
external component needed is a current sense resistor (typically
0.001 to 0.01, 1W to 2W).
The transfer function is given in Equation 1.
V OUT = GAIN I S R S + V OS
(EQ. 1)
Where ISRS is the product of the load current and the sense
resistor and is equal to VSENSE.
When the sensed input voltage is >1.35V, the gmHI amplifier
path is selected and the input gm stage derives its ~2.86µA
FN6973 Rev 5.00
October 24, 2013
Page 10 of 16
ISL28005
VCC
OPTIONAL
FILTER
CAPACITOR
I = 2.86µA
VSENSE
IS
RS+
+
R1
VSENSE
RS
HIGH-SIDE
SENSING
VRS+ = 2V TO 28V
gmHI
-
VCC = 2V to 28V
RSR2
+
OPTIONAL
TRANSIENT
PROTECTION
OUT
-
1.35V
Rf
IMIRROR
R3
gmLO
‘VSENSE
Rg
R5
LOAD
R4
GND
FIGURE 26. HIGH-SIDE CURRENT DETECTION
VCC = 2V TO 28V
VCC
OPTIONAL
FILTER
CAPACITOR
I = 2.86µA
VSENSE
IS
RS+
+
RS
R1
VSENSE
LOW-SIDE
SENSING
VRS+= 0V TO 28V
gmHI
RSR2
LOAD
+
OPTIONAL
TRANSIENT
PROTECTION
1.35V
VCC
IMIRROR
R3
gmLO
R5
OUT
Rf
Rg
VSENSE
R4
GND
FIGURE 27. LOW-SIDE CURRENT DETECTION
FN6973 Rev 5.00
October 24, 2013
Page 11 of 16
ISL28005
Hysteretic Comparator
The input trans-conductance amps are under control of a
hysteretic comparator operating from the incoming source
voltage on the RS+ pin (see Figure 28). The comparator monitors
the voltage on RS+ and switches the sense amplifier from the
low-side gm amp to the high-side gm amplifier whenever the
input voltage at RS+ increases above the 1.35V threshold.
Conversely, a decreasing voltage on the RS+ pin, causes the
hysteric comparator to switch from the high-side gm amp to the
low-side gm amp as the voltage decreases below 1.35V. It is that
low-side sense gm amplifier that gives the ISL28005 the
proprietary ability to sense current all the way to 0V. Negative
voltages on the RS+ or RS- are beyond the sensing voltage range
of this amplifier.
0.5
0.4
ACCURACY (%)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.2
0.4
0.6
0.8
1.0
1.2
VRS+ (V)
1.4
1.6
1.8
value of 100Ω will provide protection for a 2V transient with the
maximum of 20mA flowing through the input while adding only
an additional 13µV (worse case over-temperature) of VOS. Refer
to the following formula:
((RP x IRS-) = (100 x 130nA) = 13µV)
Switching applications can generate voltage spikes that can
overdrive the amplifier input and drive the output of the amplifier
into the rails, resulting in a long overload recovery time.
Capacitors CM and CD filter the common mode and differential
voltage spikes.
Error Sources
There are 3 dominant error sources: gain error, input offset
voltage error and Kelvin voltage error (see Figure 29). The gain
error is dominated by the internal resistance matching
tolerances. The remaining errors appear as sense voltage errors
at the input to the amplifier. They are VOS of the amplifier and
Kelvin voltage errors. If the transient protection resistor is added,
an additional VOS error can result from the IxR voltage due to
input bias current. The limiting resistor should only be added to
the RS- input, due to the high-side gm amplifier (gmHI) sinking
several micro amps of current through the RS+ pin.
Layout Guidelines
2.0
Kelvin Connected Sense Resistor
FIGURE 28. GAIN ACCURACY vs VRS+ = 0V TO 2V
Typical Application Circuit
Figure 30 shows the basic application circuit and optional
protection components for switched-load applications. For
applications where the load and the power source is permanently
connected, only an external sense resistor is needed. For
applications where fast transients are caused by hot plugging the
source or load, external protection components may be needed.
The external current limiting resistor (RP) in Figure 30 may be
required to limit the peak current through the internal ESD
diodes to < 20mA. This condition can occur in applications that
experience high levels of in-rush current causing high peak
voltages that can damage the internal ESD diodes. An RP resistor
The source of Kelvin voltage errors is illustrated in Figure 29. The
resistance of 1/2 oz. copper is ~1m per square with a TC of
~3900ppm/°C (0.39%/°C). When you compare this unwanted
parasitic resistance with the total of 1m to 10m resistance of the
sense resistor, it is easy to see why the sense connection must be
chosen very carefully. For example, consider a maximum current of
20A through a 0.005sense resistor, generating a VSENSE = 0.1
and a full scale output voltage of 10V (G = 100). Two side contacts
of only 0.25 square per contact puts the VSENSE input about 0.5 x
1m away from the resistor end capacitor. If only 10A the 20A total
current flows through the kelvin path to the resistor, you get an error
voltage of 10mV (10A x 0.5sq x 0.001/sq. = 10mV) added to the
100mV sense voltage for a sense voltage error of 10%
(0.110V - 0.1)/0.1V) x 100.
CURRENT
RESISTOR
Current SENSE
Sense Resistor
CURRENT
Current InIN
Non-uniform
NON-UNIFORM
CURRENT
FLOW
Current Flow
1mΩ
10mΩ
1 toTO
10mO
Copper
Trace TRACE
1/2
Oz COPPER
1mΩ /SQ
30mO/Sq.
CURRENT OUT
Current Out
PC BOARD
Board
PC
KELVIN
CONTACTS
Kelvin VVSSContacts
FIGURE 29. PC BOARD CURRENT SENSE KELVIN CONNECTION
FN6973 Rev 5.00
October 24, 2013
Page 12 of 16
ISL28005
2.7VDC
TO
28VDC
VCC
I = 2.86µA
RS+
RS
(1mΩ
TO
0.1Ω)
CD
gmHI
RS-
CM
+
RP
+
-
0.1VDC
TO
28VDC
OUT
-
1.35V
gmLO
LOAD
GND
FIGURE 30. TYPICAL APPLICATION CIRCUIT
Overall Accuracy (VOA %)
where:
VOA is defined as the total output accuracy Referred-to-Output
(RTO). The output accuracy contains all offset and gain errors, at
a single output voltage. Equation 2 is used to calculate the %
total output accuracy.
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
V OUT actual – V OUT exp ected
V OA = 100 ------------------------------------------------------------------------------------
V OUT exp ected
(EQ. 2)
• PDMAX for each amplifier can be calculated using Equation 5:
V OUTMAX
PD MAX = V S I qMAX + V S - V OUTMAX ---------------------------RL
(EQ. 5)
where:
where
• TMAX = Maximum ambient temperature
VOUT Actual = VSENSE x GAIN
• JA = Thermal resistance of the package
Example: Gain = 100, For 100mV VSENSE input we measure
10.1V. The overall accuracy (VOA) is 1% as shown in Equation 3.
• PDMAX = Maximum power dissipation of 1 amplifier
10.1 – 10
V OA = 100 ------------------------ = 1percent
10
• VCC = Total supply voltage
(EQ. 3)
• IqMAX = Maximum quiescent supply current of 1 amplifier
Power Dissipation
• VOUTMAX = Maximum output voltage swing of the application
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 4:
• RL = Load resistance
T JMAX = T MAX + JA xPD MAXTOTAL
FN6973 Rev 5.00
October 24, 2013
(EQ. 4)
Page 13 of 16
ISL28005
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE
REVISION
October 24, 2013
FN6973.5
CHANGE
Added eight new Typical Performance Curves
1. Av = 100 Capacitive Load Drive Gain vs Freq
2. Av = 100 Capacitive Load Drive Phase vs Freq
3. Av = 50 Capacitive Load Drive Gain vs Freq
4. Av = 50 Capacitive Load Drive Phase vs Freq
5. Av = 20 Capacitive Load Drive Gain vs Freq
6. Av = 20 Capacitive Load Drive Phase vs Freq
7. High Side Operation Input Bias Currents
8. Low Side Operation Input Bias Currents
Under Electrical Specifications Table:
Changed parameter from Is to Icc to clarify supply current.
April 11, 2011
FN6973.4
Corrected location of the load in Figure 27. Moved Load from the ground side of the input sense circuit to the high side of the
voltage source.
Updated note in Min Max column of spec table from "Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production tested." to
"Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design."
September 2, 2010
FN6973.3
Added -T7A tape and reel package options to Ordering Information Table for all packages.
May 12, 2010
FN6973.2
Added Note 4 to Part Marking Column in “Ordering Information” on page 3.
Corrected hyperlinks in Notes 1 and 3 in “Ordering Information” on page 3.
Corrected ISL28005 hyperlink in “About Intersil” on page 15.
April 12, 2010
Added Eval boards to ordering info.
April 7, 2010
Added “Related Literature” on page 1
Updated Package Drawing Number in the “Ordering Information” on page 3 from MDP0038 to P50.64A.
Revised package outline drawing from MDP0038 to P5.064A on page 16. MDP0038 package contained 2 packages for both
the 5 and 6 Ld SOT-23. MDP0038 was obsoleted and the packages were separated and made into 2 separate package
outline drawings; P5.064A and P6.064A. Changes to the 5 Ld SOT-23 were to move dimensions from table onto drawing,
add land pattern and add JEDEC reference number.
February 3, 2010
FN6973.1
-Page1:
Edited last sentence of paragraph 2.
Moved order of GAIN listings from 20, 50, 100 to 100, 50, 20 in the 3rd paragraph.
Under Features ....removed "Low Input Offset Voltage 250µV,max"
Under Features .... moved order of parts listing from 20, 50, 100 (from top to bottom) to 100, 50, 20.
-Page 3:
Removed coming soon on ISL28005FH50Z and ISL28005FH20Z and changes the order or listing them to 100, 50, 20.
-Page 5:
VOA test. Under conditions column ...deleted “20mV to”. It now reads ... Vsense = 100mV
SR test. Under conditions column ..deleted what was there. It now reads ... Pulse on RS+pin, See Figure 25
-Page 6:
ts test. Removed Gain = 100 and Gain = 100V/V in both description and conditions columns respectively.
-Page 9
Added Figure 25 and adjusted figure numbers to account for the added figure.
December 14, 2009
FN6973.0
Initial Release
FN6973 Rev 5.00
October 24, 2013
Page 14 of 16
ISL28005
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
© Copyright Intersil Americas LLC 2009-2013. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6973 Rev 5.00
October 24, 2013
Page 15 of 16
ISL28005
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
D
A
0.08-0.20
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
2
5
(0.60)
0.20 C
2x
0.95
SEE DETAIL X
B
0.40 ±0.05
3
END VIEW
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
2.90
5
H
0.15 C A-B
2x
C
1.45 MAX
1.14 ±0.15
0.10 C
SIDE VIEW
SEATING PLANE
(0.25) GAUGE
PLANE
0.45±0.1
0.05-0.15
4
DETAIL "X"
(0.60)
(1.20)
NOTES:
(2.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN6973 Rev 5.00
October 24, 2013
Page 16 of 16
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