DATASHEET
ISL28114, ISL28214, ISL28414
Single, Dual, Quad General Purpose Micropower, RRIO Operational Amplifiers
FN6800
Rev 10.00
December 8, 2016
The ISL28114, ISL28214, and ISL28414 are single, dual, and
quad channel general purpose micropower, rail-to-rail input
and output operational amplifiers with supply voltage range of
1.8V to 5.5V. Key features are a low supply current of 390µA
maximum per channel at room temperature, a low bias
current, and a wide input voltage range, which enables the
ISL28x14 devices to be excellent general purpose op amps for
a wide range of applications.
Features
The ISL28114 is available in the SC70-5 and SOT23-5
packages, the ISL28214 is in the MSOP8, SO8, and SOT23-8
packages, and the ISL28414 is in the TSSOP14 and SOIC14
packages. All devices operate across the extended
temperature range of -40°C to +125°C.
• Packages
- ISL28114 (single). . . . . . . . . . . . . . . . . . . . SC70-5, SOT23-5
- ISL28214 (dual) . . . . . . . . . . . . . . . . MSOP8, SO8, SOT23-8
- ISL28414 (quad) . . . . . . . . . . . . . . . . . . . SOIC14, TSSOP14
Related Literature
Applications
• For a full list of related documents, visit our website
- ISL28114, ISL28214 and ISL28414 product pages
• Process control
• Low current consumption . . . . . . . . . . . . . . . . . . . . . . . . 390µA
• Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
• Gain-bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz
• Input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . 20pA, Max.
• Operating temperature range. . . . . . . . . . . .-40°C to +125°C
• Power supply control/regulation
• Signal gain/buffers
• Active filters
• Current shunt sensing
• Transimpedance amp
RF
100kΩ
LOAD
RINRSENSE
IN-
10kΩ
RIN+
IN+
+5V
-
VOUT
V+
ISL28x14
V-
+
10kΩ
GAIN = 10
RREF+
100kΩ
VREF
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
FIGURE 1. TYPICAL APPLICATION
FN6800 Rev 10.00
December 8, 2016
Page 1 of 23
ISL28114, ISL28214, ISL28414
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
ISL28114FEZ-T7 (Notes 1, 2)
BKA (Note 5)
3k
5 Ld SC-70
P5.049
ISL28114FEZ-T7A (Notes 1, 2)
BKA (Note 5)
250
5 Ld SC-70
P5.049
ISL28114FHZ-T7 (Notes 1, 2)
BDBA (Note 5)
3k
5 Ld SOT-23
P5.064A
ISL28114FHZ-T7A (Notes 1, 2)
BDBA (Note 5)
250
5 Ld SOT-23
P5.064A
ISL28214FUZ (Note 2)
8214Z
-
8 Ld MSOP
M8.118A
ISL28214FUZ-T7 (Notes 1, 2)
8214Z
1.5k
8 Ld MSOP
M8.118A
ISL28214FBZ (Note 2)
28214 FBZ
-
8 Ld SOIC
M8.15E
ISL28214FBZ-T7 (Notes 1, 2)
28214 FBZ
1k
8 Ld SOIC
M8.15E
ISL28214FBZ-T13 (Notes 1, 2)
28214 FBZ
2.5k
8 Ld SOIC
M8.15E
ISL28214FHZ-T7 (Notes 1, 3)
BELA (Note 5)
3k
8 Ld SOT-23
P8.064
ISL28214FHZ-T7A (Notes 1, 3)
BELA (Note 5)
250
8 Ld SOT-23
P8.064
ISL28414FVZ (Note 2)
28414 FVZ
-
14 Ld TSSOP
MDP0044
ISL28414FVZ-T7 (Notes 1, 2)
28414 FVZ
1k
14 Ld TSSOP
MDP0044
ISL28414FVZ-T13 (Notes 1, 2)
28414 FVZ
2.5k
14 Ld TSSOP
MDP0044
ISL28414FBZ (Note 2)
28414 FBZ
-
14 Ld SOIC
MDP0027
ISL28414FBZ-T7 (Notes 1, 2)
28414 FBZ
1k
14 Ld SOIC
MDP0027
ISL28414FBZ-T13 (Notes 1, 2)
28414 FBZ
2.5k
14 Ld SOIC
MDP0027
ISL28114SOT23EVAL1Z
Evaluation Board
ISL28214MSOPEVAL2Z
Evaluation Board
ISL28214SOICEVAL2Z
Evaluation Board
ISL28414TSSOPEVAL1Z
Evaluation Board
NOTES:
1. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), see device information page for ISL28114, ISL28214, ISL28414. For more information on MSL, see Tech Brief
TB363.
5. The part marking is located on the bottom of the part.
FN6800 Rev 10.00
December 8, 2016
Page 2 of 23
ISL28114, ISL28214, ISL28414
Pin Configurations
IN+
1
VS-
2
IN-
3
ISL28214
(8 LD MSOP, 8 LD SOIC, 8 LD SOT-23)
TOP VIEW
ISL28114
(5 LD SOT-23)
TOP VIEW
ISL28114FEZ
(5 LD SC-70)
TOP VIEW
VS+
5
OUT
4
OUT
1
VS-
2
IN+
3
5
4
VS+
IN-
OUT_A
1
8
VS+
IN-_A
2
7
OUT_B
IN+_A
3
6
IN-_B
VS-
4
5
IN+_B
ISL28414
(14 LD TSSOP, 14 LD SOIC)
TOP VIEW
OUT_A 1
14 OUT_D
IN-_A 2
13 IN-_D
IN+_A 3
12 IN+_D
VS+ 4
11 VS-
IN+_B 5
10 IN+_C
IN-_B 6
9 IN-_C
8 OUT_C
OUT_B 7
Pin Descriptions
PIN NUMBER
PIN NAME 5 Ld SC-70
OUT
OUT_A
OUT_B
OUT_C
OUT_D
4
5 Ld SOT-23
8 Ld MSOP,
8 Ld SOIC,
8 Ld SOT-23
14 Ld TSSOP,
14 LD SOIC
DESCRIPTION
CIRCUITS
Output
1
1
7
V+
1
7
8
14
OUT
VCIRCUIT 1
VS-
2
2
4
11
Negative supply voltage
V+
CAPACITIVELY
TRIGGERED
ESD CLAMP
VCIRCUIT 2
IN+
IN+_A
IN+_B
IN+_C
IN+_D
1
ININ-_A
IN-_B
IN-_C
IN-_D
3
VS+
5
Positive Input
3
3
5
2
6
FN6800 Rev 10.00
December 8, 2016
IN-
IN+
Negative Input
4
5
V+
3
5
10
12
8
2
6
9
13
4
VCIRCUIT 3
Positive supply voltage
See “CIRCUIT 2”
Page 3 of 23
ISL28114, ISL28214, ISL28414
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
Machine Model (ISL28114, ISL28214) . . . . . . . . . . . . . . . . . . . . . . . 350V
Machine Model (ISL28414). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
5 Ld SC-70 (Notes 6) . . . . . . . . . . . . . . . . . .
250
N/A
5 Ld SOT-23 (Notes 6) . . . . . . . . . . . . . . . . .
225
N/A
8 Ld MSOP (Notes 6, 7) . . . . . . . . . . . . . . . .
180
100
8 Ld SOIC Package (Notes 6, 7) . . . . . . . . .
126
90
8 Ld SOT-23 Package (Notes 6, 7) . . . . . . .
240
168
14 Ld TSSOP Package (Notes 6, 7) . . . . . .
120
40
14 Ld SOIC Package (Notes 6, 7) . . . . . . . .
90
50
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified. Boldface limits apply across
the operating temperature range, -40°C to +125°C, unless otherwise specified.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
-4
0.5
4
mV
5
mV
DC SPECIFICATIONS
VOS
Input Offset Voltage
-40°C to +125°C
TCVOS
Input Offset Voltage Temperature
Coefficient
IOS
Input Offset Current
IB
Input Bias Current
-5
-40°C to +125°C
ISL28114
5
1
30
pA
3
20
pA
100
pA
20
pA
-50
50
pA
- 0.1
5.1
V
-20
-100
ISL28214, ISL28414
Common-Mode Input Voltage Range
CMRR
PSRR
VOH
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing, High
µV/°C
-20
3
VCM = -0.1V to 5.1V
72
dB
-40°C to +125°C
70
dB
VS = 1.8V to 5.5V
71
dB
-40°C to +125°C
70
dB
4.993
V
RL = 10kΩ
4.985
4.98
VOL
Output Voltage Swing, Low
V+
Supply Voltage
IS
Supply Current per Amplifier
RL = 10kΩ
V
13
1.8
RL = OPEN
300
15
mV
20
mV
5.5
V
390
µA
475
µA
ISC+
Output Source Short-Circuit Current RL = 10Ω to V-
-31
mA
ISC-
Output Sink Short-Circuit Current
26
mA
FN6800 Rev 10.00
December 8, 2016
RL = 10Ω to V+
Page 4 of 23
ISL28114, ISL28214, ISL28414
Electrical Specifications
VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified. Boldface limits apply across
the operating temperature range, -40°C to +125°C, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
AC SPECIFICATIONS
GBWP
Gain-Bandwidth Product
VS = ±2.5V
AV = 100, RF = 100kΩ, RG = 1kΩ,
RL = 10kΩ to VCM
eN VP-P
Peak-to-Peak Input Noise Voltage
eN
Input Noise Voltage Density
iN
Input Noise Current Density
ZIN
Input Impedance
Cin
Differential Input Capacitance
Common-Mode Input Capacitance
5
MHz
VS = ±2.5V
f = 0.1Hz to 10Hz
12
µVP-P
VS = ±2.5V
f = 1kHz
40
nV/√(Hz)
VS = ±2.5V
f = 10kHz
16
nV/√(Hz)
VS = ±2.5V
f = 1kHz
8
fA/√(Hz)
1012
Ω
1.0
pF
1.3
pF
VS = ±2.5V
f = 1MHz
TRANSIENT RESPONSE
SR
Slew Rate
VOUT = 0.5V to 4.5V
2.5
V/µs
tr, tf, Small Signal
Rise Time, tr 10% to 90%
VS = ±2.5V
AV = +1, VOUT = 0.05VP-P
RF = 0Ω, RL = 10kΩCL = 15pF
37
ns
42
ns
5.6
µs
Fall Time, tf 10% to 90%
ts
Settling Time to 0.1%, 4VP-P Step
VS = ±2.5V
AV = +1, RF = 0ΩRL = 10kΩ
CL = 1.2pF
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
FN6800 Rev 10.00
December 8, 2016
Page 5 of 23
ISL28114, ISL28214, ISL28414
Typical Performance Curves
VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified.
50
INPUT NOISE VOLTAGE (nV/Hz)
10,000
40
30
10
0
-10
-20
-30
-40
SIMULATION
-50
-40
-20
0
20
40
60
80
100
120
1000
100
10
140
1
10
TEMPERATURE (°C)
1k
10k
100k
FIGURE 3. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE
20
120
20
100
0
100
0
80
-20
GAIN
60
-40
40
-60
20
-80
0
-100
-20 V+ = ±0.9V
RL = 100k
-40
CL = 10pF
-60 SIMULATION
-80
0.1
1
10
-120
PHASE
-140
-160
100
1k
10k 100k
FREQUENCY (Hz)
1M
-180
10M 100M
80
-60
20
-80
0
-100
-20 V+ = ±0.9V
RL = 100k
-40
CL = 10pF
-60 SIMULATION
-80
0.1
70
80
60
70
30
0
0.01
10
-140
-160
100
1k
10k 100k
FREQUENCY (Hz)
1M
-180
10M 100M
PSRR+ VS = ±0.9V
PSRR+ VS = ±2.5V
PSRR- VS = ±2.5V
60
50
40
PSRR- VS = ±0.9V
30
RL = INF
20 C = 4pF
L
10 AV = +1
20
10
1
-120
PHASE
FIGURE 5. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 100kΩ,
CL = 10pF, VS = ±2.5V
90
40
-40
40
80
50
-20
GAIN
60
PSRR (dB)
CMRR (dB)
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 100kΩ,
CL = 10pF, VS = ±0.9V
OPEN-LOOP GAIN (dB)
120
PHASE (°)
OPEN-LOOP GAIN (dB)
100
FREQUENCY (Hz)
SIMULATION
0.1
1
10
100 1k 10k 100k
FREQUENCY (Hz)
1M
10M 100M
FIGURE 6. CMRR vs FREQUENCY (SIMULATED DATA)
FN6800 Rev 10.00
December 8, 2016
PHASE (°)
IBIAS (pA)
20
V+ = ±2.5V
AV = 1
VCM = 100mVP-P
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 7. PSRR vs FREQUENCY, VS = ±0.9V, ±2.5V
Page 6 of 23
ISL28114, ISL28214, ISL28414
Typical Performance Curves
70
GAIN (dB)
AV = 100
V+ = ±2.5V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
30
20
AV = 10
Rg = 10k, Rf = 100k
10
0
0
Rg = 1k, Rf = 100k
50
40
1
Rg = 100, Rf = 100k
AV = 1000
AV = 1
-10
10
NORMALIZED GAIN (dB)
60
VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
Rg = OPEN, Rf = 0
10k
1k
100
100k
1M
10M
100M
-1
-2
-3
-4
VOUT = 10mVP-P
-5
VOUT = 50mVP-P
-6 VS = ±2.5V
VOUT = 100mVP-P
-7 CL = 4pF
A = +1
-8 V
RL = 10k
-9
100
1k
VOUT = 200mVP-P
VOUT = 500mVP-P
VOUT = 1VP-P
10k
0
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
10M
100M
14
1
-2
-3
-4
RL = 4.99k
-5
RL = 1k
-6 V+ = ±2.5V
-7 CL = 4pF
AV = +1
-8
VOUT = 50mVP-P
-9
100
1k
10k
RL = 499
1M
CL = 1004pF
CL = 474pF
6
CL = 224pF
4
CL = 104pF
2
0
CL = 26pF
-2
RL = 100
100k
VS = ±2.5V
12 RL = 10k
AV = +1
10
VOUT = 50mVP-P
8
10M
CL = 4pF
-4
1k
100M
10k
FREQUENCY (Hz)
100k
1M
10M
FREQUENCY (Hz)
FIGURE 11. GAIN vs FREQUENCY vs CL
FIGURE 10. GAIN vs FREQUENCY vs RL
140
1
0
120
-1 CL = 4pF
RL = 10k
-2
AV = +1
-3 VOUT = 50mVP-P
CROSSTALK (dB)
NORMALIZED GAIN (dB)
1M
FIGURE 9. FREQUENCY RESPONSE vs VOUT
FIGURE 8. FREQUENCY RESPONSE vs CLOSED-LOOP GAIN
-4
-5
VS = ±2.5V
-6
VS = ±1.75V
-7
VS = ±1.25V
-8
-9
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FN6800 Rev 10.00
December 8, 2016
80
60
40
20
VS = ±0.9V
100k
100
0
10
VS = ±2.5V
RL-DRIVER = INF
RL-RECEIVER = 10k
CL = 4pF
AV = +1
VSOURCE = 1VP-P
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 13. CROSSTALK, VS = ±2.5V
Page 7 of 23
ISL28114, ISL28214, ISL28414
VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
30
3
20
2
10
LARGE SIGNAL (V)
VS = ±2.5V
RL = 10k
CL = 15pF
AV = +1
VOUT = 50mVP-P
0
-10
-20
1
VS = ±0.9V
0
RL = 10k
CL = 15pF
AV = +1
VOUT = RAIL
-1
-2
-30
-40
VS = ±2.5V
0
80
160
240
320
400
480
560
640
720
-3
800
0
1
2
3
4
TIME (ns)
0.5
RL = INF
CL = 15pF
AV =10
Rf = 9.09k, Rg = 1k
INPUT (V)
-0.1
-0.2
-0.3
OUTPUT AT VS = ±2.5V
0
0.4
0.8
1.2
1.6 2.0 2.4
TIME (ms)
2.8
3.3
-0.5
0.4
-1.5
-0.5
-0.6
0.5
-1.0
OUTPUT AT VS = ±0.9V
-0.4
0
3.6
INPUT (V)
0
8
9
10
3.0
0.6
OUTPUT (V)
INPUT
7
FIGURE 15. LARGE SIGNAL TRANSIENT RESPONSE vs
RL, VS = ±0.9V, ±2.5V
FIGURE 14. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±2.5V
0.1
5
6
TIME (µs)
OUTPUT AT VS = ±2.5V
-2.5
0
-3.0
4.0
-0.1
1.5
RL = INF
CL = 15pF
AV = 10
Rf = 9.09k, Rg = 1k
0.2
0.1
2.0
OUTPUT AT VS = ±0.9V
0.3
-2.0
2.5
1.0
0.5
0
INPUT
0
0.4
0.8
1.2
1.6 2.0 2.4
TIME (ms)
2.8
3.3
3.6
-0.5
4.0
FIGURE 17. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±0.9V, ±2.5V
FIGURE 16. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±0.9V, ±2.5V
100
+
O
T
T
-
SH
O
O
O
VE
60
O
VE
R
50
SH
70
O
OVERSHOOT (%)
80
VS = ±2.5V
RL = 10k
AV = 1
VOUT = 50mVP-P
R
90
40
30
20
10
0
1
10
100
CAPACITANCE (pF)
1k
10k
FIGURE 18. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±2.5V
FN6800 Rev 10.00
December 8, 2016
Page 8 of 23
OUTPUT (V)
SMALL SIGNAL (mV)
Typical Performance Curves
ISL28114, ISL28214, ISL28414
Applications Information
Power Dissipation
Functional Description
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply conditions, and
ambient temperature conditions. It is therefore important to
calculate the maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package types need to be modified to remain in
the safe operating area. These parameters are related using
Equation 1:
The ISL28114, ISL28214 and ISL28414 are single, dual, and
quad, CMOS rail-to-rail input, output (RRIO) micropower
operational amplifiers. They are designed to operate from single
supply (1.8V to 5.5V) or dual supply (±0.9V to ±2.75V). The parts
have an input common-mode range that extends 100mV above
and below the power supply voltage rails. The output stage can
swing to within 15mV of the supply rails with a 10kΩ load.
Input ESD Diode Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input currents
never exceed 20mA (see Figure 19).
(EQ. 1)
T JMAX = T MAX + JA xPD MAXTOTAL
where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S I qMAX + V S - V OUTMAX -----------------------R
L
(EQ. 2)
where:
V+
VIN-
RIN-
-
RIN+
+
RF
• TMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
RL
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1 amplifier
RG
V-
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
FIGURE 19. INPUT ESD DIODE CURRENT LIMITING
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28114, ISL28214, and ISL28414 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
If the application requires less than all amplifiers on one
channel, the user must configure the unused channel(s) to
prevent oscillation. The unused channel(s) will oscillate if the
input and output pins are floating. This will result in higher than
expected supply currents and possible noise injection into the
channel being used. The proper way to prevent this oscillation is
to short the output to the inverting input and ground the positive
input (as shown in Figure 20).
ISL28114, ISL28214, and ISL28414 SPICE
Model
Figure 21 on page 11 shows the SPICE model schematic and
Figure 22 on page 12 shows the net list for the SPICE model. The
model is a simplified version of the actual device and simulates
important AC and DC parameters. AC parameters incorporated
into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain,
and Phase. The DC parameters are IOS, total supply current, and
output voltage swing. The model uses typical parameters given in
the “Electrical Specifications” Table beginning on page 4. The
AVOL is adjusted for 90dB with the dominate pole at 125Hz. The
CMRR is set 72dB, f = 80kHz. The input stage models the actual
device to present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
Figures 23 through 30 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Large Signal 5V Step Response, and CMRR and Open-Loop Gain
Phase.
+
FIGURE 20. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
FN6800 Rev 10.00
December 8, 2016
Page 9 of 23
ISL28114, ISL28214, ISL28414
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable license to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FN6800 Rev 10.00
December 8, 2016
Page 10 of 23
1e-6
2
R1
4.0004
En
1
IN+
3
En
GAIN = 1
R5
4
M15
NCHANNELMOSFET
9 10
IN-
NCHANNELMOSFET
DN
R22
5e11
D13
+
-
R23
5e11
29
DX
V3
100
16
D2
10
+
-
CinDif
1.02E-12
0
V9
10
17
.61
EOS
GAIN = 1e-3
0
14
R6
1
15
5
6
11
12
IOS1
25e-12
Vcm
.61
R24
0.425
7
10
Vin-
10
RA2
G2A
13
G2
1
GAIN = 351
V2
I1
5e-3
Voltage Noise Stage
V4
R8
4
R7
4
R25
18
R12
1
GAIN = 334.753e-3
DX
28
8
R11
GAIN = 334.753e-3
R9
PMOSISIL
M16 PMOSISIL
M17
M14
30
+
-
RA1
+
-
+
-
GAIN = 351
G1
+
-
R21
+
-
DX
+
-
Vin+
R2
4.0004
D3
R10
1e9
D1
G1A
I2
5e-3
1e-6
D4
Cin2
1.26e-12
Cin1
1.26e-12
Input Stage
1st Gain Stage
V+
E2
+
-
+
-
GAIN = 1
0
V++
G11
.604
636.6588k
21
V5
Vg
50
D7
DX
23
26
Vmid
300e-6
E4
R14
636.6588k
+
-
D6
Page 11 of 23
C3
2E-9
+
-
DX
G6
GAIN = 24.89e-3
GAIN = 2.5118E-08
G8
22
Gain Stage
C5
1591.596
L2
10e-12
G9
D11
15.9159E-3
+
-
GAIN = 0.02
G10
+
-
G12
D12
GAIN = 0.02
GAIN = 0.02
V--
VMid Supply ref V
R18
GAIN = 6.283e-4
Correction Current
E3
+
-
Common Mode
2nd Gain Stage
V8
25
.08
R16
10e3
+
-
20
27
+
-
DY
+
-
G4
DX
V6
VOUT
ISY
D8
.604
V7
24
.08
Vc
R19
GAIN = 0.02
10e-12
GAIN = 6.283e-4
R15
10e3
GAIN = 2.5118E-08
D10
DY
GAIN = 24.89e-3
+
-
R13
C4
+
-
GAIN = 1
Sources
Pole Stage
with Zero
0
FIGURE 21. SPICE SCHEMATIC
+
-
19
R17
1591.596
+
-
DX
+
-
D9
G7
15.9159E-3
G5
DX
C2
2E-9
+
-
DX
L1
D5
G3
Output Stage
R20
50
ISL28114, ISL28214, ISL28414
V1
DX
FN6800 Rev 10.00
December 8, 2016
.
ISL28114, ISL28214, ISL28414
*ISL28114 Macromodel - covers following
*products
*ISL28114
*ISL28214
*ISL28414
**
*Revision History:
*Revision C, LaFontaine October 20th 2011
*Model for Noise to match measured part,
* quiescent supply currents,
*CMRR 72dB
*fcm=100kHz, AVOL 90dB f=125Hz, SR =
*2.5V/us, GBWP 5MHz, 2nd pole 10Mhz
output voltage clamp and short ckt current
*limit.
**
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT" Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
* Connections: +input
*
| -input
*
| | +Vsupply
*
| | | -Vsupply
*
| | | | output
*
| | | | |
.subckt ISL28114 Vin+ Vin- V+ V- VOUT
* source ISL28114_DS rev2
*
*Voltage Noise
E_En VIN+ EN 28 0 1
D_D13 29 28 DN
V_V9 29 0 0.425
R_R21 28 0 30
*
*Input Stage
M_M14 3 1 5 5 NCHANNELMOSFET
M_M15 4 VIN- 6 6 NCHANNELMOSFET
M_M16 11 VIN- 9 9 PMOSISIL
M_M17 12 1 10 10 PMOSISIL
I_I1 7 V-- DC 5e-3
I_I2 V++ 8 DC 5e-3
I_IOS VIN- 1 DC 25e-12
G_G1A V++ 14 4 3 351
G_G2A V-- 14 11 12 351
V_V1 V++ 2 1e-6
V_V2 13 V-- 1e-6
R_R1 3 2 4.0004
R_R2 4 2 4.0004
R_R3 5 7 10
R_R4 7 6 10
R_R5 9 8 10
R_R6 8 10 10
R_R7 13 11 4
R_R8 13 12 4
R_RA1 14 V++ 1
R_RA2 V-- 14 1
C_CinDif VIN- EN 1.02E-12
C_Cin1 V-- EN 1.26e-12
C_Cin2 V-- VIN- 1.26e-12
*
*1st Gain Stage
G_G1 V++ 16 15 VMID 334.753e-3
G_G2 V-- 16 15 VMID 334.753e-3
V_V3 17 16 .61
V_V4 16 18 .61
D_D1 15 VMID DX
D_D2 VMID 15 DX
D_D3 17 V++ DX
D_D4 V-- 18 DX
R_R9 15 14 100
R_R10 15 VMID 1e9
R_R11 16 V++ 1
R_R12 V-- 16 1
*
*2nd Gain Stage
G_G3 V++ VG 16 VMID 24.893e-3
G_G4 V-- VG 16 VMID 24.893e-3
V_V5 19 VG .604
V_V6 VG 20 .604
D_D5 19 V++ DX
D_D6 V-- 20 DX
R_R13 VG V++ 636.658e3
R_R14 V-- VG 636.658e3
C_C2 VG V++ 2E-09
C_C3 V-- VG 2E-09
*
*Mid supply Ref
E_E4 VMID V-- V++ V-- 0.5
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
I_ISY V+ V- DC 300e-6
*
*Common Mode Gain Stage with Zero
G_G5 V++ VC VCM VMID 2.5118E-8
G_G6 V-- VC VCM VMID 2.5118E-8
E_EOS 1 EN VC VMID 1e-3
R_R15 VC 21 10e3
R_R16 22 VC 10e3
R_R22 EN VCM 5e11
R_R23 VCM VIN- 5e11
L_L1 21 V++ 15.9159e-3
L_L2 22 V-- 15.9159e-3
*
*Pole Stage
G_G7 V++ 23 VG VMID 6.283e-4
G_G8 V-- 23 VG VMID 6.283e-4
R_R17 23 V++ 1591.596
R_R18 V-- 23 1591.596
C_C4 23 V++ 10e-12
C_C5 V-- 23 10e-12
*
*Output Stage with Correction Current
Sources
G_G9 26 V-- VOUT 23 0.02
G_G10 27 V-- 23 VOUT 0.02
G_G11 VOUT V++ V++ 23 0.02
G_G12 V-- VOUT 23 V-- 0.02
V_V7 24 VOUT .08
V_V8 VOUT 25 .08
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V++ 26 DX
D_D10 V++ 27 DX
D_D11 V-- 26 DY
D_D12 V-- 27 DY
R_R19 VOUT V++ 50
R_R20 V-- VOUT 50
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3
vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28114
FIGURE 22. SPICE NET LIST
FN6800 Rev 10.00
December 8, 2016
Page 12 of 23
ISL28114, ISL28214, ISL28414
Characterization vs Simulation Results
10,000
V+ = ±2.5V
AV = 1
1000
100
10
1
V+ = ±2.5V
AV = 1
INPUT NOISE VOLTAGE (nV/Hz)
INPUT NOISE VOLTAGE (nV/Hz)
10,000
10
100
1k
FREQUENCY (Hz)
10k
1000
100
10
100k
FIGURE 23. CHARACTERIZED INPUT NOISE VOLTAGE
70
GAIN (dB)
30
20
AV = 10
0
Rg = 10k, Rf = 100k
0
Rg = OPEN, Rf = 0
100
1k
Rg = 100k, Rf = 100k
-10
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 25. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY
10
100
LARGE SIGNAL (V)
1
VS = ±0.9V
0
RL = 10k
CL = 15pF
AV = +1
VOUT = RAIL
-2
0
1
2
3
4
5
6
TIME (µs)
8
9
FIGURE 27. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
FN6800 Rev 10.00
December 8, 2016
10
100M
1
VIN
V(VIN+)/VOUT)
-0
-1
RL = 10k
CL = 15pF
AV = +10
VOUT = RAIL
-2
7
10M
VS = ±2.5V
VOUT
2
VS = ±2.5V
-1
10k
100k
1.0M
FREQUENCY (Hz)
(A) AC sims.dat (active)
3
2
1k
FIGURE 26. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY
3
LARGE SIGNAL (V)
AV = 10
20
AV = 1
-10
10
-3
AV = 100
40
Rg = 10k, Rf = 100k
10
100k
Rg = 1k, Rf = 100k
V+ = ±2.5V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
10k
Rg = 100, Rf = 100k
AV = 1000
60
Rg = 1k, Rf = 100k
50
40
100
1k
FREQUENCY (Hz)
(A) AC sims.dat (active)
70
Rg = 100, Rf = 100k
AV = 1000
10
FIGURE 24. SIMULATED INPUT NOISE VOLTAGE
GAIN (dB)
60
1
-3
0
5
10
15
TIME (µs)
20
25
30
FIGURE 28. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs
RL, VS = ±0.9V, ±2.5V
Page 13 of 23
ISL28114, ISL28214, ISL28414
20
100
0
80
-20
GAIN
60
-40
40
-60
20
-80
0
-100
-20 V+ = ±0.9V
RL = 100k
-40
CL = 10pF
-60 SIMULATION
-80
0.1
1
10
-120
PHASE
-140
-160
100
1k
10k 100k
FREQUENCY (Hz)
1M
-180
10M 100M
120
80
GAIN
RL = 10k
40
CL = 10pF
MODEL VOS SET TO ZERO
0 FOR THIS TEST
80
70
70
60
60
50
50
30
1.0
10
100 1.0k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
(A) AC sims.dat (active)
40
30
20
20
10
0.1
FIGURE 30. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
80
40
PHASE
160
0.01
CMRR (dB)
CMRR (dB)
FIGURE 29. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
(A) AC2.dat (active)
200
OPEN-LOOP GAIN (dB)/PHASE (°)
120
PHASE (°)
OPEN-LOOP GAIN (dB)
Characterization vs Simulation Results (Continued)
10
SIMULATION
0
0.01 0.1
1
10
100 1k 10k 100k 1M
FREQUENCY (Hz)
10M 100M
FIGURE 31. SIMULATED (DESIGN) CMRR
FN6800 Rev 10.00
December 8, 2016
0
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 32. SIMULATED (SPICE) CMRR
Page 14 of 23
ISL28114, ISL28214, ISL28414
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
December 8, 2016
FN6800.10
Updated Related Literature section.
Updated third Applications bullet.
Updated Ordering Information table on page 2.
June 11, 2015
FN6800.9
Electrical Spec table, page 5 - Input Noise Voltage Density (eN) added a spec at 10kHz (typical
spec).
October 26, 2012
FN6800.8
Added SOT23-8 package on page 1 to description and features.
Ordering Information on page 2 - Added ISL28214FHZ parts and Note 5 reference.
Added Lead Finish Note to Ordering information for 8 LD SOT-23 parts.
Thermal Information on page 4 - Added 8 LD SOT-23 package with Tja and Tjc
Added P8.064 POD on page 23.
April 13, 2012
FN6800.7
Changed the low supply current in “Features” and description on page 1 from 360µA to 390µA.
Removed ISL28114FEV1Z-T7 Coming Soon parts from “Ordering Information” on page 2.
Removed applicable pinout from page 3.
On page 4, changed MIN/MAX limits for “VOS” at 25°C from -5/5mV to -4/4mV.
On page 4, changed MIN/MAX limits for “VOS” at -40°C to 125°C from -6/6mV to -5/5mV.
On page 4, changed “TCVOS” TYP from 2µV/°C to 5µV/°C.
On page 4, changed MAX limit for “IS” MAX at 25°C from 360µA to 390µA.
On page 4, changed MAX limit for “IS” MAX at -40°C to 125°C from 400µA to 475µA.
Revised Figure 8 on page 7.
Revised Figure 11 on page 7.
Revised Figure 18 on page 8.
January 3, 2012
FN6800.6
Revised “SPICE SCHEMATIC” on page 11 and “SPICE NET LIST” on page 12.
May 18, 2011
FN6800.5
- On page 3, Pin Descriptions: Circuit 3 diagram, removed anti-parallel diodes from the IN+ to INterminals.
- On page 4, Absolute Maximum Ratings: changed Differential Input Voltage from "0.5V" to "V- 0.5V to V+ + 0.5V"
- On page 4, updated CMRR and PSRR parameters in Electrical Specifications table with test
condition specifying -40°C to 125°C typical parameter.
- On page 5, updated Note 8, referenced in MIN and MAX column headings of Electrical
Specifications table, from "Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested." to new standard "Compliance to datasheet limits is assured by one or more
methods: production test, characterization and/or design."
- On page 9, under “Input ESD Diode Protection,” removed “They also contain back to-back
diodes across the input terminals.” Removed “Although the amplifier is fully protected, high
input slew rates that exceed the amplifier slew rate (±2.5V/µs) may cause output distortion.”
- On page 9, Figure 19: updated circuit schematic by removing back-to-back input protection
diodes.
- On page 11 replaced SPICE schematic (Figure 21)
- On page 12 replaced SPICE Netlist (Figure 22)
- On page 13 replaced Figure 24
- On page 14 replaced Figure 32
FN6800 Rev 10.00
December 8, 2016
CHANGE
Page 15 of 23
ISL28114, ISL28214, ISL28414
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision. (Continued)
DATE
REVISION
CHANGE
September 23, 2010
FN6800.4
Added new SC70 pinout package extension as follows:
Added to Related Literature on page 1 “See AN1547 for “ISL28414TSSOPEVAL1Z Evaluation
Board User’s Guide”.
Added to ordering information ISL28114FEV1Z-T7 and ISL28114FEV1Z-T7A and Evaluation
boards.
Added to Pin Configurations new pinout for ISL28114FEV1Z.
Added in Pin Descriptions ISL28114FEV1Z SC70 pin description column.
Changed Note 7 on page page 4 from “For JC, the “case temp” location is the center of the
exposed metal pad on the package underside.” to
“For JC, the “case temp” location is taken at the package top center.”
Added “Related Literature” on page 1.
Changed package outline drawing from MDP0038 to P5.064A on page 2 and page 18.
MDP0038 package contained 2 packages for both the 5 and 6 Ld SOT-23. MDP0038 was
obsoleted and the packages were separated and made into 2 separate package outline
drawings; P5.064A and P6.064A. Changes to the 5 Ld SOT-23 were to move dimensions from
table onto drawing, add land pattern and add JEDEC reference number.
Added Note 5 to “Ordering Information” on page 2.
December 16, 2009
FN6800.3
Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page 4.
November 17, 2009
FN6800.2
Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information”
on page 2.
November 12, 2009
FN6800.1
Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice
model (page 12).
October 23, 2009
FN6800.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
FN6800 Rev 10.00
December 8, 2016
Page 16 of 23
ISL28114, ISL28214, ISL28414
Small Outline Transistor Plastic Packages (SC70-5)
P5.049
D
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES
5
SYMBOL
4
E
CL
1
2
CL
3
e
E1
b
CL
0.20 (0.008) M
C
C
CL
A
A2
SEATING
PLANE
A1
-C-
PLATING
b1
0.043
0.80
1.10
-
0.004
0.00
0.10
-
A2
0.031
0.039
0.80
1.00
-
b
0.006
0.012
0.15
0.30
-
b1
0.006
0.010
0.15
0.25
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.009
0.08
0.20
6
D
0.073
0.085
1.85
2.15
3
E
0.071
0.094
1.80
2.40
-
E1
0.045
0.053
1.15
1.35
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0512 Ref
1.30 Ref
-
L2
c1
NOTES
0.031
0.010
0.018
0.017 Ref.
0.26
0.46
4
0.420 Ref.
0.006 BSC
0o
N
c
MAX
0.000
WITH
MIN
A
L
b
MILLIMETERS
MAX
A1
L1
0.10 (0.004) C
MIN
-
0.15 BSC
8o
0o
5
8o
-
5
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.15
0.25
Rev. 3 7/07
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
4X 1
VIEW C
0.4mm
0.75mm
For the most recent package outline drawing, see P5.049.
2.1mm
0.65mm
TYPICAL RECOMMENDED LAND PATTERN
FN6800 Rev 10.00
December 8, 2016
Page 17 of 23
ISL28114, ISL28214, ISL28414
Package Outline Drawing
For the most recent package outline drawing, see P5.064A.
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
D
A
0.08-0.20
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
2
5
(0.60)
0.20 C
2x
0.95
SEE DETAIL X
B
0.40 ±0.05
3
END VIEW
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
2.90
5
H
0.15 C A-B
2x
C
1.45 MAX
1.14 ±0.15
0.10 C
SIDE VIEW
SEATING PLANE
(0.25) GAUGE
PLANE
0.45±0.1
0.05-0.15
4
DETAIL "X"
(0.60)
(1.20)
NOTES:
(2.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN6800 Rev 10.00
December 8, 2016
Page 18 of 23
ISL28114, ISL28214, ISL28414
Package Outline Drawing
For the most recent package outline drawing, see M8.118A.
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0±0.1
8
A
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
FN6800 Rev 10.00
December 8, 2016
Page 19 of 23
ISL28114, ISL28214, ISL28414
Package Outline Drawing
For the most recent package outline drawing, see M8.15E.
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN6800 Rev 10.00
December 8, 2016
Page 20 of 23
ISL28114, ISL28214, ISL28414
Small Outline Package Family (SO)
For the most recent package outline drawing, see MDP0027.
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
NOTES:
Rev. M 2/07
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN6800 Rev 10.00
December 8, 2016
Page 21 of 23
ISL28114, ISL28214, ISL28414
Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B
D
MDP0044
A
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
For the most recent package outline drawing, see MDP0044.
0° - 8°
DETAIL X
FN6800 Rev 10.00
December 8, 2016
Page 22 of 23
ISL28114, ISL28214, ISL28414
Small Outline Transistor Plastic Packages (SOT23-8)
0.20 (0.008) M
CL
C
P8.064
VIEW C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e
b
INCHES
SYMBOL
8
7
6
5
CL
CL
E
1
2
3
E1
4
e1
C
D
CL
A
A2
SEATING
PLANE
A1
-C-
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.009
0.015
0.22
0.38
-
b1
0.009
0.013
0.22
0.33
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0768 Ref
1.95 Ref
-
L
0.10 (0.004) C
MIN
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
8
8
5
WITH
b
R
0.004
-
0.10
-
PLATING
b1
R1
0.004
0.010
0.10
0.25
0o
8o
0o
8o
c
c1
4
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
4X 1
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
For the most recent package outline drawing, see P8.064.
VIEW C
© Copyright Intersil Americas LLC 2009-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6800 Rev 10.00
December 8, 2016
Page 23 of 23
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