DATASHEET
ISL28233, ISL28433
FN7692
Rev 3.00
July 26, 2011
Dual and Quad Micropower Chopper Stabilized, RRIO Operational Amplifiers
The ISL28233 and ISL28433 are dual and quad micropower,
chopper stabilized operational amplifiers that are optimized
for single and dual supply operation from 1.8V to 6.0V and
±0.825V to ±3.0V. Their low supply current of 18µA and wide
input range enable the ISL28233, ISL28433 to be excellent
general purpose op amps for a wide range of applications. The
ISL28233 and ISL28433 are ideal for handheld devices that
operate off 2 AA or single Li-ion batteries.
Features
The ISL28233 is available in 8 Ld MSOP, 8 Ld SOIC and 8 Ld
DFN packages. The ISL28433 is available in 14 Ld TSSOP,
14 Ld SOIC and 14 Ld 3mmx4mm TDFN packages. All devices
operate over the temperature range of -40°C to +125°C.
• Low Noise (0.01Hz to 10Hz) . . . . . . . . . . . . . . . . . 1.0µVP-P, Typ.
Related Literature
• Operating Temperature Range . . . . . . . . . . . . -40°C to +125°C
• See AN1596, “ISL28233SOICEVAL1Z Evaluation Board
User’s Guide”
• See AN1575, “ISL28433SOICEVAL1Z, ISL28433TSSOPEVAL1Z
Evaluation Board User’s Guide”
• Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . 6µV, Max.
• Low Offset Drift . . . . . . . . . . . . . . . . . . . . . . . 0.05µV/°C, Max.
• Quiescent Current (Per Amplifier) . . . . . . . . . . . . . .18µA, Typ.
• Single Supply Range . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.0V
• Dual Supply Range . . . . . . . . . . . . . . . . . . . ±0.825V to ±3.0V
• Rail-to-Rail Inputs and Output
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . 180pA, Max.
Applications
• Bi-Directional Current Sense
• Temperature Measurement
• Medical Equipment
• Electronic Weigh Scales
• Precision/Strain Gauge Sensor
• Precision Regulation
• Low Ohmic Current Sense
• High Gain Analog Front Ends
Typical Application
VOS vs Temperature
4
V+
+1.8V TO +6.0V
I-SENSE+
499k
4.99k
+
0.1
4.99k
V+
VSENSE
OUT
V499k
INPUT OFFSET VOLTAGE (µV)
3
VREF
2
1
0
-1
-2
-3
GND
I-SENSE-
-4
-50
BI-DIRECTIONAL CURRENT SENSE AMPLIFIER
FN7692 Rev 3.00
July 26, 2011
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Page 1 of 25
ISL28233, ISL28433
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28233FUZ
233FZ
8 Ld MSOP
M8.118A
ISL28233FRZ
233Z
8 Ld 3mmx3mm DFN
L8.3x3J
ISL28233FBZ
28233 FBZ
8 Ld SOIC
M8.15E
ISL28433FBZ
28433 FBZ
14 Ld SOIC
MDP0027
ISL28433FVZ
28433 FVZ
14 Ld TSSOP
MDP0044
Coming Soon
ISL28433FRTZ
TBD
14 Ld 3x4 mm TDFN
TBD
ISL28233SOICEVAL1Z
Evaluation Board
ISL28433TSSOPEVAL1Z
Evaluation Board
ISL28433SOICEVAL1Z
Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28233, ISL28433. For more information on MSL please see techbrief
TB363.
FN7692 Rev 3.00
July 26, 2011
Page 2 of 25
ISL28233, ISL28433
Pin Configurations
ISL28233
(8 LD DFN)
TOP VIEW
ISL28233
(8 LD MSOP, SOIC)
TOP VIEW
- +
IN+_A 3
+ -
V- 4
OUT_A
1
8 V+
7 OUT_B
IN-_A
2
7 OUT_B
6 IN-_B
IN+_A
3
6 IN-_B
V-
4
5 IN+_B
5 IN+_B
ISL28433
(14 LD TDFN)
TOP VIEW
ISL28433
(14 LD SOIC)
TOP VIEW
IN-_A 2
- +
+ -
IN+_A 3
IN+_B 5
- +
+ -
OUT_B 7
13 IN-_D
IN-_A 2
12 IN+_D
IN+_A 3
14 OUT_D
- +
+ -
10 IN+_C
IN+_B 5
9
IN-_C
IN-_B 6
8
OUT_C
OUT_B 7
13 IN-_D
12 IN+_D
V+ 4
11 V-
V+ 4
IN-_B 6
OUT_A 1
14 OUT_D
OUT_A 1
11 V10 IN+_C
+ -
IN-_A 2
8 V+
- +
OUT_A 1
9
IN-_C
8
OUT_C
ISL28433
(14 LD TSSOP)
TOP VIEW
OUT_A 1
IN-_A 2
14 OUT_D
- +
+ -
IN+_A 3
12 IN+_D
V+ 4
11 V-
IN+_B 5
FN7692 Rev 3.00
July 26, 2011
+ -
OUT_B 7
10 IN+_C
- +
IN-_B 6
13 IN-_D
9
IN-_C
8
OUT_C
Page 3 of 25
ISL28233, ISL28433
Pin Descriptions
ISL28233
(8 LD MSOP,
SOIC, DFN)
ISL28433
(14 LD TSSOP,
SOIC, TDFN)
PIN
NAME
FUNCTION
3
3
IN+_A
Non-inverting input
5
5
IN+_B
-
10
IN+_C
-
12
IN+_D
EQUIVALENT CIRCUIT
V+
+
+
IN+
-
IN-
CLOCK GEN + DRIVERS
VCircuit 1
4
11
V-
Negative supply
2
2
IN-_A
Inverting input
6
6
IN-_B
-
9
IN-_C
-
13
IN-_D
1
1
OUT_A
7
7
OUT_B
-
8
OUT_C
-
14
OUT_D
(See Circuit 1)
Output
V+
OUT
VCircuit 2
8
4
V+
-
-
PAD
FN7692 Rev 3.00
July 26, 2011
Positive supply
Thermal Pad
Thermal Pad. Connect to most negative supply. TDFN and
DFN packages only.
Page 4 of 25
ISL28233, ISL28433
Absolute Maximum Ratings
Thermal Information
Max Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . (V- - 0.3V) to (V+ + 0.3V)V
Max Input Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0V
ESD Tolerance
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 4000V
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . 2000V
Latch-Up (Tested per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
14 Ld TSSOP (Notes 4, 7) . . . . . . . . . . . . . .
110
40
14 Ld SOIC (Notes 4, 7) . . . . . . . . . . . . . . . .
75
47
14 Ld TDFN (Notes 5, 6) . . . . . . . . . . . . . . .
TBD
TBD
8 Ld MSOP (Notes 4, 7) . . . . . . . . . . . . . . . .
180
65
8 Ld SOIC (Notes 4, 7) . . . . . . . . . . . . . . . . .
125
90
8 Ld DFN (Notes 5, 6). . . . . . . . . . . . . . . . . .
53
12
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ unless otherwise specified. Boldface limits apply over
the operating temperature range,-40°C to +125°C.
MIN
PARAMETER
DESCRIPTION
CONDITIONS
MAX
(Note 8) TYP (Note 8)
UNIT
DC SPECIFICATIONS
VOS
TCVOS
IOS
TCIOS
IB
TCIB
Input Offset Voltage
Input Offset Voltage Temperature Coefficient
PSRR
±2
6
µV
T = -40°C to +125°C
-11
-
11
µV
T = -40°C to +125°C
-0.05
0.01
0.05
µV/°C
-
10
-
pA
Input Offset Current
Input Offset Current Temperature Coefficient
T = -40°C to +85°C
-
0.11
-
pA/°C
Input Bias Current
T = -40°C to +85°C
-180
-
180
pA
T = -40°C to +125°C
-600
-
600
pA
T = -40°C to +85°C
-
0.49
-
pA/°C
V+ = 5.0V, V- = 0V
Guaranteed by CMRR
-0.1
-
5.1
V
VCM = -0.1V to 5.1V
118
125
-
dB
115
-
-
dB
110
138
-
dB
110
-
-
dB
Input Bias Current Temperature Coefficient
CMIR
CMRR
-6
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Vs = 1.8V to 6.0V
VOH
Output Voltage, High
4.965
4.981
-
V
VOL
Output Voltage, Low
-
18
35
mV
AOL
Open Loop Gain
RL = 1M
-
174
-
dB
V+
Supply Voltage
Guaranteed by PSRR
1.8
-
6.0
V
IS
Supply Current, Per Amplifier
RL = OPEN
-
18
25
µA
-
-
35
µA
FN7692 Rev 3.00
July 26, 2011
Page 5 of 25
ISL28233, ISL28433
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ unless otherwise specified. Boldface limits apply over
the operating temperature range,-40°C to +125°C. (Continued)
MIN
PARAMETER
DESCRIPTION
CONDITIONS
MAX
(Note 8) TYP (Note 8)
UNIT
ISC+
Output Source Short Circuit Current
RL = Short to V-
13
17
26
mA
ISC-
Output Sink Short Circuit Current
RL = Short to V+
-26
-19
-13
mA
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
AV = 100, RF = 100kRG = 1k
RL = 10kto VCM
-
400
-
kHz
eN VP-P
Peak-to-Peak Input Noise Voltage
f = 0.01Hz to 10Hz
-
1.0
-
µVP-P
eN
Input Noise Voltage Density
f = 1kHz
-
65
-
nV/(Hz)
iN
Input Noise Current Density
f = 1kHz
-
72
-
fA/(Hz)
f = 10Hz
-
79
-
fA/(Hz)
f = 1MHz
-
1.6
-
pF
-
1.12
-
pF
-
0.2
-
V/µs
-
0.1
-
V/µs
-
1.1
-
µs
-
1.1
-
µs
Cin
Differential Input Capacitance
Common Mode Input Capacitance
TRANSIENT RESPONSE
SR
Positive Slew Rate
VOUT = 1V to 4V, RL = 10k
Negative Slew Rate
tr, tf, Small Signal Rise Time, tr 10% to 90%
Fall Time, tf 10% to 90%
tr, tf Large Signal
AV = +1, VOUT = 2VP-P RF = 0
RL = 10kCL = 1.2pF
-
20
-
µs
-
30
-
µs
Settling Time to 0.1%, 2VP-P Step
AV = +1, RF = 0RL = 10kCL = 1.2pF
-
35
-
µs
Output Overload Recovery Time, Recovery to 90%
of output saturation
AV = +2, RF = 10kRL = OpenCL = 3.7pF
-
10.5
-
µs
Rise Time, tr 10% to 90%
Fall Time, tf 10% to 90%
ts
trecover
AV = +1, VOUT = 0.1VP-P RF = 0
RL = 10kCL = 1.2pF
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7692 Rev 3.00
July 26, 2011
Page 6 of 25
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified.
4
4
3
3
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
n
2
1
0
-1
-2
-3
-4
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2
1
0
-1
-2
VS = ±0.825V
VIN = 0V
-3
RL = OPEN
-4
-50
6.0
-25
0
SUPPLY VOLTAGE (V)
25
50
75
TEMPERATURE (°C)
100
125
100
125
100
125
FIGURE 2. VOS vs TEMPERATURE
FIGURE 1. VOS vs SUPPLY VOLTAGE
400
4
INPUT BIAS CURRENT (pA)
INPUT OFFSET VOLTAGE (µV)
3
2
1
0
-1
-2
VS = ±2.5V
VIN = 0V
RL = OPEN
-3
-4
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
300
200
100
VS = ±0.825V
0
-100
-50
125
VS = ±2.5V
-25
50
75
FIGURE 4. IB+ vs TEMPERATURE
400
INPUT OFFSET CURRENT (pA)
100
300
INPUT BIAS CURRENT (pA)
25
TEMPERATURE (°C)
FIGURE 3. VOS vs TEMPERATURE
200
VS = ±2.5V
VS = ±0.825V
100
0
-100
-50
0
-25
0
25
50
75
TEMPERATURE (°C)
FIGURE 5. IB- vs TEMPERATURE
FN7692 Rev 3.00
July 26, 2011
100
125
VS = ±2.5V
50
VS = ±0.825V
0
-50
-100
-150
-50
-25
0
25
50
75
TEMPERATURE (°C)
FIGURE 6. IOS vs TEMPERATURE
Page 7 of 25
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
PER AMPLIFIER
SUPPLY CURRENT (µA)
35
VS = ±2.5V
30
VS = ±0.825V
25
20
15
10
-50
-25
0
25
50
75
100
125
PEAK TO PEAK NOISE VOLTAGE (nV)
1000
40
VS = 5V
800 RL = 100k
CL = 3.7pF
600 Rg = 10, Rf = 100k
AV = 10,000
400
200
0
-200
-400
-600
-800
-1000
0.1
10
20
30
40
TEMPERATURE (°C)
INPUT NOISE CURRENT (pA/Hz)
INPUT NOISE VOLTAGE (nV/Hz)
VS = 5V
AV = 1
100
10
0.001
0.01
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
90
100
VS = 5V
AV = 1
0.1
0.01
0.001
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 9. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY
FIGURE 10. INPUT NOISE CURRENT DENSITY vs FREQUENCY
200
200
150
OPEN LOOP GAIN (dB)/PHASE (°)
OPEN LOOP GAIN (dB)/PHASE (°)
80
1.0
1000
PHASE
100
50
GAIN
0
-100
0.1m
70
FIGURE 8. INPUT NOISE VOLTAGE 0.01Hz TO 10Hz
FIGURE 7. SUPPLY CURRENT vs TEMPERATURE
-50
50
60
TIME (s)
RL = 10k
CL = 100pF
SIMULATION
1m 10m 100m 1
10
100
1k
10k 100k 1M
FREQUENCY (Hz)
FIGURE 11. FREQUENCY RESPONSE vs OPEN LOOP GAIN,
RL = 10kΩ
FN7692 Rev 3.00
July 26, 2011
10M
150
PHASE
100
50
GAIN
0
-50
-100
0.1m
RL = 10M
CL = 100pF
SIMULATION
1m 10m 100m 1
10 100 1k
FREQUENCY (Hz)
10k 100k 1M
FIGURE 12. FREQUENCY RESPONSE vs OPEN LOOP GAIN,
RL = 10MΩ
Page 8 of 25
10M
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
1
1
0
NORMALIZED GAIN (dB)
RL = 1k
-2
NORMALIZED GAIN (dB)
RL = 100k
-1
RL = OPEN
RL = 10k
-3
-4
RL = 49.9k
-5
VS = ±0.8V
CL = 3.7pF
AV = +1
VOUT = 10mVP-P
-6
-7
-8
-9
100
1k
RL = 100k
0
RL = 1k
-1
-2
RL = 10k
-4
RL = 49.9k
-5
VS = ±2.5V
CL = 3.7pF
AV = +1
VOUT = 10mVP-P
-6
-7
-8
10k
100k
1M
-9
100
10M
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. GAIN vs FREQUENCY vs RL, VS = ±0.8V
0
8
-1
GAIN (dB)
6
NORMALIZED GAIN (dB)
Rf = Rg = 1k
7
Rf = Rg = 10k
5
4
1
0
100
Rf = Rg = 100k
VS = ±2.5V
RL = 100k
CL = 3.7pF
AV = +2
VOUT = 10mVP-P
1k
-3
10k
100k
FREQUENCY (Hz)
1M
-5
-7
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 16. GAIN vs FREQUENCY vs VOUT, RL = OPEN
Rg = 100, Rf = 100k
0
NORMALIZED GAIN (dB)
GAIN (dB)
VOUT = 10mV
VS = ±2.5V
RL = OPEN
CL = 3.7pF
AV = 1
-1
Rg = 1k, Rf = 100k
AV = 100
V+ = 5V
CL = 3.7pF
RL = 100k
VOUT = 10mVP-P
AV = 10
Rg = 10k, Rf = 100k
10
-10
10
VOUT = 100mV
1
AV = 1000
30
0
VOUT = 250mV
-6
-9
100
10M
50
20
VOUT = 500mV
-4
-8
70
40
VOUT = 1V
-2
FIGURE 15. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES
Rf/Rg
60
10M
1
9
2
1M
FIGURE 14. GAIN vs FREQUENCY vs RL, VS = ±2.5V
10
3
RL = OPEN
-3
AV = 1
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 17. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FN7692 Rev 3.00
July 26, 2011
VS = ±0.8V
-3
-4
VS= ±1.5V
-5
VS = ±2.75V
-6
RL = 100k
CL = 3.7pF
AV = +1
VOUT = 10mVP-P
-7
-8
Rg = OPEN, Rf = 0
100
VS = ±0.7V
-2
-9
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 18. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
Page 9 of 25
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
20
8
CL = 824pF
0
CL = 474pF
4
-20
CL = 224pF
2
CMRR (dB)
NORMALIZED GAIN (dB)
6
0
-2
CL = 104pF
-4
CL = 51pF
VS = ±2.5V
-6 R = 100k
L
-8 AV = +1
VOUT = 10mVP-P
-10
100
1k
SIMULATION
-60
-80
-100
CL = 3.7pF
10k
-40
VS = ±2.5V
RL = 100k
AV = +1
VCM = 1VP-P
-120
100k
1M
-140
100
10M
1k
10k
FREQUENCY (Hz)
FIGURE 19. GAIN vs FREQUENCY vs C L
0
-10
-10
-20
-20
PSRR (dB)
PSRR (dB)
-50
-60
-70
PSRR+
-80
-90
100
10M
-30
PSRR-
-40
-100
10
1M
FIGURE 20. CMRR vs FREQUENCY, V S = ±2.5V
0
-30
100k
FREQUENCY (Hz)
VS = ±0.8V
RL = 100k
CL = 16.3pF
AV = +1
VCM = 1VP-P
1k
10k
100k
FREQUENCY (Hz)
1M
-40
-50
PSRR+
-60
VS = ±2.5V
RL = 100k
CL = 16.3pF
AV = +1
VCM = 1VP-P
-70
-80
PSRR-
-90
-100
-110
10
10M
FIGURE 21. PSRR vs FREQUENCY, VS = ±0.8V
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 22. PSRR vs FREQUENCY, VS = ±2.5V
155
160
150
150
PSRR (dB)
CMRR (dB)
140
145
140
VS = ±2.5V
VCM = ±2.6V
135
130
-50
-25
0
25
50
75
TEMPERATURE (°C)
FIGURE 23. CMRR vs TEMPERATURE
FN7692 Rev 3.00
July 26, 2011
100
130
120
110
125
VS = 1.8V to 6.0V
100
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
FIGURE 24. PSRR vs TEMPERATURE
Page 10 of 25
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
5.0
4.5
4.0
SIGNAL (V)
3.5
3.0
2.5
2.0
RL = 100k
CL = 3.7pF
AV = 1
VOUT = 4VP-P
1.5
1.0
0.5
0
0
50
100
150
200
250
TIME (µs)
300
350
400
FIGURE 25. LARGE SIGNAL STEP RESPONSE (4V)
0.14
1.2
0.12
1.0
0.10
0.6
SIGNAL (V)
SIGNAL (V)
0.8
RL = 100k
CL = 3.7pF
AV = 1
VOUT = 1VP-P
0.4
0.02
0
10
20
30
40
50
60
TIME (µs)
70
80
90
0
0
100
FIGURE 26. LARGE SIGNAL STEP RESPONSE (1V)
4.995
10
15
20
25
TIME (µs)
30
35
40
40
VS =5V
RL = 10kΩ
35
4.990
4.985
4.980
4.975
-50
5
FIGURE 27. SMALL SIGNAL STEP RESPONSE (100mV)
VOL (mV)
5.000
VOH (V)
RL = 100k
CL = 3.7pF
AV = 1
VOUT = 100mVP-P
0.06
0.04
0.2
0
0.08
VS = 5V
RL = 10kΩ
30
25
20
-25
0
25
50
75
TEMPERATURE (°C)
FIGURE 28. VOH vs TEMPERATURE
FN7692 Rev 3.00
July 26, 2011
100
125
15
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
FIGURE 29. VOL vs TEMPERATURE
Page 11 of 25
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
-20
-20
-40
-40
Vs = ±0.8V
RL = OPEN
CL = 3.7pF
AV = 1
VOUT = 1VP-P
-60
CROSSTALK (dB)
-80
-100
-60
-80
-100
-120
-120
-140
1k
10k
100k
FREQUENCY (Hz)
-140
1k
1M
FIGURE 30. CROSSTALK vs FREQUENCY, VS = ±0.8V
10k
100k
FREQUENCY (Hz)
12
14
TA = -40°C to +85°C
TA = -40°C to +85°C
12
FREQUENCY (UNITS)
8
6
4
2
10
8
6
4
2
0
TCIOS (pA/°C)
0.70
0.66
FIGURE 33. TCIB HISTOGRAM
40
40
TA = -40°C to +125°C
INPUT OFFSET CURRENT (pA)
FREQUENCY (UNITS)
0.58
TCIB (pA/°C)
FIGURE 32. TCIOS HISTOGRAM
30
25
20
15
10
5
0
0.54
0.50
0.42
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
-0.04
0
0.46
FREQUENCY (UNITS)
10
35
1M
FIGURE 31. CROSSTALK vs FREQUENCY, VS = ±2.5V
0.62
CROSSTALK (dB)
Vs = ±2.5V
RL = OPEN
CL = 3.7pF
AV = 1
VOUT = 1VP-P
-40 -35 -30 -25 -20 -15 -10 -5
0
5
10 15 20 25 30 35
TCVOS (nV/°C)
FIGURE 34. TCVOS HISTOGRAM
FN7692 Rev 3.00
July 26, 2011
30
20
10
0
-10
-20
-30
-40
-0.5
0.5
1.5
2.5
3.5
COMMON MODE VOLTAGE (V)
4.5
FIGURE 35. IOS vs VCM
Page 12 of 25
5.5
ISL28233, ISL28433
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
40
20
15
IB- BIAS CURRENT (pA)
IB+ BIAS CURRENT (pA)
30
20
10
0
-10
-20
-0.5
10
5
0
-5
-10
-15
0.5
1.5
2.5
3.5
4.5
-20
-0.5
5.5
0.5
1.5
2.5
3.5
4.5
5.5
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
FIGURE 36. IB+ vs VCM
FIGURE 37. IB- vs VCM
6
INPUT OFFSET VOLTAGE (µV)
4
2
0
-2
-4
-6
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
COMMON MODE VOLTAGE (V)
FIGURE 38. VOS vs VCM
MAIN AMPLIFIER
5kHz CROSSOVER
FILTER
IN-
VOUT
IN+
CHOPPER STABILIZED DC OFFSET CORRECTION
FIGURE 39. ISL28233, ISL28433 FUNCTIONAL BLOCK DIAGRAM
FN7692 Rev 3.00
July 26, 2011
Page 13 of 25
ISL28233, ISL28433
Applications Information
High Gain, Precision DC-Coupled Amplifier
Functional Description
The circuit in Figure 41 implements a single-stage DC-coupled
amplifier with an input DC sensitivity of under 100nV that is only
possible using a low VOS amplifier with high open loop gain. High
gain DC amplifiers operating from low voltage supplies are not
practical using typical low offset precision op amps. For example,
a typical precision amplifier in a gain of 10kV/V with a ±100µV
VOS and offset drift 0.5µV/°C of a low offset op amp would
produce a DC error of >1V with an additional 5mV/°C of
temperature dependent error making it difficult to resolve DC
input voltage changes in the mV range.
The ISL28233 and ISL28433 use a proprietary
chopper-stabilized technique (see Figure 39) that combines a
400kHz main amplifier with a very high open loop gain (174dB)
chopper amplifier to achieve very low offset voltage and drift
(2µV, 0.01µV/°C typical) while consuming only 18µA of supply
current per channel.
This multi-path amplifier architecture contains a time continuous
main amplifier whose input DC offset is corrected by a parallelconnected, high gain chopper stabilized DC correction amplifier
operating at 100kHz. From DC to ~5kHz, both amplifiers are active
with DC offset correction and most of the low frequency gain is
provided by the chopper amplifier. A 5kHz crossover filter cuts off
the low frequency amplifier path leaving the main amplifier active
out to the 400kHz gain-bandwidth product of the device.
The key benefits of this architecture for precision applications are
very high open loop gain, very low DC offset, and low 1/f noise.
The noise is virtually flat across the frequency range from a few
millihertz out to 100kHz, except for the narrow noise peak at the
amplifier crossover frequency (5kHz).
The ±6µV max VOS and 0.05µV/°C max temperature drift of the
ISL28233, ISL28433 produces a temperature stable maximum
DC output error of only ±60mV with a maximum output
temperature drift of 0.5mV/°C. The additional benefit of a very
low 1/f noise corner frequency and some feedback filtering
enables DC voltages and voltage fluctuations well below 100nV
to be easily detected with a simple single stage amplifier.
CF
0.018µF
1M,
+2.5V
Rail-to-rail Input and Output (RRIO)
The RRIO CMOS amplifier uses parallel input PMOS and NMOS that
enable the inputs to swing 100mV beyond either supply rail. The
inverting and non-inverting inputs do not have back-to-back input
clamp diodes and are capable of maintaining high input impedance
at high differential input voltages. This is effective in eliminating
output distortion caused by high slew-rate input signals.
The output stage uses common source connected PMOS and
NMOS devices to achieve rail-to-rail output drive capability with
17mA current limit and the capability to swing to within 20mV of
either rail while driving a 10k load.
IN+ and IN- Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications where
either input is expected to exceed the rails by 0.5V, an external
series resistor must be used to ensure the input currents never
exceed 20mA (see Figure 40).
VIN
RIN
+
VOUT
RL
FIGURE 40. INPUT CURRENT LIMITING
Layout Guidelines for High Impedance Inputs
To achieve the maximum performance of the high input
impedance and low offset voltage of the ISL28233 and ISL28433
amplifiers, care should be taken in the circuit board layout. The PC
board surface must remain clean and free of moisture to avoid
leakage currents between adjacent traces. Surface coating of the
circuit board will reduce surface moisture and provide a humidity
barrier, reducing parasitic resistance on the board.
FN7692 Rev 3.00
July 26, 2011
VIN
100
1M
VOUT
RL
+
100
-2.5V
ACL = 10kV/V
FIGURE 41. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER
ISL28233, ISL28433 SPICE Model
Figure 42 shows the SPICE model schematic and Figure 43
shows the net list for the ISL28233, ISL28433 SPICE model. The
model is a simplified version of the actual device and simulates
important parameters such as noise, Slew Rate, Gain and Phase.
The model uses typical parameters from the “Electrical
Specifications Table” on page 5. The poles and zeroes in the
model were determined from the actual open and closed-loop
gain and phase response. This enables the model to present an
accurate AC representation of the actual device. The model is
configured for ambient temperature of +25°C.
Figures 44 through 51 show the characterization vs simulation
results for the Noise Density, Frequency Response vs Close Loop
Gain, Gain vs Frequency vs CL and Large Signal Step Response (4V).
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
Page 14 of 25
ISL28233, ISL28433
The Licensee may not sell, loan, rent, or license the macro-model, in
whole, in part, or in modified form, to anyone outside the Licensee’s
company. The Licensee may modify the macro-model to suit his/her
specific applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental, or
consequential damages in connection with or arising out of the use
of this macro-model. Intersil reserves the right to make changes to
the product and the macro-model without prior notice.
FN7692 Rev 3.00
July 26, 2011
Page 15 of 25
ISL28233, ISL28433
V16
V15
Dn2
7
Dn1
I2
R22
I1
R21
R1
R2
+
-
+
-
Vin+
M1
En
M2
Cin1
Cin2
13
Vin-
12
R3
R4
4
Input Stage
Voltage Noise
7
7
+
+
D2
R6
-
R8
-
G2
D4
C1
G4
V4
V6
13
VV3
12
16
-
V3
G1
-
R5
D1
+
V5
G3
R7
C2
+
D3
4
4
SR Limit & First Pole
Gain Stage
7
+
-
R12
L1
+
G8
G5
D7
R14
+
D8
G10
C3
V+
R16
R11
VV3
Vout
16
R10
E1
+
+
-
G7
-
G5
+
4
R9
L2
R13
+
C4
G9
+
-
D6
D5
G10
+
-
G11
+
R15
VZero/Pole
Pole
Output Stage
FIGURE 42. SPICE CIRCUIT SCHEMATIC
FN7692 Rev 3.00
July 26, 2011
Page 16 of 25
ISL28233, ISL28433
* ISL28233, ISL28433 Macromodel
* Revision B, April 2009
* AC characteristics, Voltage Noise
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections:
+input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28233
3
2
7
4
6
*
*Voltage Noise
D_DN1
102 101 DN
D_DN2
104 103 DN
R_R21
0 101 120k
R_R22
0 103 120k
E_EN
8 3 101 103 1
V_V15
102 0 0.1Vdc
V_V16
104 0 0.1Vdc
*
*Input Stage
C_Cin1
8 0 0.4p
C_Cin2
2 0 2.0p
R_R1
9 10 10
R_R2
10 11 10
R_R3
4 12 100
R_R4
4 13 100
M_M1
12 8 9 9 pmosisil
+ L=50u
+ W=50u
M_M2
13 2 11 11 pmosisil
+ L=50u
+ W=50u
I_I1
4 7 DC 92uA
I_I2
7 10 DC 100uA
*
*Gain stage
G_G1
4 VV2 13 12 0.0002
G_G2
7 VV2 13 12 0.0002
R_R5
4 VV2 1.3Meg
R_R6
VV2 7 1.3Meg
D_D1
4 14 DX
D_D2
15 7 DX
V_V3
VV2 14 0.7Vdc
V_V4
15 VV2 0.7Vdc
*
*SR limit first pole
G_G3
4 VV3 VV2 16 1
G_G4
7 VV3 VV2 16 1
R_R7
4 VV3 1meg
R_R8
VV3 7 1meg
C_C1
VV3 7 12u
C_C2
4 VV3 12u
D_D3
4 17 DX
D_D4
18 7 DX
V_V5
VV3 17 0.7Vdc
V_V6
18 VV3 0.7Vdc
*
*Zero/Pole
E_E1
16 4 7 4 0.5
G_G5
4 VV4 VV3 16 0.000001
G_G6
7 VV4 VV3 16 0.000001
L_L1
20 7 0.3H
R_R12
20 7 2.5meg
R_R11
VV4 20 1meg
L_L2
4 19 0.3H
R_R9
4 19 2.5meg
R_R10
19 VV4 1meg
*Pole
G_G7
4 VV5 VV4 16 0.000001
G_G8
7 VV5 VV4 16 0.000001
C_C3
VV5 7 0.12p
C_C4
4 VV5 0.12p
R_R13
4 VV5 1meg
R_R14
VV5 7 1meg
*
*Output Stage
G_G9
21 4 6 VV5 0.0000125
G_G10
22 4 VV5 6 0.0000125
D_D5
4 21 DY
D_D6
4 22 DY
D_D7
7 21 DX
D_D8
7 22 DX
R_R15
4 6 8k
R_R16
6 7 8k
G_G11
6 4 VV5 4 -0.000125
G_G12
7 6 7 VV5 -0.000125
*
.model pmosisil pmos (kp=16e-3 vto=10m)
.model DN D(KF=6.4E-16 AF=1)
.MODEL DX D(IS=1E-18 Rs=1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28233
FIGURE 43. SPICE NET LIST
v
FN7692 Rev 3.00
July 26, 2011
Page 17 of 25
ISL28233, ISL28433
Characterization vs Simulation Results
1000
V+ = 5V
AV = 1
100
10
0.001
V+ = 5V
AV = 1
INPUT NOISE VOLTAGE (nV/Hz
INPUT NOISE VOLTAGE (nV/Hz
1000
0.01
0.1
1
10
100
1k
10k
100
10
0.1
100k
1
FIGURE 44. CHARACTERIZED INPUT NOISE VOLTAGE DENSITY
vs FREQUENCY
70
AV = 1000
Rg = 100, Rf = 100k
AV = 10
Rg = 10k, Rf = 100k
10
0
GAIN (dB)
GAIN (dB)
V+ = 5V
CL = 3.7pF
RL = 100k
VOUT = 10mVP-P
30
20
50
Rg = 1k, Rf = 100k
AV = 100
40
30
Rg = OPEN, Rf = 0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 46. CHARACTERIZED FREQUENCY RESPONSE vs
CLOSED LOOP GAIN
AV = 1
Rg = 10M Rf = 1
100
1k
10k
100k
FREQUENCY (Hz)
0
-2
-4
V+ = 5V
-6 RL = 100k
AV = +1
-8 V
OUT = 10mVP-P
1k
CL = 104pF
CL = 51pF
CL = 3.7pF
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 48. CHARACTERIZED GAIN vs FREQUENCY vs C L
FN7692 Rev 3.00
July 26, 2011
1M
10M
FIGURE 47. SIMULATED FREQUENCY RESPONSE vs CLOSED
LOOP GAIN
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Rg = 10k, Rf = 100k
AV = 10
CL = 824pF
6
2
-10
100
Rg = 1k, Rf = 100k
8
CL = 824pF
CL
CL = 474pF
CL = 224pF
4
100k
Rg = 100, Rf = 100k
AV = 100
-10
10
8
6
10k
10
0
100
1k
20
AV = 1
-10
10
AV = 1000
60
50
40
100
FIGURE 45. SIMULATED INPUT NOISE VOLTAGE DENSITY vs
FREQUENCY
70
60
10
FREQUENCY (Hz)
FREQUENCY (Hz)
CL = 474pF
4
CL
C
L = 224pF
2
0
-2
-4
-6
CL = 3.7pF
-8
-10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 49. SIMULATED GAIN vs FREQUENCY vs CL
Page 18 of 25
ISL28233, ISL28433
5.0
5.0
4.5
4.5
4.0
4.0
3.5
3.5
3.0
LARGE SIGNAL (V)
LARGE SIGNAL (V)
Characterization vs Simulation Results (Continued)
V+ = 5V
RL = 100k
CL = 3.7pF
AV = 1
VOUT = 4VP-P
2.5
2.0
1.5
1.0
VOUT
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0
VIN
0
50
100
150
200
250
300
350
400
TIME (µs)
FIGURE 50. CHARACTERIZED LARGE SIGNAL STEP RESPONSE (4V)
FN7692 Rev 3.00
July 26, 2011
0
0
50
100
150
200
250
300
350
400
TIME (µs)
FIGURE 51. SIMULATED LARGE SIGNAL STEP RESPONSE (4V)
Page 19 of 25
ISL28233, ISL28433
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
5/31/11
FN7692.3
3/24/11
12/2/10
CHANGE
Changed minimum operating supply voltage from +1.65V to +1.8V throughout entire datasheet.
Added to Ordering Information Table on page 2 - ISL28233SOICEVAL1Z, ISL28433TSSOPEVAL1Z,
ISL28433SOICEVAL1Z
FN7692.2
Added “Related Literature” on page 1
Removed "Coming Soon" from ISL28233FRZ device (8 Ld DFN) in "Ordering Information" on page 2.
Corrected Thermal Pad Pin Name in “Pin Descriptions” on page 4 from "NC" to "PAD"
Corrected JA note for TDFN package in “Thermal Information” on page 5 from "JA is measured with the
component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for
details." To "JA is measured in free air with the component mounted on a high effective thermal conductivity
test board with "direct attach" features. See Tech Brief TB379." (since TDFN has thermal pad; TDFN package
option not released yet)
10/27/10
FN7692.1
Changed Part Marking for ISL28233FUZ from 8233Z to 233FZ in “Ordering Information” table on page 2
Added ISL28233 in DFN package to Ordering Information” table on page 2.
On page 6, removed Note 8.
Changed note in MIN MAX columns of “Electrical Specifications” table from:
“Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.”
To:
"Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or
design."
8/25/10
FN7692.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL28233, ISL28433
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
© Copyright Intersil Americas LLC 2010-2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7692 Rev 3.00
July 26, 2011
Page 20 of 25
ISL28233, ISL28433
Package Outline Drawing
L8.3x3J
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0 9/09
2X 1.950
3.00
B
0.15
8
5
3.00
(4X)
6X 0.65
A
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
4
8X 0.30
8X 0.400 ± 0.10
TOP VIEW
6
PIN #1 INDEX AREA
1
4
0.10 M C A B
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
0.10 C
Max 1.00
C
0.08 C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
C
0 . 2 REF
5
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
FN7692 Rev 3.00
July 26, 2011
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Page 21 of 25
ISL28233, ISL28433
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN7692 Rev 3.00
July 26, 2011
Page 22 of 25
ISL28233, ISL28433
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0±0.1
8
A
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
FN7692 Rev 3.00
July 26, 2011
Page 23 of 25
ISL28233, ISL28433
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
MILLIMETERS
(N/2)+1
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN7692 Rev 3.00
July 26, 2011
Page 24 of 25
ISL28233, ISL28433
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
NOTES:
Rev. M 2/07
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7692 Rev 3.00
July 26, 2011
Page 25 of 25
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