ISL43L840IR

DATASHEET ISL43L840 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Dual 4 to 1 Analog Multiplexer The Intersil ISL43L840 device is a precision, bidirectional, analog switch configured as a dual 4-channel multiplexer/demultiplexer, designed to operate from a single +1.6V to +3.6V supply. ON resistance is 0.5 with a +3V supply and 0.62 with a single +1.8V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 4nA max at +25°C and 30nA max at +85°C with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL43L840 is a dual 4 to 1 multiplexer device that is offered in a 16 Ld TSSOP and 16 Ld 3x3 QFN packages. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANCE ISL43L840 FN6096 Rev 1.00 October 12, 2004 Features • ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62 • RON Matching Between Channels. . . . . . . . . . . . . . . . .0.12 • RON Flatness Across Signal Range . . . . . . . . . . . . . .0.056 • Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V • Low Power Consumption (PD). . . . . . . . . . . . . . . . . . 4kV Thermal Resistance (Typical, Note 3) JA (°C/W) 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 16 Ld 3x3 QFN Package . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range ISL43L840IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on Ax, Bx, COMx, ADDx exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified TEMP (°C) (NOTE 5) MIN TYP Full 0 - V+ V 25 - 0.5 0.75  Full - - 0.8  25 - 0.12 0.2  Full - - 0.2  25 - 0.056 0.15  Full - - 0.15  25 -4 - 4 nA Full -30 - 30 nA 25 -8 - 8 nA Full -60 - 60 nA Input Voltage High, VINH, VADDH Full 1.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.5 V V+ = 3.6V, VINH = VADD = 0V or V+ (Note 10) Full -0.5 - 0.5 A V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10)) 25 - 19 28 ns Full - - 30 ns 25 - 4 - ns Full 1 - - ns PARAMETER TEST CONDITIONS (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 2.7V, ICOM = 100mA, VAx or VBx = 0V to V+, (See Figure 5) RON Matching Between Channels, RON V+ = 2.7V, ICOM = 100mA, VAx or VBx = Voltage at max RON, (Note 6) RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VAx or VBx = 0V t0 V+, (Note 7) Ax or Bx OFF Leakage Current, IAx(OFF) or IBx(OFF) V+ = 3.3V, VCOM = 0.3V, 3V, VAx or VBx = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 3.3V, VCOM = VAx or VBx = 0.3V, 3V DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 3.3V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 10) Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - -96 - pC Input OFF Capacitance, COFF f = 1MHz, VAx or VBx = VCOM = 0V, (See Figure 7) 25 - 62 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VAx or VBx = VCOM = 0V, (See Figure 7) 25 - 232 - pF FN6096 Rev 1.00 October 12, 2004 Page 3 of 11 ISL43L840 Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified (Continued) TEMP (°C) (NOTE 5) MIN TYP RL = 50, CL = 35pF, f = 100kHz, (See Figures 4 and 6) 25 - 65 - dB 25 - -100 - dB f = 20Hz to 20kHz, 0.5Vp-p, RL = 32 25 - 0.02 - % Full 1.6 - 3.6 V 25 - - 0.05 A Full - - 0.9 A PARAMETER OFF Isolation Crosstalk, (Note 9) Total Harmonic Distortion (THD) TEST CONDITIONS (NOTE 5) MAX UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. 10. Guaranteed but not tested. Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4, 8), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP MIN (°C) (NOTE 5) TYP MAX UNIT (NOTE 5) S ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Full 0 - V+ V 25 - 0.62 0.85  Full - - 0.9  25 - 0.12 -  Full - 0.12 -  25 - 0.14 -  Full - 0.14 -  Input Voltage High, VINH, VADDH Full 1 - - V Input Voltage Low, VINL, VADDL Full - - 0.4 V Input Current, IINH, IINL, IADDH, IADDL V+ = 1.8V, VINH, VADD = 0V or V+ (Note 10) Full -0.5 - 0.5 A 25 - 24 33 ns Full - - 35 ns ON Resistance, RON V+ = 1.8V, ICOM = 10.0mA, VAx or VBx= 1.0V, (See Figure 5) RON Matching Between Channels, RON) V+ = 1.8V, ICOM = 10.0mA, VAx or VBx = 1.0V, (See Figure 5) RON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 10.0mA, VAx or VBx = 0V, 0.9V, 1.6V, (See Figure 5) DIGITAL INPUT CHARACTERISTICS DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) Break-Before-Make Time, tBBM V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 10) 25 - 9 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0(See Figure 2) 25 - -46 - pC FN6096 Rev 1.00 October 12, 2004 Page 4 of 11 ISL43L840 Test Circuits and Waveforms V+ LOGIC INPUT tr < 5ns tf < 5ns 50% V+ C C 0V tTRANS V+ VOUT VA0, VB0 A0,B0 90% VOUT COMA COMB A1-A3 B1-B3 ADD1-0 GND SWITCH OUTPUT LOGIC INPUT 10% 0V CL 35pF RL 50 0V tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L  ON  FIGURE 1A. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1B. ADDRESS tTRANS TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ V+ LOGIC INPUT ON VOUT RG OFF OFF 0V C COMA Ax, Bx 0 COMB ADDX SWITCH OUTPUT VOUT VG VOUT GND CL 1nF LOGIC INPUT Q = VOUT x CL Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ C tr < 5ns tf < 5ns V+ LOGIC INPUT A0-A3 B0-B3 V+ 0V C COMA COMB ADD1-0 90% SWITCH OUTPUT VOUT VOUT RL 50 CL 35pF LOGIC INPUT GND 0V tBBM Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME FN6096 Rev 1.00 October 12, 2004 Page 5 of 11 ISL43L840 Test Circuits and Waveforms (Continued) V+ V+ C C RON = V1/100mA SIGNAL GENERATOR NO or NC NO or NC VNX 100mA 0V or V+ ANALYZER COM 0V or V+ V1 ADDX ADDX COM GND GND RL FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ SIGNAL GENERATOR C V+ NOA or NCA 0V or V+ C 50 COMA NO or NC ADDX 0V or V+ ADDX IMPEDANCE ANALYZER NOB or NCB ANALYZER FIGURE 5. RON TEST CIRCUIT COMB N.C. GND COM GND RL FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT Detailed Description The ISL43L840 analog switches offer precise switching capability from a single 1.6V to 3.6V supply with low onresistance (0.5) and high speed operation (tRANS = 19ns). The device is especially well-suited to portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.2W), and low leakage currents (60nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these FN6096 Rev 1.00 October 12, 2004 conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is Page 6 of 11 ISL43L840 reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1k OPTIONAL PROTECTION DIODE V+ ADDX VNOx VCOM GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION High-Frequency Performance In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 15). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed-through, while Crosstalk indicates the amount of feed-through from one switch to another. Figure 16 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Power-Supply Considerations Leakage Considerations The ISL43L840 construction is typical of most CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L840 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Logic-Level Thresholds The device is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (see Figure 13). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. FN6096 Rev 1.00 October 12, 2004 Page 7 of 11 ISL43L840 Typical Performance Curves TA = 25°C, Unless Otherwise Specified 0.75 0.65 ICOM = 100mA V+ = 1.65V 0.7 V+ = 3V ICOM = 100mA 0.6 0.65 0.55 V+ = 1.8V 85°C RON () RON () 0.6 0.55 25°C 0.45 V+ = 2.7V 0.5 0.5 V+ = 3V 0.45 0.4 -40°C V+ = 3.6V 0.4 0 1 2 3 4 0.35 0 0.5 1 FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 0.75 2 2.5 3 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE 100 V+ = 1.8V ICOM = 100mA 0.7 0.65 50 85°C 0.6 V+ = 1.8V 0.55 Q (pC) RON () 1.5 VCOM (V) VCOM (V) 25°C 0 V+ = 3V 0.5 -50 0.45 -40°C 0.4 0 0.5 1 VCOM (V) 1.5 2 -100 FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 0.5 1 1.5 VCOM (V) 2 2.5 3 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 1.6 60 1.4 50 1.2 VINH tRANS (ns) VINH AND VINL (V) 0 1 VINL 0.8 40 30 85°C 20 0.6 10 1 1.5 2 2.5 3 3.5 4 4.5 V+ (V) FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FN6096 Rev 1.00 October 12, 2004 25°C -40°C 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5 FIGURE 14. ADDRESS TRANS TIME vs SUPPLY VOLTAGE Page 8 of 11 ISL43L840 0 V+ = 3V GAIN 0 PHASE 20 40 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 0.1 1 100 10 100 FREQUENCY (MHz) FIGURE 15. FREQUENCY RESPONSE CROSSTALK (dB) -10 -10 20 -20 30 -30 40 -40 50 -50 60 ISOLATION -60 70 -70 80 -80 OFF ISOLATION (dB) 0 10 V+ = 3V PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 90 CROSSTALK -90 -100 1k 100 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 16. CROSSTALK AND OFF ISOLATION Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Submicron CMOS © Copyright Intersil Americas LLC 2004. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6096 Rev 1.00 October 12, 2004 Page 9 of 11 ISL43L840 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 B M 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 L A D -C- e  A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 0.002 0.006 D 0.193 0.201 4.90 5.10 3 E1 0.169 0.177 4.30 4.50 4 e A2 MILLIMETERS 0.026 BSC E 0.246 L 0.020 N  0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 0.70 6 16 8o 0o - 6.50 7 8o Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) FN6096 Rev 1.00 October 12, 2004 Page 10 of 11 ISL43L840 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C A D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E 9 TOP VIEW A2 A A3 SIDE VIEW 4X P 9 - 0.05 - A2 - - 1.00 9 A3 0.20 REF 0.18 - D1 2.75 BSC 9 1.35 1.65 7, 8, 10 - 2.75 BSC 1.35 1.50 9 1.65 7, 8, 10 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 16 2 Nd 4 3 - 0.60 NX k  - - 12 4 3 9 9 Rev. 1 6/04 NOTES: 1 (DATUM A) 2 3 6 INDEX AREA NX L N e 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. (Ne-1)Xe REF. E2 E2/2 2. N is the number of terminals. 7 3. Nd and Ne refer to the number of terminals on each D and E. 8 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 9 CORNER OPTION 4X (Nd-1)Xe REF. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. BOTTOM VIEW A1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b 5 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. SECTION "C-C" C L 9. Features and dimensions A2, A3, D1, E1, P &  are present when Anvil singulation method is used and not present for saw singulation. C L L e FN6096 Rev 1.00 October 12, 2004 1.50 3.00 BSC - 10 5, 8 3.00 BSC P D2 2 N FOR ODD TERMINAL/SIDE 0.30 D Ne 7 L1 0.23 9 8 4X P C C 1.00 - 0.10 M C A B D2 (DATUM B) A1 5 NX b 8 0.90 - e 0.08 C SEATING PLANE 0.80 E1 / / 0.10 C C NOTES A E2 0 4X B MAX A1 E 0.15 C B 0.15 C A NOMINAL D2 2X 2X MIN b E/2 E1 SYMBOL L1 10 L 10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension. e TERMINAL TIP FOR EVEN TERMINAL/SIDE Page 11 of 11