DATASHEET
ISL5120, ISL5121, ISL5122, ISL5123
Low Voltage, Single Supply, Dual SPST, SPDT Analog Switches
The Intersil ISL5120, ISL5121, ISL5122, ISL5123 devices are
precision, bidirectional, dual analog switches designed to
operate from a single +2.7V to +12V supply. Targeted
applications include battery powered equipment that benefit
from the devices’ low power consumption (5µW), low leakage
currents (100pA max), and fast switching speeds (tON = 28ns,
tOFF = 20ns). Cell phones, for example, often face ASIC
functionality limitations. The number of analog input or GPIO
pins may be limited and digital geometries are not well suited to
analog switch performance. This family of parts may be used to
“mux-in” additional functionality while reducing ASIC design
risk. Some of the smallest packages are available, alleviating
board space limitations and making Intersil’s newest line of
low-voltage switches an ideal solution.
The ISL5120, ISL5121, ISL5122 are dual
single-pole/single-throw (SPST) devices. The ISL5120 has two
normally open (NO) switches; the ISL5121 has two normally
closed (NC) switches; the ISL5122 has one NO and one NC
switch and can be used as an SPDT. The ISL5123 is a
committed SPDT, which is perfect for use in 2-to-1 multiplexer
applications.
TABLE 1. FEATURES AT A GLANCE
ISL5121
ISL5122
ISL5123
Number of
Switches
2
2
2
1
SW 1/SW 2
NO/NO
NC/NC
NO/NC
SPDT
3.3V RON
32Ω
32Ω
32Ω
32Ω
40ns /20ns
40ns
/20ns
40ns
/20ns
40ns /20ns
19Ω
19Ω
19Ω
19Ω
5V RON
5V tON/tOFF
28ns/2y0ns 28ns/20ns 28ns/20ns 28ns/20ns
12V RON
11Ω
12V tON/tOFF
25ns/17ns
Packages
8 Ld SOIC,
8 Ld SOT-23
11Ω
11Ω
11Ω
25ns/17ns 25ns/17ns 25ns/17ns
8 Ld SOIC,
8 Ld SOT-23
8 Ld SOIC,
6 Ld SOT-23
Related Literature
• TB363, “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
FN6022 Rev 8.00
August 12, 2015
Features
• Improved (lower rON, faster switching), pin compatible
replacements for ISL84541, ISL84542, ISL84543,
ISL84544
• Fully specified at 3.3V, 5V, and 12V supplies
• ON resistance (rON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Ω
• rON matching between channels . . . . . . . . . . . . . . . . . . . . . . . ≤1Ω
• Low charge injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
• Single supply operation . . . . . . . . . . . . . . . . . . . . . . +2.7V to +12V
• Low power consumption (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical, Note 7)
JA (°C/W)
6 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
215
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . 150°C
Moisture Sensitivity (see Technical Brief TB363)
All Other Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
8 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . . -65°C to 150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range
ISL512xCx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ISL512xIx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
7. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 8), unless
otherwise specified.Boldface limits apply across the operating temperature range, -40°C to +85°C (ISL512xIx) or
0°C to +70°C. (ISL512xCx)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Full
0
-
V+
V
25
-
19
30
Ω
Full
-
23
40
Ω
25
-
0.8
2
Ω
Full
-
1
4
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-resistance, rON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,
(See Figure 5)
rON Matching Between Channels,
rON
V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3.5V
rON Flatness, rFLAT(ON)
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V
Full
-
7
8
Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,
(Note 10)
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.1
-
0.1
nA
Full
-5
-
5
nA
25
-0.2
-
0.2
nA
Full
-10
-
10
nA
25
-
28
75
ns
Full
-
40
150
ns
25
-
20
50
ns
Full
-
30
100
ns
COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V,
(Note 10)
COM ON Leakage Current, ICOM(ON)
V = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or
Floating, (Note 10)
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
VNO or VNC = 3V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V,
(See Figure 1)
VNO or VNC = 3V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V,
(See Figure 1)
Break-before-make Time Delay
(ISL5122, ISL5123), tD
RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V,
(See Figure 3)
Full
3
10
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
3
5
pC
Off Isolation
RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 4)
25
-
76
-
dB
FN6022 Rev 8.00
August 12, 2015
Page 4 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 8), unless
otherwise specified.Boldface limits apply across the operating temperature range, -40°C to +85°C (ISL512xIx) or
0°C to +70°C. (ISL512xCx) (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Crosstalk (Channel-to-channel)
RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 6)
25
-
-105
-
dB
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
60
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
8
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7),
ISL5120/1/2
25
-
21
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7),
ISL5123
25
-
28
-
pF
Full
2.7
12
V
Full
-1
0.0001
1
µA
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, VIN = 0V or V+, all channels on or off
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 5.5V, VIN = 0V or V+
Electrical Specifications - 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 8),
unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C (ISL512xIx) or
0°C to +70°C. (ISL512xCx)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Full
0
-
V+
V
25
-
32
50
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-resistance, rON
V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
rON Matching Between Channels,
rON
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V
rON Flatness, rFLAT(ON)
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 1.5V
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, (Note 10)
COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, (Note 10)
COM ON Leakage Current, ICOM(ON)
V = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or
floating, (Note 10)
Full
-
40
60
Ω
25
-
0.8
2
Ω
Full
-
1
4
Ω
25
-
6
8
Ω
Full
-
7
12
Ω
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.2
-
0.2
nA
Full
-10
-
10
nA
25
-
40
120
ns
Full
-
60
200
ns
25
-
20
50
ns
Full
-
30
120
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
FN6022 Rev 8.00
August 12, 2015
VNO or VNC = 1.5V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V
VNO or VNC = 1.5V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V
Page 5 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Electrical Specifications - 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 8),
unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C (ISL512xIx) or
0°C to +70°C. (ISL512xCx) (Continued) (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Break-before-make Time Delay
(ISL5122, ISL5123), tD
RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V,
VIN = 0 to 3V
Full
3
20
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω
25
-
1
5
pC
Off Isolation
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
76
-
dB
25
-
-105
-
dB
Crosstalk (Channel-to-channel)
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
56
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V
25
-
8
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, ISL5120/1/2
25
-
21
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, ISL5123
25
-
28
-
pF
V+ = 3.6V, VIN = 0V or V+, all channels on or off
Full
-1
-
1
µA
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
Electrical Specifications - 12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 8),
unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C (ISL512xIx) or
0°C to +70°C. (ISL512xCx).
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Full
0
-
V+
V
25
-
11
20
Ω
Full
-
15
25
Ω
25
-
0.8
2
Ω
Full
-
1
4
Ω
25
-
1
4
Ω
Full
-
-
6
Ω
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.2
-
0.2
nA
Full
-10
-
10
nA
25
-
25
35
ns
Full
-
35
55
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-resistance, rON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 10V
rON Matching Between Channels,
rON
V+ = 12V, ICOM = 1.0mA, VNO or VNC = 10V
rON Flatness, rFLAT(ON)
V+ = 12V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V,
(Note 10)
COM OFF Leakage Current, ICOM(OFF) V+ = 13V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V,
(Note 10)
COM ON Leakage Current, ICOM(ON)
V = 13V, VCOM = 1V, 12V, or VNO or VNC = 1V, 12V, or
floating, (Note 10)
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
FN6022 Rev 8.00
August 12, 2015
VNO or VNC = 10V, RL =1kΩ, CL = 35pF, VIN = 0 to 4V
Page 6 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Electrical Specifications - 12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 8),
unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C (ISL512xIx) or
0°C to +70°C. (ISL512xCx). (Continued)
PARAMETER
TEST CONDITIONS
Turn-OFF Time, tOFF
VNO or VNC = 10V, RL =1kΩ, CL = 35pF, VIN = 0 to 4V
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
25
-
17
30
ns
Full
-
26
50
ns
Break-before-make Time Delay
(ISL5122, ISL5123), tD
RL = 300Ω, CL = 35pF, VNO or VNC = 10V,
VIN = 0 to 4V
Full
0
2
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω
25
-
5
15
pC
Off Isolation
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
76
-
dB
25
-
-105
-
dB
Crosstalk (Channel-to-channel)
ns
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
25
-
63
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V
25
-
8
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, ISL5120/1/2
25
-
21
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, ISL5123
25
-
28
-
pF
V+ = 13V, VIN = 0V or V+, all channels on or off
Full
-1
-
1
µA
Full
-
-
0.8
V
Full
2.9
-
-
V
Full
4
3
-
V
Full
-1
-
1
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
ISL5120CX only
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 13V, VIN = 0V or V+
NOTES:
8. VIN = input voltage to perform proper function.
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
10. Leakage parameter is 100% tested at high temp, and established by correlation at +25°C.
Test Circuits and Waveforms
3V OR 4V
LOGIC
INPUT
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
NO or NC
COM
IN
VOUT
90%
SWITCH
OUTPUT
V+
tr < 20ns
tf < 20ns
90%
0V
LOGIC
INPUT
RL
1k?
GND
CL
35pF
tON
Logic input waveform is inverted for switches that have the opposite logic
sense.
Repeat test for all switches. CL includes fixture and stray capacitance.
V OUT = V
FIGURE 1A. MEASUREMENT POINTS
RL
--------------------------(NO or NC) R + r
L
ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FN6022 Rev 8.00
August 12, 2015
Page 7 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Test Circuits and Waveforms (Continued)
V+
SWITCH
OUTPUT
VOUT
RG
VOUT
V+
LOGIC
INPUT
ON
ON
OFF
C
VG
VOUT
COM
NO or NC
GND
IN
CL
0V
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
3V OR 4V
LOGIC
INPUT
0V
C
VOUT1
NO1
VNX
COM1
VOUT2 RL1
300?
NC2
SWITCH
OUTPUT
VOUT1
COM2
90%
IN1
0V
RL2
300?
IN2
SWITCH
OUTPUT
VOUT2
90%
0V
LOGIC
INPUT
CL1
35pF
CL2
35pF
GND
tD
tD
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS (ISL5122 ONLY)
FIGURE 3B. TEST CIRCUIT (ISL5122 ONLY)
V+
3V OR 4V
LOGIC
INPUT
0V
C
NO
VNX
RL
300?
IN
SWITCH
OUTPUT
VOUT
90%
0V
VOUT
COM
NC
CL
35pF
GND
LOGIC
INPUT
tD
CL includes fixture and stray capacitance.
FIGURE 3C. MEASUREMENT POINTS (ISL5123 ONLY)
FIGURE 3D. TEST CIRCUIT (ISL5123 ONLY)
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6022 Rev 8.00
August 12, 2015
Page 8 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V1/1mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
INX
0V or VINH
1mA
0.8V or VINH
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO1 or NC1
COM1
50?
NO or NC
IN1
COM2
ANALYZER
RL
INX
IN2 0V or VINH
0V or 2.4V
NO2 or NC2
GND
NC
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL5120, ISL5121, ISL5122, ISL5123 bidirectional, dual
analog switches offer precise switching capability from a
single 2.7V to 12V supply with low ON-resistance (19Ω) and
high speed operation (tON = 28ns, tOFF = 20ns). The devices
are especially well suited to portable battery powered
equipment thanks to the low operating supply voltage (2.7V),
low power consumption (5µW), low leakage currents (100pA
max) and the tiny SOT-23 packaging. High frequency
applications also benefit from the wide bandwidth and the very
high off isolation and crosstalk rejection.
Supply Sequencing and Overvoltage
Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
FN6022 Rev 8.00
August 12, 2015
0V or VINH
IMPEDANCE
ANALYZER
COM
GND
FIGURE 7. CAPACITANCE TEST CIRCUIT
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and GND (see
Figure 8 on page 10). To prevent forward biasing these diodes,
V+ must be applied before any input signals, and input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ resistor in
series with the input (see Figure 8). The resistor limits the input
current below the threshold that produces permanent
damage, and the submicroamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
Page 9 of 16
ISL5120, ISL5121, ISL5122, ISL5123
limit the analog signal from 1V below V+ to 1V above GND. The
low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
High Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
300MHz (see Figure 16 on page 12). Figure 16 also illustrates
that the frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 17 on page 12 details the high Off Isolation and
Crosstalk rejection provided by this family. At 10MHz, Off
Isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation and Crosstalk
rejection due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
FIGURE 8. OVERVOLTAGE PROTECTION
Power Supply Considerations
The ISL512x construction is typical of most CMOS analog
switches, except that they have only two supply pins: V+ and
GND. V+ and GND drive the internal CMOS switches and set
their analog voltage limits. Unlike switches with a 13V
maximum supply voltage, the ISL512x 15V maximum supply
voltage provides plenty of room for the 10% tolerance of 12V
supplies, as well as room for overshoot and noise spikes.
The minimum recommended supply voltage is 2.7V. It is
important to note that the input signal range, switching times
and ON-resistance degrade at lower supply voltages. Refer to
the electrical specification tables starting on page 4 and
Typical Performance curves starting on page 11 for details.
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these diodes
conducts if any analog signal exceeds V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced, they
are reverse biased differently. Each is biased by either V+ or
GND and the analog signal. This means their leakages will vary
as the signal varies. The difference in the two diode leakages
to the V+ and GND pins constitutes the analog-signal-path
leakage current. All analog leakage current flows between
each pin and one of the supply terminals, not to the other
switch terminal. This is why both sides of a given switch can
show leakage currents of the same or opposite polarity. There
is no connection between the analog signal paths and V+ or
GND.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched V+
and GND signals to drive the analog switch gate terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
Logic-level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a
supply range of 3V to 11V (see Figure 15). At 12V the VIH level
is about 2.5V. This is still below the TTL guaranteed high output
minimum level of 2.8V, but the noise margin is reduced. For
best results with a 12V supply, use a logic family the provides a
VOH greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
FN6022 Rev 8.00
August 12, 2015
Page 10 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Typical Performance Curves
TA = +25°C, unless otherwise specified.
45
40
V+ = 3.3V
40
35
35
30
30
rON (Ω)
rON (Ω)
20
+25°C
-40°C
15
30
25
V+ = 5V
20
+85°C
+25°C
-40°C
15
10
20
-40°C
10
+25°C
20
25
15
+85°C
25
+85°C
+85°C
15
5
3
4
5
6
7
8
V+ (V)
9
10
11
12
10
13
5
-40°C
6
VCOM (V)
8
10
12
V+ = 3.3V
60
+25°C
50
+85°C
0.1
0
0.25
0.2
0.15
40
-40°C
30
V+ = 5V
+25°C
0.1
Q (pC)
rON (Ω)
4
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
0.2
+85°C
20
-40°C
-40°C
V+ = 12V
+85°C
+25°C
-40°C
0
4
2
V+ = 12V
V+ = 3.3V
0
+25°C
0.1
0.05
V+ = 5V
10
+85°C
0.05
0
0.15
0
2
0
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE
0.5
0.4
0.3
V+ = 12V
+25°C
6
8
VCOM (V)
10
-10
-20
0
4
2
6
VCOM (V)
12
8
10
12
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 11. rON MATCH vs SWITCH VOLTAGE
100
35
90
80
30
+85°C
tOFF (ns)
tON (ns)
70
60
+85°C
25
50
-40°C
-40°C
40
20
-40°C
+25°C
30
20
+25°C
2
3
4
5
6
7
V+ (V)
8
9
10
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE
FN6022 Rev 8.00
August 12, 2015
11
12
15
2
3
4
5
6
7
V+ (V)
8
9
10
11
FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
Page 11 of 16
12
ISL5120, ISL5121, ISL5122, ISL5123
Typical Performance Curves
NORMALIZED GAIN (dB)
TA = +25°C, unless otherwise specified. (Continued)
3.0
2.5
-40°C
2.0
+85°C
GAIN
-3
-6
0
PHASE
20
+25°C
1.5
+85°C
40
-40°C
60
+25°C
1.0
RL = 50Ω
VIN = 0.2VP-P to 2.5VP-P (V+ = 3.3V)
VIN = 0.2VP-P to 4VP-P (V+ = 5V)
VIN = 0.2VP-P to 5VP-P (V+ = 12V)
VINL
+85°C
0.5
2
3
4
5
6
7
8
V+ (V)
9
10
11
12
13
1
10
-10
10
0
-30
30
10
-40
40
20
-50
50
-70
70
-80
80
CROSSTALK
-100
1M
10M
PSRR (dB)
60
ISOLATION
100k
600
V+ = 3.3V, SWITCH OFF
OFF ISOLATION (dB)
CROSSTALK (dB)
20
10k
100
RL = 50?
-20
-110
1k
100
FIGURE 16. FREQUENCY RESPONSE
V+ = 3V to 13V
-90
80
FREQUENCY (MHz)
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
-60
40
V+ = 12V, SWITCH ON
50
60
90
70
100
80
110
100M 500M
V+ = 12V, SWITCH OFF
30
0.3
V+ = 3.3V, SWITCH ON
1
10
100
FREQUENCY (Hz)
FREQUENCY (MHz)
FIGURE 17. CROSSTALK AND OFF ISOLATION
FIGURE 18. ±PSRR vs FREQUENCY
1000
Die Characteristics
Substrate Potential (Powered Up):
GND
Transistor Count:
ISL5120: 66
ISL5121: 66
ISL5122: 66
ISL5123: 58
Process:
Si Gate CMOS
FN6022 Rev 8.00
August 12, 2015
PHASE (°)
VINH AND VINL (V)
VINH
V+ = 3.3V to 12V
0
Page 12 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
August 12, 2015
FN6022.8
Updated Ordering Information on page 3
May 6, 2015
FN6022.7
Added Revision History
Updated datasheet to Intersil new standards
Updated ordering information table by removing obsolete parts and adding Notes 2, 4 and 5.
Replaced M8.15 POD with the latest revision (Rev 4.)
Changes from Rev 0 to Rev 1: Remove “u” symbol from drawing (overlaps the “a” on Side View).
Changes from Rev 1 to Rev 2: Updated to new POD format by removing table and moving dimensions onto
drawing and adding land pattern
Changes from Rev2 to Rev 3: Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changes from Rev 3 to Rev 4: Changed “1982” to “1994” in Note 1.
Replaced P6.064 with the latest revision (Rev 4).
Changes from Rev 3 to Rev 4: Update to new format (same dimensions, added land pattern and moved
dimensions from table onto drawing)
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2005-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6022 Rev 8.00
August 12, 2015
Page 13 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6022 Rev 8.00
August 12, 2015
Page 14 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Package Outline Drawing
P6.064
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 4, 2/10
0-8°
1.90
0.95
0.08-0.22
D
A
6
5
4
2.80
PIN 1
INDEX AREA
1.60 +0.15/-0.10
3
3
(0.60)
1
2
3
0.20 C
2x
0.40 ±0.10
B
SEE DETAIL X
3
0.20 M C A-B D
END VIEW
TOP VIEW
10° TYP
(2 PLCS)
2.90 ±0.10
3
1.15 +0.15/-0.25
C
0.10 C
SEATING PLANE
0.00-0.15
SIDE VIEW
(0.25)
GAUGE
PLANE
1.45 MAX
DETAIL "X"
0.45±0.1
4
(0.95)
(0.60)
(1.20)
(2.40)
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
Package conforms to JEDEC MO-178AB.
TYPICAL RECOMMENDED LAND PATTERN
FN6022 Rev 8.00
August 12, 2015
Page 15 of 16
ISL5120, ISL5121, ISL5122, ISL5123
Small Outline Transistor Plastic Packages (SOT23-8)
0.20 (0.008) M
CL
C
P8.064
VIEW C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e
b
INCHES
SYMBOL
8
7
6
5
CL
CL
E
1
2
3
E1
4
e1
C
D
CL
A
A2
A1
SEATING
PLANE
-C-
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.009
0.015
0.22
0.38
-
b1
0.009
0.013
0.22
0.33
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0768 Ref
1.95 Ref
-
L
0.10 (0.004) C
MIN
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
8
8
5
WITH
b
R
0.004
-
0.10
-
PLATING
b1
R1
0.004
0.010
0.10
0.25
0o
8o
0o
8o
c
c1
4
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
4X 1
VIEW C
FN6022 Rev 8.00
August 12, 2015
Page 16 of 16
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