ISL54502IRUZ-T

DESIGNS FOR NEW D E D N E M M NT PART NOT RECO PLACEME E R D E D N RECOMME UZ-T ISL54050IR ISL54501, ISL54502 DATASHEET FN6550 Rev 3.00 May 6, 2013 +1.62V to +5.5V, 5Ω, Single SPST Analog Switches The Intersil ISL54501 and ISL54502 devices are low ON-resistance, low voltage, bi-directional, single pole/single throw (SPST) analog switches designed to operate from a single +1.62V to +5.5V supply. Targeted applications include battery powered equipment that benefit from low rON resistance (5), excellent rON flatness, and fast switching speeds (tON = 22ns, tOFF = 15ns). The digital logic input is 1.8V CMOS compatible when using a single +3V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to switch in additional functionality while reducing ASIC design risk. The ISL54501, ISL54502 are offered in a 6 Ld 1.2mmx1.0mmx0.4mm pitch µTDFN package, alleviating board space limitations. The ISL54501 has one normally open (NO) switch and ISL54502 has one normally closed (NC) switch. ISL54501 ISL54502 NUMBER OF SWITCHES 1 1 SW NO NC 1.8V rON 12 12 1.8V tON/tOFF 70ns/52ns 70ns/52ns 3V rON 6.0 6.0 3V tON/tOFF 30ns/20ns 30ns/20ns 5V rON 5.0 5.0 5V tON/tOFF 22ns/15ns 22ns/15ns FN6550 Rev 3.00 May 6, 2013 • ON-resistance (rON) - VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 - VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 - VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 • rON Flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 • Single Supply Operation. . . . . . . . . . . . . . . . . . . . +1.62V to +5.5V • Fast Switching Action (+4.5V Supply) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns • ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV • 1.8V CMOS Logic Compatible (+3V supply) • Available in 6 Ld µTDFN and 6 Ld SOT-23 Packages • Pb-free Available (RoHS compliant) Applications TABLE 1. FEATURES AT A GLANCE Packages Features 6 Ld µTDFN, 6 Ld SOT-23 • Battery powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops • Portable Test and Measurement • Medical Equipment • Audio and video switching Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Page 1 of 13 ISL54501, ISL54502 Ordering Information PART NUMBER (Notes 1, 4) PART MARKING PACKAGE (Tape and Reel) (Pb-Free) TEMP. RANGE (°C) PKG. DWG. # ISL54501IRUZ-T (Note 2) 1 -40 to +85 6 Ld µTDFN L6.1.2x1.0A ISL54501IHZ-T (Note 3) 4501 -40 to +85 6 Ld SOT-23 P6.064A ISL54502IRUZ-T (Note 2) 2 -40 to +85 6 Ld µTDFN L6.1.2x1.0A ISL54502IHZ-T (Note 3) 4502 -40 to +85 6 Ld SOT-23 P6.064A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54501, ISL54502. For more information on MSL please see techbrief TB363. FN6550 Rev 3.00 May 6, 2013 Page 2 of 13 ISL54501, ISL54502 Pin Configurations (Note 5) ISL54502 (6 LD UTDFN) TOP VIEW ISL54501 (6 LD UTDFN) TOP VIEW NO 1 6 IN N.C. 1 6 IN GND 2 5 V+ GND 2 5 V+ N.C. 3 4 COM NC 3 4 COM ISL54502 (6 LD SOT-23) TOP VIEW ISL54501 (6 LD SOT-23) TOP VIEW 6 GND N.C. 1 IN 5 COM 2 4 V+ NO 3 NC 1 6 GND IN 2 5 COM N.C. 3 4 V+ NOTE: 5. Switches Shown for Logic “0” Input. Pin Descriptions PIN LOGIC ISL54501 ISL54502 System Power Supply Input (+1.62V to +5.5V) 0 Off On GND Ground Connection 1 On Off IN Digital Control Input V+ COM FUNCTION Truth Table NOTE: Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply. Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Connect FN6550 Rev 3.00 May 6, 2013 Page 3 of 13 ISL54501, ISL54502 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5V Input Voltages NO, NC, IN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V) Output Voltages COM (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . . . . . . . . ±300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max)  600mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2.2kV Thermal Resistance (Typical) JA (°C/W) JC(°C/W) 6 Ld µTDFN Pkg. (Notes 7, 9) . . . . . . . . . . . 239.2 111.6 6 Ld SOT-23 Pkg. (Note 8, 9). . . . . . . . . . . . 260 120 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions V+ (Positive DC Supply Voltage) . . . . . . . . . . . . 1.8V ± 10% to 5.0V ± 10% Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+ VIN (Digital Logic Input Voltage (IN) . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+ Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 8. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 9. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS Full 0 - V+ V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 14, see Figure 4) 25 - 4.2 5  Full - - 6  25 - 1.1 1.3  rON Flatness, rFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 13, 14) Full - - 1.5  NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V 25 -25 1.2 25 nA Full -150 - 150 nA COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V, or Floating 25 -30 1.7 30 nA Full -300 - 300 nA V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 1, Note 14) 25 - 22 - ns Full - 23 - ns V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 1, Note 14) 25 - 15 - ns Full - 15 - ns V+ = 5.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 3, Note 14) Full - 18 - ns Charge Injection, Q VG = 0V, RG = 0, CL = 1.0nF (see Figure 2) 25 - 16 - pC OFF-Isolation L = 50, CL = 5pF, f = 1MHz, VCOM = 1VP-P 25 - 75 - dB DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD (see Figure 3) Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 25 - 0.12 - % Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 25 - 0.01 - % -3dB Bandwidth Signal = 0dBm, RL = 50 25 - 350 - MHz NO or NC OFF Capacitance, COFF V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 5) 25 - 6 - pF COM ON Capacitance, CCOM(ON) V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 5) 25 - 12 - pF FN6550 Rev 3.00 May 6, 2013 Page 4 of 13 ISL54501, ISL54502 Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 11, 12) Full 1.62 - 5.5 V 25 - 0.02 0.1 µA Full - 0.5 2.5 µA V TYP MAX (Notes 11, 12) UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.8 Input Voltage High, VINH Full 2.4 - - V Full -0.1 0.044 0.1 µA Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS Full 0 - V+ V 25 - 6.3 7  Full - - 8  25 - 1.8 2.3  Full - - 2.5  25 - 28 - ns Full - 30 - ns 25 - 20 - ns Full - 30 - ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON rON Flatness, rFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 14, see Figure 4) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 13, 14) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 1, Note 8) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 1, Note 14) Charge Injection, Q VG = 0V, RG = 0,CL = 1.0nF (see Figure 2) 25 - 12 - pC OFF-Isolation RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VP-P (see Figure 3) 25 - 75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 25 - 0.4 - % Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 25 - 0.053 - % -3dB Bandwidth Signal = 0dBm, RL = 50 25 - 350 - MHz NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 5) 25 - 6 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 5) 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 5) 25 - 12 - pF 25 - 0.02 - µA Full - 0.11 - µA Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.4 - - V Full -0.1 0.049 0.1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL FN6550 Rev 3.00 May 6, 2013 V+ = 3.6V, VIN = 0V or V+ Page 5 of 13 ISL54501, ISL54502 Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS Full 0 - V+ V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+ (Note 14, see Figure 4) 25 - 11.9 12.8  Full - - 13.8  25 - 70 - ns Full DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 1, Note 14) - 130 - ns Turn-OFF Time, tOFF V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 1, Note 14) 25 - 52 - ns Full - 100 - ns VG = V+/2, RG = 0, CL = 1.0nF (see Figure 2) 25 - 5.8 - pC Charge Injection, Q DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.4 V Input Voltage High, VINH Full 1 - - V NOTES: 10. VIN = input voltage to perform proper function. 11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 14. Limits established by characterization and are not production tested. Test Circuits and Waveforms V+ LOGIC INPUT 50% C 0V tOFF SWITCH INPUT VNO SWITCH INPUT VOUT 90% SWITCH OUTPUT V+ tr < 20ns tf < 20ns VOUT NO or NC COM IN 90% 0V LOGIC INPUT GND RL 50 CL 35pF tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL --------------------------V OUT = V (NO or NC) R + r L  ON  FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES FN6550 Rev 3.00 May 6, 2013 Page 6 of 13 ISL54501, ISL54502 Test Circuits and Waveforms (Continued) V+ SWITCH OUTPUT VOUT RG VOUT VINH ON ON LOGIC INPUT OFF C VG GND VOUT COM NO OR NC IN CL VINL LOGIC INPUT Q = VOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ V+ C C SIGNAL GENERATOR rON = V1/I1 * NO OR NC NO OR NC VNX IN 0V OR V+ IN V1 I1 VINL OR VINH 100mA COM COM ANALYZER GND GND RL * I = 10mA AT V+ = 1.8V 1 FIGURE 3. OFF ISOLATION TEST CIRCUIT FIGURE 4. rON TEST CIRCUIT V+ C NO OR NC IN VINL OR VINH IMPEDANCE ANALYZER COM GND FIGURE 5. CAPACITANCE TEST CIRCUIT FN6550 Rev 3.00 May 6, 2013 Page 7 of 13 ISL54501, ISL54502 Detailed Description The ISL54501 and ISL54502 are bi-directional, single pole/single throw (SPST) analog switches. They offer precise switching capability from a single 1.62V to 5.5V supply with low ON-resistance and high speed operation. With a single supply of 5V the typical ON-resistance is only 5, with a typical turn-on and turn-off time of: tON = 22ns, tOFF = 15ns. The devices are especially well suited for portable battery powered equipment due to their low operating supply voltage (1.62V), low power consumption (0.11µW), low leakage currents (300nA max), and tiny µTDFN package. The ISL54501 is a single normally open (NO) SPST analog switch. The ISL54502 is a single normally closed (NC) SPST analog switch. External V+ Series Resistor For improved ESD and latch-up immunity, Intersil recommends adding a 100 resistor in series with the V+ power supply pin of the ISL54501, ISL54502 IC (see Figure 6). During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many over voltage transient events. Under normal operation the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance. V+ OPTIONAL PROTECTION RESISTOR If these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting Schottky diodes to the signal pins (as shown in Figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current. OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNX OPTIONAL SCHOTTKY DIODE VCOM GND C FIGURE 7. OVERVOLTAGE PROTECTION 100 NO COM NC IN GND FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see FN6550 Rev 3.00 May 6, 2013 Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. Power-Supply Considerations The ISL54501, ISL54502 construction is typical of most single supply CMOS analog switches in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54501, ISL54502 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V ± 10% but the part will operate with a supply below 1.62V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the “Electrical Specifications” tables starting on page 4 the and “Typical Performance Curves” starting on page 9 for details. Page 8 of 13 ISL54501, ISL54502 V+ and GND also power the internal logic and level shiftier. The level shiftier converts the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (see Figure 14). At 3.6V the VIH level is about 0.98V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50 systems, the ISL54501, ISL54502 has a -3dB bandwidth of 350MHz (see Figure 15). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch behaves like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to output. Off isolation is the resistance of this signal feedthrough. Figure 16 details the high off isolation provided by the ISL54501, ISL54502. At 1MHz, off isolation is about 75dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Typical Performance Curves TA = +25°C, Unless Otherwise Specified 6 8 ICOM = 100mA V+ = 4.5V ICOM = 100mA 7 5 V+ = 2.7V 6 4 V+ = 3V 4 rON () rON () 5 V+ = 4.5V 3 +85°C +25°C 3 -40°C V+ = 5V 2 2 1 0 0 1 2 3 4 VCOM (V) FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE FN6550 Rev 3.00 May 6, 2013 5 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCOM (V) FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE Page 9 of 13 ISL54501, ISL54502 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 14 8 13 7 +85°C 12 +25°C 10 rON () 5 rON () 11 6 -40°C 4 +85°C 9 8 +25°C 7 -40°C 6 5 3 3 2 0 0.5 1.0 1.5 2.0 V+ = 1.8V ICOM = 10mA 4 V+ = 2.7V ICOM = 100mA 2 2.5 0 0.2 0.4 0.6 0.8 VCOM (V) 1.0 1.2 1.4 1.6 1.8 2.0 VCOM (V) FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE 130 100 120 -40°C 90 -40°C 110 80 100 70 80 tOFF (ns) tON (ns) 90 +25°C 70 60 50 40 +25°C 50 40 30 +85°C 20 30 +85°C 10 20 10 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 1.5 2.0 2.5 3.0 V+ (V) 4.0 4.5 5.0 5.5 6.0 V+ (V) FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE 1.4 0 -1 1.2 -2 V+ = 1.8V TO 5.5V VCOM = 1VP-P -3 NORMALIZED GAIN (dB) 1.0 VINH AND VINL (V) 3.5 VINH 0.8 VINL 0.6 0.4 -4 -5 -6 -7 -8 -9 -10 -11 0.2 -12 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V+ (V) FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FN6550 Rev 3.00 May 6, 2013 5.5 -13 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 15. FREQUENCY RESPONSE Page 10 of 13 ISL54501, ISL54502 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 19 -20 -30 V+ = 1.8V TO 5.5V -40 14 -50 9 Q (pC) (dB) -60 -70 -80 4 -90 V+ = 5V -100 -1 -110 -120 1k V+ = 1.8V 10k 100k 1M 10M 100M 1G -6 0.0 0.5 1.0 1.5 FREQUENCY (Hz) FIGURE 16. OFF ISOLATION 2.0 2.5 V+ = 3V 3.0 3.5 4.0 4.5 5.0 VCOM (V) FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 57 PROCESS: Submicron CMOS © Copyright Intersil Americas LLC 2007-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN6550 Rev 3.00 May 6, 2013 Page 11 of 13 ISL54501, ISL54502 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) L6.1.2x1.0A A B E 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS PIN 1 REFERENCE 2X 0.10 C 2X D 0.10 C MIN NOMINAL MAX NOTES A 0.45 0.50 0.55 - A1 - - 0.05 - A3 TOP VIEW DETAIL A 0.10 C 7X SYMBOL A 0.08 C 0.127 REF b 0.15 0.20 0.25 5 D 0.95 1.00 1.05 - E 1.15 1.20 1.25 - 0.40 BSC e A1 A3 SIDE VIEW C SEATING PLANE 4X e DETAIL B 1 5X L 3 - L 0.30 0.35 0.40 - L1 0.40 0.45 0.50 - N 6 2 Ne 3 3  L1 - 0 - 12 4 Rev. 2 8/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 6 4 BOTTOM VIEW b 6X 0.10 C A B 0.05 C NOTE 3 0.1x45° CHAMFER 2. N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. A3 A1 DETAIL A DETAIL B PIN 1 LEAD 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 1.00 1.40 0.20 0.30 0.45 0.20 0.35 0.40 LAND PATTERN FN6550 Rev 3.00 May 6, 2013 10 Page 12 of 13 ISL54501, ISL54502 Package Outline Drawing P6.064A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° 0.95 D 0.08-0.20 A 5 6 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 1 (0.60) 3 2 0.20 C 2x 0.40 ±0.05 B 5 SEE DETAIL X 3 0.20 M C A-B D TOP VIEW 2.90 5 END VIEW 10° TYP (2 PLCS) 0.15 C A-B 2x H 1.14 ±0.15 C SIDE VIEW 0.10 C 0.05-0.15 1.45 MAX SEATING PLANE DETAIL "X" (0.25) GAUGE PLANE 0.45±0.1 4 (0.60) (1.20) NOTES: (2.40) (0.95) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (1.90) TYPICAL RECOMMENDED LAND PATTERN FN6550 Rev 3.00 May 6, 2013 Page 13 of 13