ISL55210IRTZ-T7A

DATASHEET ISL55210 FN7811 Rev 2.00 Jun 6, 2013 Wideband, Low-Power, Ultra-High Dynamic Range Differential Amplifier The ISL55210 is a very wide band, Fully Differential Amplifier (FDA) intended for high dynamic range ADC input interface applications. This voltage feedback FDA design includes an independent output common mode voltage control. Features Intended for very high dynamic range ADC interface applications, at the lowest quiescent power (115mW), the ISL55210 offers a 4.0GHz Gain Bandwidth Product with a very low input noise of 0.85nV/√(Hz). In a balanced differential I/O configuration, with 2VP-P output into a 200Ω load configured for a gain of 15dB, the IM3 terms are output VCM +0.5V. This would only occur if the single source was coming from a higher voltage than the output VCM setting. Power Supply, Shutdown, and Thermal Considerations The ISL55210 is intended for single supply operation from 3.0V to 4.2V with an absolute maximum setting of 4.5V. The 3.3V supply current is trimmed to be nominally 35mA at +25°C ambient. Figure 27 shows the supply current for nominal +25°C and -40°C to +85°C operation over the specified maximum supply range. The input stage is biased from an internal voltage referenced from the negative supply giving the exceptional 90dB low frequency PSRR shown in Figure 25. Since the input stage bias is from a re-regulated internal supply, a simple approach to single +5V operation can be supported as shown in Figure 32. Here, a simple IR drop from the +5V supply will bring the operating supply voltage for the ISL55210 into its allowed range. Figure 32 shows example calculations for the voltage range at the ISL55210 +VS pin assuming a ±5% tolerance on the +5V supply and a 35mA to 55mA range on the total supply current. Considering the 34mA to 44mA quiescent current range from Figure 27 over the -40°C to +85°C ambient, and the 3.4V to 4.4V supply voltage range assumed here, this is designing for a 1mA to 11mA average load current which should be adequate for most intended application loads. Good supply decoupling at the device pins is required for this simple solution to still provide exceptional SFDR performance. FN7811 Rev 2.00 Jun 6, 2013 +5V ±5% 35 24.3 3.4 55mA + RF 4.4V 2.2µF 10nF 10k + C in 1:n RO RG PD V CM Vi VO ISL55210 RO RG - RF FIGURE 32. OPERATING FROM A SINGLE +5V SUPPLY The ISL55210 includes a power shutdown feature that can be used to reduce system power dissipation when signal path operation is not required. This pin (PD) is referenced to the ground pins and must be asserted low to activate the shutdown feature. When not used, a 10kΩ external resistor to +VS should be used to assert a high level at this pin. Digital control on this pin can be either an open collector output (using that 10kΩ pullup) or a CMOS logic line running off the same +VS as the amplifier. For split supply operation, the PD pins must be pulled to below -VS + 0.54V to disable. Since the ISL55210 operates as a differential inverting op amp, there is only modest signal path isolation when disabled as shown in Figure 23. For small input signals, Figure 23 shows about 5dB to 6dB isolation while for large signals, back to back protection diodes across the inputs compress the signal to show actually an improved isolation. This is intended to protect any subsequent devices from large input signals during shutdown. Those diodes limit the maximum overdrive voltage across the input to approximately 0.5V in each polarity. The RG resistors of Test Circuit #1 limit the current into those diodes under this condition. The supply current in shutdown does not reduce to zero as internal circuitry is still active to hold the output common mode voltage at the VCM control input voltage even during shutdown (or the default value). This is intended to hold the ISL55210 output near the desired common mode output level during shutdown. This improves turn on characteristic and keeps the output voltages in a safe range for downstream circuitry. DISABLED OPERATION WARNING IN DC COUPLED DESIGNS When disabled, the output stage provides a nominal DC voltage at the Vcm control pin input or the default internal 1.2V value. Being very low power, any external circuit condition that can cause the output pins to source or sink DC current can move the ISL55210 internal operating points into regions from which it may not recover when the device is enabled. If the external circuitry can force >20µA into the output pins or pull > 1.5mA out of the output pins correct operation is not guaranteed. For designs that might force current into the output stage during disable, adding a resistor to ground on the outputs might provide Page 13 of 19 ISL55210 an effective means of turning that into a low sourcing current condition with minimal impact to the desired signal path operation when enabled. With equal feedback and gain resistors, the total output noise expression becomes very simple. This is: The very low internal power dissipation of the ISL55210, along with the excellent thermal conductivity of the QFN package when the exposed metal pad is tied to a conductive plate, reduces the TJ rise above ambient to very modest levels. Assuming a nominal 115mW dissipation and using the +63°C/W measured thermal impedance from Junction to ambient, gives a rise of only 0.12 * 63 = +7.6°C. Operation at elevated ambient temperatures is easily supported given this very low internal rise to junction. e0 = The maximum internal junction temperatures would occur at maximum supply voltage, +85°C maximum ambient operating, and where the QFN exposed pad is not tied to a conductive layer. Where the QFN must be mounted with an insulating layer to the exposed metal plate, such as in a split supply application, device measurements show an increased thermal impedance junction to ambient of +120°C/W. Using this, and a maximum quiescent internal power on 4.5V absolute maximum, which shows 45mA for +85°C maximum operating ambient from Figure 27, we get 4.5V * 45mA * +120°C/W = +24°C rise above +85°C or approximately +109°C operating TJ maximum - still well below the specified Absolute Maximum operating junction temperature of +135°C. Noise Analysis The decompensated voltage feedback design of the ISL55210 provides very low input voltage and current noise. While a detailed noise model using arbitrary external resistors can be made, most applications will have a balanced feedback network with the two RF (feedback) resistors equal and the two RG (gain) resistors equal. Figure 33 shows the test circuit used to measure the output noise with the noise terms detailed. The aim here was to measure the output noise with two different resistor settings to extract out a model for the input referred En and In terms for just the amplifier itself. 4kTRf * RF 4kTRg * + 25 in 1:1 * ISL55210 in 4kTRg * ADT1-1WT eO * 25 RG 2 (EQ. 1) The NG term in Equation 1 is the Noise Gain = 1 + RF/RG. The last term in Equation 1 captures both the RF and RG resistor noise terms. If we assume a 50Ω source in Test Circuit #1, the total RG resistor value will be 100Ω as that 50Ω will come through the transformer to look like a 50Ω source on each side. This gives a lower noise gain (3V/V) than signal gain (4V/V) for just the amplifier. The total gain in Test Circuit #1 is still approximately 1.4 * 4 = 5.6V/V including the transformer step up. Putting in NG = 3, RF = 200Ω, RG = 100Ω with the ISL55210 noise terms of eni = 0.85nV/√Hz and In = 5pA/√Hz into Equation 1 (4kT = 1.6E - 20J) gives a total output differential noise voltage = 5.26nV/√Hz. Input referring this to the input side of the transformer of Test Circuit #1 gives an input referred spot noise of only 0.88nV/√Hz. This extremely low input referred noise is a combination of low amplifier noise terms and the effect of the input transformer configuration. Driving Cap and Filter Loads Most applications will drive a resistive or filter load. The ISL55210 is robust to direct capacitive load on the outputs up to approximately 10pF. For frequency response flatness, it is best to avoid any output pin capacitance as much as possible - as that capacitance increases, the high frequency portion of the ISL55210 (>1GHz) response will start to show considerable peaking. No oscillations were observed up through 10pF load on each output. For AC coupled applications, an output network that is a small series resistor (10Ω to 50Ω) into a blocking cap is preferred. This series resistor will isolate parasitic capacitance to ground from the internally closed loop output stage of the amplifier and de-queue the self resonance of the blocking capacitors. Once the output stage sees this resistive element first, the remaining part of the filter design can be done without fear of amplifier instability. Driving ADCs eni RG 1µF 2  e ni  NG  + 2  i n R f  + 2  4kTR f NG  - 1µF * RF 4kTRf FIGURE 33. NOISE MODEL AND TEST CIRCUIT 1µF 50 Many of the intended applications for the ISL55210 are as a low power, very high dynamic range, last stage interface to high performance ADCs. The lowest power ADCs, such as the ISLA112P50 shown on the front page, include an innovative "Femto-Charge" internal architecture that eliminates op amps from the ADC design and only passes signal charge from stage to stage. This greatly reduces the required quiescent power for these ADCs but then that signal charge has to be provided by the external circuit at the two input pins. This appears on an ADC like the ISLA112P50 as a clock rate dependent common mode input current that must be supplied by the interface circuit. At 500MHz, this DC current is 1.3mA on each input for the ISLA112P50. Most interfaces will also include an interstage noise power bandlimiting filter between the amplifier and the ADC. This filter needs to be designed considering the loading of the amplifier, FN7811 Rev 2.00 Jun 6, 2013 Page 14 of 19 ISL55210 any VCM level shifting that needs to take place, the filter shape, and this ICM issue into the ADC input pins. Here are 4 example topologies suitable for different situations. 1. AC coupled, broadband RLC interstage filter design. This approach lets the amplifier operate at its desired output common mode, then provides the ADC common mode voltage and current through a bias path as part of the filter design’s last stage R values. The VB is set to include the IR loss from that voltage to the ADC inputs due to the ICM current. This circuit is the one shown on the front page where we get a usable frequency range from about 500kHz to 150MHz. 2. AC coupled, higher frequency range interstage filter design. This design replaces the Rt resistors in Figure 34 with large valued inductors and implements the filter just using shunt resistors at the end of the RLC filter (here, that is just the ADC internal differential Rin). In this case, the ADC VCM can be tied to the centerpoint of the bias path inductors (very much like a Bias-T) to provide the common mode voltage and current to the ADC inputs. These bias inductors do limit the low frequency end of the operation where, with 1µH values, operation from 10MHz to 200MHz is supported using the approach of Figure 35. 3. AC coupled with output side transformer. This design includes an output side transformer, very similar to ADC characterization circuits. This approach allows a slightly lower amplifier output swing (if N > 1 is used) and very easy 2nd order low pass responses to be implemented. It also provides the ICM and VCM bias to the ADC through the transformer centertap. This approach would be attractive for higher ADC input swing targets and more aggressive noise power bandwidth control needs. 4. DC coupled with ADC VCM and ICM provided from the amplifier. Here, DC to very high frequency interstage low pass filters can be provided. Again, the RS element must be low to reduce the IR drop from the VCM of the converter, which now shows up on the output of the ISL55210, to the ADC input pins. In this case, split supplies are required to satisfy the amplifier output and input common mode range limits discussed earlier. Rf RF ADC +3.3V ISL55210 Vcm1 Ls Icm ADC +3.3V IN+ Cb Rs ISL55210 Rt 1.2V Ci n Rin LP VCM1 IN+ 1.2V Ct Cin Rin RT Cb Rt Ls Ct Cb RS Icm R Rt R R s t s v –V I  I  R  =R V V B bcm cm t t cm2 cm LP LS INRf ICM Cb RS Ct Vb Rs LS Ct IN- Vcm2 = 0.535 or 1V RF VCM2 = 0.535 or 1V ICM 2 LpLs FIGURE 34. AC COUPLED, BROADBAND RLC INTERSTAGE FILTER DE SIGN FIGURE 35. AC COUPLED, HIGHER FREQUENCY RLC FILTER DESIGN Rf RF ADC ADC +3.3V ISL55210 VCM1 +3.0V ICM RS Cb ISL55210 1:n Cin Ct VCM2 = 0.535 or 1V Rt 30 2ICM FIGURE 36. AC COUPLED WITH OUTPUT SIDE TRANSFORMER FN7811 Rev 2.00 Jun 6, 2013 Ct Ls -1.1V INICM Rin Rs Ct RF Cin Rt Cb Rt IN+ Ct Vcm Rin RS Icm Rs Rt 1.2V Ls IN+ IN- Rf Icm Rs 30 Vcm = 0.535V or 1V FIGURE 37. DC COUPLED WITH A COMMON VCM VOLTAGE FROM THE ADC Page 15 of 19 ISL55210 Layout Considerations The ISL55210 pinout is organized to isolate signal I/O along one axis of the package with ground, power and control pins on the other axis. Ground and power should be planes coming into the upper and lower sides of the package (see the Pin Configuration on page 1). The signal I/O should be laid out as tight as possible with parasitic C to the ground and/or power planes reduced as much as possible by opening up those planes under the I/O elements. The ground pins and package backside metal contact should be connected into a good ground plane. The power supply should have both a large value electrolytic cap to ground, then a high frequency ferrite beads, then 0.01µF SMD ceramic caps at the supply pins. Some improvement in HD2 performance may be experienced by placing and X2Y cap between the two VS+ pins and ground underneath the package on the board back side. This is 4 terminal device that is included in the EVM board layout. EVM Board (Rev. C) Test circuit #1 (Figure 28) is implemented on an Evaluation Module Board available from Intersil. This board includes a number of optional features that are not populated as the board is delivered. The full EVM board circuit is shown in Figure 38 where unloaded (optional) elements are shown in green. The nominal supply voltage for the board and device is a single 3.3V supply. From this, the ISL55210, ISL55211 generates an internal common mode voltage of approximately 1.2V. That voltage can be overridden by populating the two resistors and potentiometer shown as R19 to R21 above. The primary test purpose for this board is to implement different interstage differential passive filters intended for the ADC interface along with the ADC input impedances. The board is delivered with only the output R's loaded to give a 200Ω differential load. This is done using the two 85Ω resistors as R9 and R10, then the 4 zero ohm elements (R10, R12, R24, and R25) and finally the two shunt elements R13 and R14 set to 35.5Ω. Including the 50Ω measurement load on the output side of the 1:1 transformer reflecting in parallel with the two 35Ω resistors takes the nominal AC shunt impedance to 71Ω||50Ω = 29.3Ω. This adds to the two 85Ω series output elements to give a total load across the amplifier outputs of 170Ω + 29.3Ω = 199.3Ω. To test a particular ADC interface RLC filter and converter input impedance, replace R11 and R12 with RF chip inductors, load C10 and C11 with the specified ADC input capacitance and R26 with the specified ADC differential input R. With these loaded, the remaining resistive elements (R24, R25, R13, R14) are set to hit a desired total parallel impedance to implement the desired filter (must be < than the ADC input differential R since that sits in parallel with any "external" elements) and achieve a 25Ω source looking into each side of the tap point transformer. This EVM board includes a user's manual showing a number of example circuits and tested results. Available on the Intersil web site in the ISL55210 Product Information Page. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE June 6, 2013 FN7811.2 Added Related Literature on page 1. Updated Figure “NOISE MODEL AND TEST CIRCUIT” on page 14 that was incorrectly drawn. July 30, 2012 FN7811.1 Added 6th paragraph to section “Power Supply, Shutdown, and Thermal Considerations” on page 13 describing the outputs can not source or sink current during disable mode. March 2, 2011 FN7811.0 Initial Release FN7811 Rev 2.00 Jun 6, 2013 Page 16 of 19 ISL55210 FN7811 Rev 2.00 Jun 6, 2013 C1001 4.7µF GND R21 VCC L1 +Vs + BEAD C1002 1.0µF C3 200Ω/DNP 100nF R19 1k/DNP C2 100nF R18 R17 Cterm2 2.2pF R7 0Ω R8 200Ω 4 13 14 GND Vcm Vs+ GND Vi- NC 11 Vi+ NC Fb- Vo- 1µF 10 C6 9 GND 50Ω 12 R26 DNP TP1 TEST POINT R20 200Ω/DNP C10 DNP 1µF R11 R24 0Ω 0Ω R13 35.5Ω 0Ω/DNP R14 35.5Ω R10 R12 R25 85Ω 0Ω 0Ω 50Ω C5 100nF TP2 DIFPROBE R16 50Ω 1 PD R22 50Ω 2 3 NC VCC 5 A GND Y C8 ADT1-1WT R28 R15 C4 100nF R9 85Ω ISL55210, ISL55211 8 R2 DNP 2 3 R4 R23 0Ω C9 100nF C7 Vo+ Fb+ PD 50Ω R6 0Ω 1 Vs+ R0 DNP R5 200Ω 7 1µF R3 GND ADT2-1T 50Ω U1 6 C1 Cterm1 2.2pF 5 IN R1 DNP 15 16 200Ω C11 DNP 4 74AHC1G04 Page 17 of 19 FIGURE 38. SCHEMATIC FOR ISL55210, ISL55211 SINGLE INPUT TRANSFORMER EVM REV. C 1µF R27 0Ω OUT ISL55210 About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability © Copyright Intersil Americas LLC 2011-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN7811 Rev 2.00 Jun 6, 2013 Page 18 of 19 ISL55210 Package Outline Drawing L16.3x3D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 3/10 4X 1.50 3.00 A 12X 0.50 B 13 6 PIN 1 INDEX AREA 16 6 PIN #1 INDEX AREA 12 3.00 1 1.60 SQ 4 9 (4X) 0.15 0.10 M C A B 5 8 16X 0.40±0.10 TOP VIEW 4 16X 0.23 ±0.05 BOTTOM VIEW SEE DETAIL “X” 0.10 C 0.75 ±0.05 C 0.08 C SIDE VIEW (12X 0.50) (2.80 TYP) ( 1.60) (16X 0.23) C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. (16X 0.60) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.25mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220 WEED. either a mold or mark feature. FN7811 Rev 2.00 Jun 6, 2013 Page 19 of 19