ISL62776IRTZ

Datasheet ISL62776 Multiphase PWM Regulator for AMD CPUs Using SVI2 Features The ISL62776 is fully compliant with AMD Serial VID Interface 2.0 (SVI2) and provides a complete solution for microprocessor and graphics processor core power. The ISL62776 controller supports two Voltage Regulators (VRs) that use external drivers for maximum flexibility. The Core VR can be configured for 4-, 3-, 2-, or 1-phase operation and the SOC VR supports 1-phase operation. The two VRs share a serial control bus to communicate with the AMD CPU and achieve lower cost and smaller board area compared with two-chip solutions. • Supports AMD SVI 2.0 serial data bus interface ○ Serial VID clock frequency range: 100kHz to 25MHz • Dual output controller with PWM output • Precision voltage regulation ○ 0.5% system accuracy over-temperature ○ 0.5V to 1.55V in 6.25mV steps ○ Enhanced load-line accuracy The R3™ modulator, based on the Renesas Robust Ripple Regulator (R3) technology, has many advantages compared to traditional modulators. These include faster transient settling time, variable switching frequency in response to load transients, and improved light-load efficiency due to diode emulation mode with load-dependent, low-switching frequency. • Supports multiple current sensing methods ○ Lossless inductor DCR current sensing ○ Precision resistor current sensing • Programmable phase operation for both Core and SOC VR outputs • Superior noise immunity and transient response Both outputs of the ISL62776 support DC Resistance (DCR) current sensing with single NTC thermistor for DCR temperature compensation or accurate resistor current sensing. Both outputs use remote voltage sense, adjustable switching frequency, Overcurrent Protection (OCP), and power-good. • Output current and voltage telemetry • Differential remote voltage sensing • High efficiency across entire load range • Programmable slew rate Applications • Programmable VID offset and droop on both outputs • AMD CPU/GPU core power • Programmable switching frequency for both outputs • Notebook computers • Excellent dynamic current balance between phases Related Literature • Protection: OCP/WOC, OVP, PGOOD, and thermal monitoring For a full list of related documents, visit our website: • Small footprint 40 Ld 5x5 TQFN package • ISL62776 device page ○ Pb-free (RoHS compliant) 0.850 Output Voltage (V) 0.800 0.750 Core Core SOC SOC 0.700 0.650 0.600 0 20 40 60 80 100 120 Load Current (A) Figure 1. Output Voltage vs Load R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 1 of 49 ISL62776 Contents 1. 1.1 1.2 1.3 1.4 1.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 2.2 2.3 2.4 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 10 3. Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Multiphase R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Standard Buck Operation During Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Differential Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 15 15 16 17 17 18 19 19 23 23 4. Resistor Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 VR Offset Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 VID-on-the-Fly Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 5. AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 27 27 29 30 30 31 2. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6. 4 4 7 8 8 8 Telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7. 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Monitor (NTC, NTC_SOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R16DS0044EU0200 Rev.2.00 Oct.8.20 33 33 33 33 33 34 35 35 Page 2 of 49 ISL62776 8. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9. Selecting Key Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load-Line Slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 39 40 41 42 43 43 44 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 PCB Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 3 of 49 ISL62776 1. 1. Overview Overview 1.1 Simplified Application Circuits VCC VSOC VCC VIN Ri ISUMN_SOC ENABLE VIN FCCM_SOC PWM_SOC VSOC Integrated Power Stage SOC_PH Cn NTC ISUMP_SOC SOC_PH VSOC IMON_SOC COMP_SOC NTC_SOC VSEN_SOC VSOC_SENSE VR_HOT_L Thermal Indicator *Optional * * FB_SOC IMON NTC VCC VIN PROG1 PROG2 PWM4 PWROK Integrated Power Stage SVT PH4 SVD µP SVC VO4 VCC VIN VDDIO COMP PWM3 ISL62776 VSEN Integrated Power Stage PH3 VO3 *Optional * * FB VCORE_SENSE VCC RTN ISEN3 PH2 ISEN2 PH1 ISEN1 VIN ISUMP VO4 GND VO3 NTC GND PAD ISUMN Cn VO2 VCC Ri VO2 Integrated Power Stage PH2 FCCM PGOOD ISEN4 PH3 PWM2 PGOOD_SOC PH4 VO1 VCORE VIN PWM1 Integrated Power Stage PH1 VO1 PH1 PH2 PH3 PH4 Figure 2. Typical Application Circuit for High-Power CPU Core Using Inductor DCR Sensing, 4+1 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 4 of 49 ISL62776 1. Overview VCC VCC Ri VSOC ISUMN_SOC ENABLE VIN VIN FCCM_SOC PWM_SOC VSOC Integrated Power Stage SOC_PH Cn NTC VSOC ISUMP_SOC SOC_PH IMON_SOC COMP_SOC NTC_SOC VSEN_SOC VR_HOT_L Thermal Indicator *Optional * * FB_SOC IMON NTC PROG1 PROG2 PWM4 PWROK SVT SVD µP SVC VCC VIN VDDIO COMP PWM3 ISL62776 VSEN Integrated Power Stage PH3 VO3 *Optional * * FB VCORE_SENSE +5V VCC RTN PWM2 ISEN4 PH2 ISEN2 PH1 ISEN1 VIN NTC FCCM PWM1 Integrated Power Stage PH1 VO1 PH3 PH1 PH2 ISUMP GND VO3 GND PAD ISUMN Cn VO2 VCC Ri VO2 Integrated Power Stage PH2 PGOOD ISEN3 PGOOD_SOC PH3 VO1 VCORE VIN Figure 3. Typical Application Circuit for Mid-Power CPUs Using Inductor DCR Sensing, 3+1 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 5 of 49 ISL62776 1. Overview VSOCN VCC Ri ISUMN_SOC Cn ENABLE VIN VIN FCCM_SOC PWM_SOC VSOC Integrated Power Stage VSOCP NTC VSOCN ISUMP_SOC VSOCP IMON_SOC COMP_SOC NTC_SOC VSEN_SOC VR_HOT_L *Optional * * FB_SOC ISL62776 Thermal Indicator IMON NTC PROG1 PROG2 PWROK PWM4 SVT PWM3 SVD µP SVC VDDIO VCC VIN COMP PWM2 VSEN Integrated Power Stage VN2 *Optional * * FB VCORE_SENSE +5V VCC VIN RTN FCCM ISEN4 PWM1 ISEN3 VN1 ISEN1 VN1 Ri ISUMN Cn VP1 VN2 VN1 ISUMP GND PAD VP2 VCORE Integrated Power Stage PGOOD ISEN2 PGOOD_SOC VN2 VP1 VP2 Figure 4. Typical Application Circuit for Low-Power CPUs Using Resistor Sensing, 2+1 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 6 of 49 ISL62776 1.2 1. Overview Block Diagram VDD CORE_I IMON COMP_SOC Current A/D SOC_I RTN +  + _ FB_SOC E/A FCCM_SOC VR2 Modulator IDROOP_SOC ISUMP_SOC ISUMN_SOC + IMON_SOC + PWM_SOC Current Sense _ PGOOD_SOC OC Fault OV Fault VSEN_SOC SOC_V NTC_SOC NTC Voltage A/D T_MONITOR Temperature Monitor VR_HOT_L Offset Frequency Slew Rate Configuration A/D IDROOP D/A DAC2 DAC1 PWROK Digital Interface SVC PROG2 VIN IDROOP_SOC ENABLE PROG1 CORE_I SVD SOC_I Telemetry SVT CORE_V SOC_V VDDIO FCCM COMP RTN + RTN  PWM1 + VR1 Modulator + _ FB E/A PWM2 PWM3 PWM4 IDROOP ISUMP + ISUMN _ Current Sense Voltage A/D CORE_V ISEN4 ISEN3 ISEN2 Current Balancing OC Fault ISEN1 PGOOD IBAL Fault VSEN OV Fault GND Figure 5. Block Diagram R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 7 of 49 ISL62776 1.3 1. Overview Ordering Information Part Number (Notes 2, 3) Part Marking Temp. Range (°C) Tape and Reel (Units) (Note 1) Package (RoHS Compliant) Pkg. Dwg. # ISL62776HRTZ 62776 HRTZ -10 to +100 - 40 Ld 5x5 TQFN L40.5x5 ISL62776HRTZ-T 62776 HRTZ -10 to +100 6k 40 Ld 5x5 TQFN L40.5x5 ISL62776IRTZ 62776 IRTZ -40 to +100 - 40 Ld 5x5 TQFN L40.5x5 ISL62776IRTZ-T 62776 IRTZ -40 to +100 6k 40 Ld 5x5 TQFN L40.5x5 Notes: 1. See TB347 for details about reel specifications. 2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL62776 device page. For more information about MSL, see TB363. 1.4 Pin Configuration PGOOD_SOC 32 VSEN_SOC 31 FCCM_SOC 33 IMON_SOC 35 ISUMP_SOC 34 ISUMN_SOC 36 FB_SOC 37 COMP_SOC 38 PROG2 1 30 PWM_SOC SVC 2 29 VIN VR_HOT_L 3 28 VSEN SVD 4 VDDIO 5 GND Pad SVT 6 (Bottom) ENABLE 7 24 PWM3 PWROK 8 23 PWM2 PGOOD 9 22 PWM1 NTC 10 21 FCCM 26 VCC ISUMP 18 25 PWM4 ISUMN 19 IMON 20 ISEN2 15 ISEN3 16 ISEN4 17 ISEN1 14 FB 13 COMP 12 27 RTN PROG1 11 1.5 39 NTC_SOC 40 NC 40 Ld TQFN Top View Pin Descriptions Pin Number Pin Name 1 PGOOD_SOC 2 SVC 3 VR_HOT_L 4 SVD 5 VDDIO 6 SVT 7 ENABLE Enable input. A high-level logic on this pin enables both VRs. 8 PWROK System power-good input. When this pin is high, the SVI2 logic is active. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must be low prior to the ISL62776 PGOOD output going high, per the AMD SVI2 Controller Guidelines. Description Open-drain output to indicate the SOC portion of the IC is ready to supply the regulated voltage. Pull-up externally to VDDP or 3.3V through a resistor (minimum 1kΩ). Serial VID clock input from the CPU processor master device. Thermal indicator signal to the AMD processor. Thermal overload open-drain output indicator active Low. Serial VID data bidirectional signal from the CPU processor master device to the VR. VDDIO is the processor memory interface power rail. This pin serves as the I/O signal level reference to the controller IC for this processor. Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly complete signal provided from this pin. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 8 of 49 ISL62776 1. Overview Pin Number Pin Name 9 PGOOD 10 NTC 11 PROG 38 PROG2 12 COMP 13 FB 14 ISEN1 Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, ISEN1 must be tied to GND through a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is shut down. 15 ISEN2 Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller disables Channel 2, and the Core VR runs in single-phase mode. Do not leave this pin floating. 16 ISEN3 Individual current sensing for Channel 3 of the Core VR. When ISEN3 is pulled to +5V, the controller disables Channel 3, and the Core VR runs in two-phase mode. Do not leave this pin floating. 17 ISEN4 Individual current sensing for Channel 4 of the Core VR. When ISEN4is pulled to +5V, the controller disables Channel 4, and the Core VR runs in three-phase mode. Do not leave this pin floating. 18 ISUMP Noninverting input of the transconductance amplifier for current monitor and load line of Core output. See Inductor DCR Current-Sensing Network. 19 ISUMN Inverting input of the transconductance amplifier for current monitor and load line of Core output. See Inductor DCR Current-Sensing Network. 20 IMON Core output current monitor. A current proportional to the Core VR output current is sourced from this pin. Renesas recommends tying a 133kΩresistor from IMON to GND. 21 FCCM Diode emulation control signal for Core. When FCCM is High, continuous conduction mode is forced. When FCCM is LOW, diode emulation at the driver this pin connects to is allowed. 22, 23, 24, 25 PWM1, 2, 3, 4 26 VCC 5V bias power. A resistor (2Ω) and a decoupling capacitor should be used from the +5V supply. A high quality, X7R dielectric, 0.1µF minimum, MLCC capacitor is recommended. 27 RTN Output voltage sense return pin for both Core VR and SOC VR. Connect to the -sense pin of the microprocessor die. 28 VSEN 29 VIN 30 PWM_SOC PWM output for SOC regulator. When tri-stated, this pin is at a high impedance state. 31 FCCM_SOC Diode emulation control signal for SOC. When FCCM_SOC is High, continuous conduction mode is forced. When FCCM_SOC is LOW, diode emulation at the driver this pin connects to is allowed. 32 VSEN_SOC Output voltage sense pin for the SOC controller. Connect to the +sense pin of the microprocessor die. 33 IMON_SOC SOC output current monitor. A current proportional to the SOC VR output current is sourced from this pin. Renesas recommends tying a 133kΩresistor from IMON_SOC to GND. 34 ISUMN_SOC Inverting input of the transconductance amplifier for current monitor and load line of the SOC VR. See Inductor DCR Current-Sensing Network. 35 ISUMP_SOC Noninverting input of the transconductance amplifier for current monitor and load line of the SOC VR. See Inductor DCR Current-Sensing Network. 36 FB_SOC 37 COMP_SOC 39 NTC_SOC 40 NC - Description Open-drain output indicates the Core portion of the IC is ready to supply the regulated voltage. Pull-up externally to VDD or 3.3V through a resistor (minimum 1kΩ). Thermistor input to VR_HOT_L circuit to monitor the Core VR temperature. Programming pins. See VR Offset Programming. Core controller error amplifier output. See Figure 2 for general component connections. Output voltage feedback to the inverting input of the Core controller error amplifier. See Figure 2 for general component connections. PWM outputs for the Core regulator. When tri-stated, these pins are at a high impedance state. Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die. Battery supply voltage, used for feed-forward and modulation. Output voltage feedback to the inverting input of the SOC controller error amplifier. See Figure 2 for general component connection. SOC VR error amplifier output. See Figure 2 for general component connections. Thermistor input to VR_HOT_L circuit to monitor SOC VR temperature. No connected GND (Bottom Pad) Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 9 of 49 ISL62776 2. 2.1 2. Specifications Specifications Absolute Maximum Ratings Parameter Minimum Maximum Unit -0.3 +7 V +28 V Supply Voltage, VDD Battery Voltage, VIN All Other Pins -0.3 VDD + 0.3V V Open-Drain Outputs, PGOOD, PGOOD_SOC, VR_HOT_L -0.3 +7 V ESD Rating Value Unit Human Body Model (Tested per JS-001-2017) 2 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 29 3.5 40 Ld TQFN Package (Notes 4, 5) Notes: 4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 5. For JC, the case temperature location is the center of the exposed metal pad on the package underside. Parameter Minimum Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range -65 Pb-Free Reflow Profile 2.3 Maximum Unit +150 °C +150 °C See TB493 Recommended Operating Conditions Parameter Minimum Supply Voltage, VDD Maximum Unit 5 ±5% V Battery Voltage, VIN 4.5 25 V Junction Temperature -10 +125 °C HRZ -10 +100 °C IRZ -40 +100 °C Ambient Temperature 2.4 Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +100°C (IRZ), fSW = 300kHz, unless otherwise noted. Parameter Symbol Test Conditions Min (Note 6) Typ Max (Note 6) Unit 11 13 mA 3.5 µA Input Power Supply +5V Supply Current IVDD ENABLE = 4V ENABLE = 0V R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 10 of 49 ISL62776 2. Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +100°C (IRZ), fSW = 300kHz, unless otherwise noted. (Continued) Parameter Symbol Test Conditions Min (Note 6) Typ Battery Supply Current IVIN ENABLE = 0V VIN Input Resistance RVIN ENABLE = 4V, VIN = 15V 310 VCC_PORr VCC rising 4.35 VCC_PORf VCC falling Max (Note 6) Unit 1 µA kΩ Power-On Reset Thresholds VCC POR Threshold 4.00 4.5 4.15 V V System and References System Accuracy, Core %Error (VOUT) No load; closed loop, active mode range, VID = 0.75V to 1.55V (HRZ) VID = 0.25V to 0.74375V (HRZ) %Error (VOUT) No load; closed loop, active mode range, VID = 0.75V to 1.55V (IRZ) VID = 0.25V to 0.74375V (IRZ) System Accuracy, SOC %Error (VOUT) No load; closed loop, active mode range, VID = 0.75V to 1.55V (HRZ) VID = 0.25V to 0.74375V (HRZ) %Error (VOUT) No load; closed loop, active mode range, VID = 0.75V to 1.55V (IRZ) VID = 0.25V to 0.74375V (IRZ) -0.5 +0.5 % -10 +10 mV -0.8 +0.8 % -12 +12 mV -1 +1 % -20 +20 mV -1.6 +1.6 % -24 +24 mV Maximum Output Voltage VOUT(max) VID = [00000000] 1.55 V Minimum Output Voltage VOUT(min) VID = [11111111] 0 V Channel Frequency Nominal Channel Frequency fSW(nom) 400 450 510 kHz 540 600 665 kHz 680 750 810 kHz 910 1000 1070 kHz Amplifiers Current-Sense Amplifier Input Offset Error Amplifier DC Gain Error Amplifier Gain-Bandwidth Product IFB = 0A (HRZ) -0.2 +0.2 mV IFB = 0A (IRZ) -0.25 +0.25 mV AV0 GBW CL = 20pF 119 dB 17 MHz 20 nA ISEN Input Bias Current Power-Good (PGOOD and PGOOD_SOC) and Protection Monitors PGOOD Low Voltage VOL IPGOOD = 4mA PGOOD Leakage Current IOH PGOOD = 3.3V PWROK High Threshold VR_HOT_L Pull-Down -1 0.4 V 1 µA 750 mV 11 Ω PWROK Leakage Current 1 µA VR_HOT_L Leakage Current 1 µA R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 11 of 49 ISL62776 2. Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +100°C (IRZ), fSW = 300kHz, unless otherwise noted. (Continued) Parameter Symbol Test Conditions Min (Note 6) Typ Max (Note 6) Unit Protection Overvoltage Threshold OVH ISUMN rising above setpoint for >1µs 275 325 375 mV Undervoltage Threshold UVH ISUMN falls below setpoint for >1µs 275 325 375 mV Current Imbalance Threshold One ISEN above another ISEN for >1.2ms 25 mV 15 µA Way Overcurrent Trip Threshold (IMONx Current Based Detection) IMONxWOC All states, IDROOP = 60µA, RIMON = 135kΩ Overcurrent Trip Threshold (IMONx Voltage Based Detection) VIMONx_OCP All states, IDROOP = 45µA, IIMONx = 11.25µA, RIMON = 135kΩ 1.475 1.505 1.535 V 1 V Logic Thresholds ENABLE Input Low VIL ENABLE Input High VIH ENABLE Leakage Current IENABLE HRZ 1.6 V IRZ 1.65 V ENABLE = 0V -1 0 1 µA ENABLE = 1V -1 0 1 µA SVT Impedance 50 SVC Frequency Range 0.1 Ω 21 MHz 30 % SVC, SVD Input Low VIL % of VDDIO SVC, SVD Input High VIH % of VDDIO 70 ENABLE = 0V; SVC, SVD = 0V and 1V -1 1 µA ENABLE = 4V; SVC, SVD = 1V -5 1 µA ENABLE = 4V; SVC, SVD = 0V -35 -5 µA 1.0 V SVC, SVD Leakage % -22 PWM PWM Output Low V0L Sinking 5mA PWM Output High V0H Sourcing 5mA PWM Tri-State Leakage 3.5 PWM = 2.5V V 1 µA Thermal Monitor NTC Source Current NTC = 0.6V NTC Thermal Warning Voltage 27 30 33 µA 610 650 690 mV NTC Thermal Warning Voltage Hysteresis 25 NTC Thermal Shutdown Voltage mV 550 590 630 mV Maximum programmed 16 20 24 mV/µs Minimum programmed 8 10 12 mV/µs Slew Rate VID-on-the-Fly Slew Rate Note: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 12 of 49 ISL62776 3. 3.1 3. Theory of Operation Theory of Operation Multiphase R3 Modulator The ISL62776 is a multiphase regulator that implements two voltage regulators, Core VR and SOC VR, on one chip controlled by AMD’s SVI 2.0 protocol. The Core VR can be programmed for 1-, 2-, 3-, or 4-phase operation. The SOC VR is a 1-phase regulator. Both regulators use the Renesas proprietary R3 (Robust Ripple Regulator) modulator. The R3 modulator combines the best features of PWM, such as fixed frequency and hysteretic, and eliminates many of its shortcomings. Figure 6 conceptually shows the multiphase R3 modulator circuit and Figure 7 shows the operational principles. 0DVWHU&ORFN&LUFXLW 9: 0DVWHU&ORFN 0DVWHU&ORFN *092 &203 3KDVH 6HTXHQFHU 9&50 &/2&. &/2&. &/2&. &UP 6ODYH&LUFXLW 9: &/2&. 6 5 3:0 3+$6( / ,/ 9&56 92 4 &2 JP &UV 6ODYH&LUFXLW 9: &/2&. 6 5 3:0 3+$6( / 4 ,/ 9&56 JP &UV 6ODYH&LUFXLW 9: &/2&. 6 5 3:0 3+$6( / 4 ,/ 9&56 JP &UV Figure 6. R3 Modulator Circuit Inside the IC, the modulator uses the master clock circuit to generate the clocks for slave circuits. The modulator discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. The Crm voltage, VCRM, is a sawtooth waveform traversing between the VW and COMP voltages. The Crm voltage resets to VW when it reaches COMP and generates a one-shot master clock signal. A phase sequencer distributes the master clock signal to the slave circuits. • If the Core VR is in 3-phase mode, the master clock signal is distributed to the three phases and the Clock1 through Clock3 signals are 120 degrees out-of-phase • If the Core VR is in 2-phase mode, the master clock signal is distributed to Phases 1 and 2 and the Clock1 and Clock2 signals are 180 degrees out-of-phase • If the Core VR is in 1-phase mode, the master clock signal is distributed to Phase 1 only and is the Clock1 signal R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 13 of 49 ISL62776 3. Theory of Operation 9: 9&50 +\VWHUHWLF:LQGRZ &203 0DVWHU &ORFN &/2&. 3:0 &/2&. 3:0 &/2&. 3:0 9: 9&UV 9&UV 9&UV Figure 7. R3 Modulator Operational Principles in Steady State Each slave circuit has its own ripple capacitor Crs; whose voltage mimics the inductor ripple current. A gm amplifier converts the inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse when it receives the clock signal and the current source charges Crs. When the Crs voltage VCrs reaches VW, the slave circuit turns off the PWM pulse and the current source discharges Crs. Because the controller works with VCrs, which is a large amplitude and noise-free synthesized signal, it achieves lower phase jitter than conventional hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode converters, the error amplifier allows the ISL62776 to maintain a 0.5% output voltage accuracy. Figure 8 shows the operational principles during load insertion response. The COMP voltage rises during load insertion, quickly generating the master clock signal, so the PWM pulses turn on earlier to increase the effective switching frequency, allowing for higher control loop bandwidth than conventional fixed frequency PWM controllers. The VW voltage rises as the COMP voltage rises, making the PWM pulses wider. During load release response, the COMP voltage falls. The master clock circuit takes longer to generate the next master clock signal so the PWM pulse is held off until needed. The VW voltage falls as the COMP voltage falls, reducing the current PWM pulse-width. This behavior gives the ISL62776 excellent response speed. All the phases share the same VW window voltage, ensuring excellent dynamic current balance among phases. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 14 of 49 ISL62776 3. Theory of Operation 9: &203 9&50 0DVWHU &ORFN &/2&. 3:0 &/2&. 3:0 &/2&. 3:0 9: 9&UV 9&UV 9&UV Figure 8. R3 Modulator Operational Principles in Load Insertion Response 3.2 Standard Buck Operation During Soft-Start At startup, during the initial rise of the output voltage, the ISL62776 forces the regulator into a standard buck mode. From the initial PWM pulse until the DAC reaches approximately 480mV, the regulator operates in this mode. Once the DAC has exceeded approximately 480mV, the ISL62776 goes into synchronous buck operation. To achieve standard buck mode, the PWM signal is tri-stated (high impedance) when the upper device is turned off. In compatible drivers and power stages, both upper and lower pass devices should be turned off when they see a tri-stated PWM signal. 3.3 Diode Emulation and Period Stretching With a compatible MOSFET driver or power stage, the regulator controlled by the ISL62776 can operate in Diode Emulation Mode (DEM). For the driver or power stage to be DEM compatible, they must be able to accept the FCCM signal from the ISL62776. For proper compatibility, the driver or power stage should also disable both upper and lower pass devices when the PWM signal they receive is tri-stated (high impedance state). When the FCCM signal is High, the driver or power stage must be in Forced Continuous Conduction Mode, meaning that the upper pass device must be on and the lower pass device must be off when the PWM signal is High. Also, when the PWM signal is Low, the upper pass device must be off and the lower pass device must be on. When the FCCM signal is Low, the driver or power stage must operate in DEM. When the PWM signal is High, the upper pass device is on and the lower pass device is off. When the PWM signal is Low, the upper pass device must be off. The lower pass device should be on only while inductor current is greater than 0A. Once the inductor current reaches 0A, both pass devices should be off until the PWM signal goes High again. One method that is commonly utilized by drivers and power stages to be DEM compatible is to monitor the Phase voltage while the low pass element is on. As Figure 9 shows, when the Phase voltage crosses zero volts, the lower pass device turns off. If the load current is light enough, as Figure 9 shows, the inductor current reaches and stays at zero before the next phase node pulse, and the regulator is in Discontinuous Conduction Mode (DCM). If the load current is heavy enough, the inductor current never reaches 0A and the regulator is in Continuous Condution Mode (CCM) although the controller is in DEM. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 15 of 49 ISL62776 3. Theory of Operation 3+$6( 8*$7( /*$7( ,/ Figure 9. Diode Emulation Figure 10 shows the operation principle in DEM at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size and therefore is the same, so the inductor current triangle is the same in the three cases. The ISL62776 clamps the ripple capacitor voltage VCrs in DEM to make it mimic the inductor current. The COMP voltage takes longer to reach VCrs, which naturally stretches the switching period. The inductor current triangles move farther apart, so that the inductor current average value is equal to the load current. The reduced switching frequency helps increase light-load efficiency. 9: &&0'&0 %RXQGDU\ 9: /LJKW'&0 9&UV ,/ 9&UV ,/ 9: 'HHS'&0 9&UV ,/ Figure 10. Period Stretching 3.4 Channel Configuration The individual PWM channels of either VR can be disabled by connecting the ISENx pin to +5V. For example, placing the controller in a 3+1 configuration, as shown in Figure 3, requires ISEN4 of the Core VR to be tied to +5V. ISEN4 disables Channel 4 of the Core VR. Connecting ISEN1 to +5V disables the Core VR output. This feature allows debugging of individual VR outputs. The ISENx pins must not float. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 16 of 49 ISL62776 3.5 3. Theory of Operation Power-On Reset The ISL62776 requires a +5V input supply tied to VDD to exceed the VDD rising Power-On Reset (POR) threshold before the controller has sufficient bias to ensure proper operation. When this threshold is reached or exceeded, and ENABLE is taken high, the ISL62776 has enough bias to check the state of the SVI inputs. Hysteresis between the rising and the falling thresholds ensures the ISL62776 does not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications on page 10). Note: VIN must be present for the controller to drive the output voltage. 1 2 3 4 5 6 7 8 VDD SVC SVD VOTF SVT Telemetry Telemetry ENABLE PWROK METAL_VID VCORE/ VCORE_SOC V_SVI PGOOD and PGOOD_SOC Interval 1 to 2: The ISL62776 waits to POR. Interval 2 to 3: SVC and SVD are externally set to the pre-Metal VID code. Interval 3 to 4: ENABLE locks the pre-Metal VID code. Both outputs soft-start to this level. Interval 4 to 5: The PGOOD signal goes HIGH, indicating proper operation. Interval 5 to 6: PGOOD and PGOOD_SOC high are detected and PWROK is taken high. The ISL62776 is prepared for SVI commands. Interval 6 to 7: The SVC and SVD data lines communicate change in VID code. Interval 7 to 8: The ISL62776 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes. Post 8: Telemetry is clocked out of the ISL62776. Figure 11. SVI Logic Timing Diagram: Typical Pre-PWROK Metal VID Start-Up 3.6 Start-Up Timing The controller start-up sequence begins when VDD is above the POR threshold and ENABLE exceeds the logic high threshold. Figure 12 shows the typical soft-start timing of the Core and SOC VRs. When the controller registers ENABLE as a high, the controller checks the state of a few programming pins during the typical 8ms delay before soft-starting the Core and SOC outputs. The pre-PWROK Metal VID is read from the state of the SVC and SVD pins and programs the DAC, and the programming resistors on PROG1 and PROG2 are read to configure switching frequency, slew rate, and output offsets. See Resistor Configuration Options for more information about the programming resistors. The ISL62776 uses a digital soft-start to ramp up the DAC to the Metal VID level programmed. PGOOD is asserted high at the end of the soft-start ramp. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 17 of 49 ISL62776 3. Theory of Operation VDD Slew Rate ENABLE MetalVID VID Command Voltage ~3ms DAC PGOOD PWROK VIN Figure 12. Typical Soft-Start Waveforms 3.7 Voltage Regulation and Load Line Implementation After the soft-start sequence, the ISL62776 regulates the output voltages to the pre-PWROK metal VID programmed. See Table 4. The ISL62776 controls the no-load output voltage to an accuracy of ±0.5% across the range of 0.75V to 1.55V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. As the load current increases from zero, the output voltage droops from the VID programmed value by an amount proportional to the load current to achieve the load line. The ISL62776 can sense the inductor current through the intrinsic DC Resistance (DCR) of the inductors as shown in Figures 2 and 3, or through resistors in series with the inductors as shown in Figure 4. In both methods, the capacitor Cn voltage represents the total inductor current. An internal amplifier converts the Cn voltage into an internal current source, Isum, with the gain set by resistor Ri. See Equation 1. (EQ. 1) V Cn I sum = --------Ri The Isum current is used for load-line implementation, current monitoring on the IMON pins, and overcurrent protection. Figure 13 shows the load-line implementation. Rdroop VCCSENSE = VOUT + Vdroop - FB Catch Resistor Idroop - COMP E/A + VIDs + DAC  VDAC + + Internal to IC X1 - VR Local VOUT VID RTN VSSSENSE VSS Catch Resistor Figure 13. Differential Sensing and Load-Line Implementation The ISL62776 drives a current source (Idroop) out of the FB pin, which is a ratio of the Isum current, as described by Equation 2. (EQ. 2) 5 V Cn 5 I droop = ---  I sum = ---  ---------4 4 Ri R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 18 of 49 ISL62776 3. Theory of Operation When using inductor DCR current sensing, a single NTC element compensates the positive temperature coefficient of the copper winding, sustaining the load-line accuracy with reduced cost. Idroop flows through resistor Rdroop and creates a voltage drop as shown in Equation 3. (EQ. 3) V droop = R droop  I droop Vdroop is the droop voltage required to implement load line. Changing Rdroop or scaling Idroop can change the load line slope. Because Isum sets the overcurrent protection level, Renesas recommends first scaling Isum based on the OCP requirement, then selecting an appropriate Rdroop value to get the required load line slope. 3.8 Differential Sensing Figure 13 also shows the differential voltage sensing scheme. VCCSENSE and VSSSENSE are the remote voltage sensing signals from the processor die. A unity gain differential amplifier senses the VSSSENSE voltage and adds it to the DAC output. The error amplifier regulates the inverting and noninverting input voltages to be equal as shown in Equation 4: (EQ. 4) VCC SENSE + V droop = V DAC + VSS SENSE Rewriting Equation 4 and substituting Equation 3 gives Equation 5, the exact equation required for load-line implementation. (EQ. 5) VCC SENSE – VSS SENSE = V DAC – R droop  I droop The VCCSENSE and VSSSENSE signals come from the processor die. The feedback is an open circuit in the absence of the processor. Figure 13 shows the recommended catch resistor to feed the VR local output voltage back to the compensator and another catch resistor to connect the VR local output ground to the RTN pin. These resistors, typically 10Ω~100Ω, provide voltage feedback if the system is powered up without a processor installed. 3.9 Phase Current Balancing The ISL62776 monitors individual phase average current by monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 14 shows the recommended current balancing circuit for DCR sensing. Rdcr3 L3 ISEN3 PHASE3 Risen Cisen Internal to IC ISEN2 IL3 Rdcr2 L2 Rpcb2 PHASE2 Risen VO IL2 Cisen ISEN1 Rpcb3 Rdcr1 L1 Rpcb1 PHASE1 Risen IL1 Cisen Figure 14. Current Balancing Circuit R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 19 of 49 ISL62776 3. Theory of Operation Each phase node voltage is averaged by a low-pass filter consisting of Risen and Cisen and is presented to the corresponding ISEN pin. Route Risen to the inductor phase-node pad to eliminate the effect of phase node parasitic PCB DCR. Equations 6 through 8 give the ISEN pin voltages: (EQ. 6) V ISEN1 =  R dcr1 + R pcb1   I L1 (EQ. 7) V ISEN2 =  R dcr2 + R pcb2   I L2 (EQ. 8) V ISEN3 =  R dcr3 + R pcb3   I L3 where Rdcr1, Rdcr2, and Rdcr3 are inductor DCR; Rpcb1, Rpcb2, and Rpcb3 are parasitic PCB DCR between the inductor output side pad and the output voltage rail; and IL1, IL2, and IL3 are inductor average currents. The ISL62776 adjusts the phase pulse-width relative to the other phases to make VISEN1 = VISEN2 = VISEN3. This adjustment yields IL1 = IL2 = IL3 when Rdcr1 = Rdcr2 = Rdcr3 and Rpcb1 = Rpcb2 = Rpcb3. Using the same components for L1, L2, and L3 provides a good match of Rdcr1, Rdcr2, and Rdcr3. Board layout determines Rpcb1, Rpcb2, and Rpcb3. Renesas recommends a symmetrical layout for the power delivery path between each inductor and the output voltage rail so that Rpcb1 = Rpcb2 = Rpcb3. Symmetrical layout can be difficult to implement. For the circuit shown in Figure 14, asymmetric layout causes different Rpcb1, Rpcb2, and Rpcb3 values, which creates a current imbalance. Figure 15 shows a differential sensing current balancing circuit recommended for ISL62776. Route the current sensing traces to the inductor pads so they pick up only the inductor DCR voltage. Each ISEN pin sees the average voltage of three sources: its own, the phase inductor phase-node pad, and the other two phase inductor output side pads. PHASE3 R isen V3p ISEN3 C isen Internal to IC ISEN2 Cisen Rdcr3 L3 IL3 R isen R pcb3 V 3n R isen V2p PHASE2 R isen Rdcr2 L2 IL2 R isen Rpcb2 Vo V 2n R isen ISEN1 Cisen PHASE1 V1p R isen R isen Rdcr1 L1 IL1 R pcb1 V 1n R isen Figure 15. Differential-Sensing Current Balancing Circuit Equation 9 through Equation 11 give the ISEN pin voltages: (EQ. 9) V ISEN1 = V 1p + V 2n + V 3n (EQ. 10) V ISEN2 = V 1n + V 2p + V 3n (EQ. 11) V ISEN3 = V 1n + V 2n + V 3p R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 20 of 49 ISL62776 3. Theory of Operation The ISL62776 makes VISEN1 = VISEN2 = VISEN3 as shown in Equation 12 and Equation 13: (EQ. 12) V 1p + V 2n + V 3n = V 1n + V 2p + V 3n (EQ. 13) V 1n + V 2p + V 3n = V 1n + V 2n + V 3p Rewriting Equation 12 gives Equation 14: (EQ. 14) V 1p – V 1n = V 2p – V 2n Rewriting Equation 13 gives Equation 15: (EQ. 15) V 2p – V 2n = V 3p – V 3n Combining Equation 14 and 15 gives Equation 16: (EQ. 16) V 1p – V 1n = V 2p – V 2n = V 3p – V 3n Therefore: (EQ. 17) R dcr1  I L1 = R dcr2  I L2 = R dcr3  I L3 Current balancing (IL1 = IL2 = IL3) is achieved when Rdcr1 = Rdcr2 = Rdcr3. Rpcb1, Rpcb2, and Rpcb3 have no effect. Because the slave ripple capacitor voltages mimic the inductor currents, the R3 modulator can naturally achieve excellent current balancing during steady state and dynamic operations. Figure 16 shows the current balancing performance of the evaluation board with a load transient of 12A/51A at different repetition rates. The inductor currents follow the load current dynamic change with the output capacitors supplying the difference. The inductor currents can track the load current at a low repetition rate, but cannot keep up when the repetition rate is in the hundred-kHz range, where it is outside of the control loop bandwidth. The controller achieves excellent current balancing in all cases installed. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 21 of 49 ISL62776 3. Theory of Operation Rep Rate = 10kHz Rep Rate = 25kHz Rep Rate = 50kHz Rep Rate = 100kHz Rep Rate = 200kHz Figure 16. Current Balancing During Dynamic Operation. CH1: IL1, CH2: ILOAD, CH3: IL2, CH4: IL3 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 22 of 49 ISL62776 3.10 3. Theory of Operation Modes of Operation The Core VR can be configured for 4-, 3-, 2-, or 1-phase operation. Table 1 shows the Core VR configurations and operational modes, programmed by the ISEN4, ISEN3, and ISEN2 pin status and the PSL0_L and PSL1_L commands from the SVI2 interface. See Table 7 for more information about PSL0_L and PSL1_L. Table 1. Core VR Modes of Operation Configuration 4-Phase Core 3-Phase Core 2-Phase Core 1-Phase Core ISEN4 To Power Stage Tied to 5V Tied to 5V Tied to 5V ISEN3 To Power Stage To Power Stage Tied to 5V Tied to 5V ISEN2 To Power Stage To Power Stage To Power Stage Tied to 5V PSL0_L and PSL1_L Mode 11 4-Phase CCM 01 1-Phase CCM 00 1-Phase DEM 11 3-Phase CCM 01 1-Phase CCM 00 1-Phase DEM 11 2-Phase CCM 01 1-Phase CCM 00 1-Phase DEM 11 1-Phase CMM 01 1-Phase CCM 00 1-Phase DEM In a 4-phase configuration, the Core VR operates in 4-phase CCM, with PSI0_L and PSI_L both high. If PSI0_L goes low using the SVI 2 interface, the Core VR sheds Phases 4, 3, and 2. Phase 1 operates in CCM. When both PSI0_L and PSI1_L go low, the Core VR operates in 1-phase DEM. In a 3-phase configuration, the Core VR operates in 3-phase CCM, with PSI0_L and PSI_L both high. If PSI0_L goes low by the SVI 2 interface, the Core VR sheds Phase 2 and Phase 3. Phase 1 operates in CCM. When both PSI0_L and PSI1_L go low, the Core VR operates in 1-phase DEM. Tie the ISEN4 pin to 5V. Phases 1, 2, and 3 are active in this configuration. In a 2-phase configuration, the Core VR operates in 2-phase CCM with PSI0_L and PSI_L both high. If PSI0_L goes low by the SVI 2 interface, the Core VR sheds Phase 2 and the Core VR operates in 1-phase CCM. When both PSI0_L and PSI1_L go low, the Core VR operates in 1-phase DEM. Tie the ISEN4 and ISEN3 pins to 5V. Phases 1 and 2 are active in this configuration. In a 1-phase configuration, the Core VR operates in 1-phase CCM and stays in 1-phase CCM when PSI0_L goes low. When both PSI0_L and PSI1_L go low, the Core VR operates in 1-phase DEM. Tie the ISEN4, ISEN3, and ISEN2 pins to 5V. Only Phase 1 is active in this configuration. The Core VR can be disabled by connecting ISUMN to +5V. The SOC VR operates in 1-phase CCM and stays in 1-phase CCM when PSI0_L goes low. When both PSI0_L and PSI1_L go low, the SOC VR operates in 1-phase DEM. Connect ISUMN_SOC to +5V to disable the SOC VR. The Core and SOC VRs have an overcurrent threshold of 1.5V on IMON and IMON_SOC, respectively. This level does not vary based on channel configuration. See Overcurrent for more information. 3.11 Dynamic Operation The Core VR and SOC VR behave the same during dynamic operation. The controller responds to VID-on-the-fly changes by slewing to the new voltage at the slew rate programmed. See Table 4 for more information. During negative VID transitions, the output voltage decays to the lower VID value at the slew rate determined by the load. The R3 modulator intrinsically has its voltage feed-forward. The output voltage is insensitive to a fast slew-rate input voltage change. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 23 of 49 ISL62776 4. 4. Resistor Configuration Options Resistor Configuration Options The PROG1 and PROG2 pins configure functionality within the IC. Resistors from these pins to GND are read during the first portion of the soft-start sequence. This section describes how to select the resistor values for each of these pins; use the values to program the output voltage offset of each output, VID-on-the-fly slew rate, and switching frequency used for both VRs. 4.1 VR Offset Programming Program a positive or negative offset for the Core VR using a resistor to ground from the PROG1 pin. Program a positive or negative offset for the SOC VR using a resistor to ground from the PROG2 pin. Table 2 and Table 3 provide the resistor values to select the desired output voltage offset. The 1% tolerance resistor value in the table must be used to program the corresponding Core or SOC output voltage offset. Table 2. PROG1 fSW and Core Output Voltage Offset Selection PROG1 1% Resistor Value (kΩ) Switching Frequency (kHz) Core Offset (mV) 5.62 450 -25 7.87 0 11.5 25 16.9 50 19.1 -25 24.9 0 34.0 25 41.2 50 52.3 750 -25 73.2 0 95.3 25 121 50 154 4.2 600 1000 -25 182 0 210 25 OPEN 50 VID-on-the-Fly Slew Rate Selection The PROG2 resistor also selects the slew rate for VID changes commanded by the processor. See Table 3. When selected, the slew rate is locked in during soft-start and is not adjustable during operation. The lowest slew rate that can be selected is 10mV/µs, which is above the minimum of 7.5mV/µs required by the SVI 2.0 specification. The slew rate selected sets the slew rate for both Core and the SOC VRs; they cannot be independently selected. 4.3 CCM Switching Frequency The programming resistor on the PROG1 pin sets the Core and SOC VR switching frequency. When the ISL62776 is in CCM, the switching frequency is not absolutely constant due to the nature of the R3 modulator. As explained in Multiphase R3 Modulator, the effective switching frequency increases during load insertion and decreases during load release to achieve fast response. Thus, the switching frequency is relatively constant at steady state. Variation is expected when the power stage condition, such as input voltage, output voltage, or load changes. The variation is usually less than 10% and does not have any significant effect on output voltage ripple magnitude. Table 3 defines the switching frequency based on the resistor value that programs the FCCM pin. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 24 of 49 ISL62776 Table 3. 4. Resistor Configuration Options PROG2 VOTF Slew Rate and SOC Output Voltage Offset Selection PROG2 1% Resistor Value (kΩ) VOTF Slew Rate (mV/µs) SOC Offset (mV) 5.62 10 -25 7.87 0 11.5 25 16.9 50 19.1 12.5 -25 24.9 0 34.0 25 41.2 50 52.3 15 -25 73.2 0 95.3 25 121 50 154 20 -25 182 0 210 25 OPEN 50 The controller monitors SVI commands to determine when to enter power-saving mode, implement dynamic VID changes, and shut down individual outputs. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 25 of 49 ISL62776 5. 5. AMD Serial VID Interface 2.0 AMD Serial VID Interface 2.0 The on-board SVI2 interface circuitry allows the AMD processor to directly control the Core and SOC voltage reference levels within the ISL62776. When the PWROK signal goes high, the IC begins monitoring the SVC and SVD pins for instructions. The ISL62776 uses a Digital-to-Analog Converter (DAC) to generate a reference voltage based on the decoded SVI value. See Figure 11 for a simple SVI interface timing diagram. 5.1 Pre-PWROK Metal VID Typical motherboard start-up begins with the controller decoding the SVC and SVD inputs to determine the pre-PWROK Metal VID setting (see Table 4). When the ENABLE input exceeds the rising threshold, the ISL62776 decodes and locks the decoded value into an onboard hold register. Table 4. Pre-PWROK Metal VID Codes SVC SVD Output Voltage (V) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 When the programming pins are read, the internal DAC circuitry begins to ramp the Core and SOC VRs to the decoded pre-PWROK Metal VID output level. The digital soft-start circuitry ramps the internal reference to the target gradually at a fixed rate of approximately 5mV/µs until the output voltage reaches ~250mV, and then at the programmed slew rate. The controlled ramp of all output voltage planes reduces inrush current during the soft-start interval. At the end of the soft-start interval, the PGOOD and PGOOD_SOC outputs transition high to indicate that both output planes are within regulation limits. If the ENABLE input falls below the enable falling threshold, the ISL62776 tri-states both outputs. PGOOD and PGOOD_SOC are pulled low with the loss of ENABLE. The Core and SOC VR output voltages decay based on output capacitance and load leakage resistance. If bias to VDD falls below the POR level, the ISL62776 responds in the manner previously described. When VDD and ENABLE rise above their respective rising thresholds, the internal DAC circuitry reacquires a pre-PWROK metal VID code and the controller soft-starts. 5.2 SVI Interface Active When the Core and SOC VRs successfully soft-start and the PGOOD and PGOOD_SOC signals transition high, PWROK can be asserted externally to the ISL62776. When PWROK is asserted to the IC, SVI instructions can begin as the controller actively monitors the SVI interface. Details about the SVI Bus protocol are provided in the “AMD Serial VID Interface 2.0 (SVI 2.0) Specification”. See AMD publication #48022. When a VID change command is received, the ISL62776 decodes the information to determine which VR is affected. The VID target is determined by the byte combinations in Table 5. The internal DAC circuitry steps the output voltage of the VR commanded to the new VID level. During this time, one or more of the VR outputs can be targeted. If either VR is commanded to power off by serial VID commands, the PGOOD signal remains asserted. If the PWROK input is deasserted, the controller steps both the Core and the SOC VRs back to the stored pre-PWROK metal VID level in the holding register from initial soft-start. No attempt is made to read the SVC and SVD inputs during this time. If PWROK is reasserted, the ISL62776 SVI interface waits for instructions. If ENABLE goes low during normal operation, all external MOSFETs are tri-stated and both PGOOD and PGOOD_SOC are pulled low. This event clears the pre-PWROK metal VID code, forces the controller to check SVC and SVD upon restart, and stores the pre-PWROK metal VID code found on restart. A POR event on either VCC or VIN during normal operation shuts down both regulators and pulls both PGOOD outputs low. The pre-PWROK metal VID code is not retained. Loss of VIN during operation typically causes the controller to enter a fault condition on one or both outputs. The controller shuts down both Core and SOC VRs and latches off. The pre-PWROK metal VID code is not retained during the process of cycling ENABLE to reset the fault latch and restart the controller. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 26 of 49 ISL62776 5.3 5. AMD Serial VID Interface 2.0 VID-on-the-Fly Transition When PWROK is high, the ISL62776 detects this flag and begins monitoring the SVC and SVD pins for SVI instructions. The microprocessor follows the protocol outlined in the following sections to send instructions for VID-on-the-fly transitions. The ISL62776 decodes the instruction and acknowledges the new VID code. For VID codes higher than the current VID level, the ISL62776 begins stepping the commanded VR outputs to the new VID target at the programmed slew rate; see Table 3. When the DAC ramps to the new VID code, a VID-on-the-fly Complete (VOTFC) request is sent on the SVI lines. When the VID codes are lower than the current VID level, the ISL62776 checks the state of the power state bits in the SVI command. If the power state bits are not active, the controller begins stepping the regulator output to the new VID target. If the power state bits are active, the controller allows the output voltage to decay and slowly steps the DAC down with the natural decay of the output. This decay allows the controller to quickly recover and move to a high VID code if commanded. The controller issues a VOTFC code on the SVI lines when the SVI command is decoded and before reaching the final output voltage. VOTFC requests do not take priority over telemetry per the AMD SVI 2.0 specification. 5.4 SVI Data Communication Protocol The SVI WIRE protocol is based on the I2C bus concept. The Serial Clock (SVC) and Serial Data (SVD) wires carry information between the AMD processor (master) and VR controller (slave) on the bus. The master initiates and terminates SVI transactions and drives the clock (SVC) during a transaction. The AMD processor is always the master and the voltage regulators are the slaves. The slave receives the SVI transactions and acts accordingly. Mobile SVI WIRE protocol timing is based on high-speed mode I2C. See AMD publication #48022 for more information. . Table 5. Serial VID Codes SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) 0000_0000 1.55000 0010_0000 1.35000 0100_0000 1.15000 0110_0000 0.95000 0000_0001 1.54375 0010_0001 1.34375 0100_0001 1.14375 0110_0001 0.94375 0000_0010 1.53750 0010_0010 1.33750 0100_0010 1.13750 0110_0010 0.93750 0000_0011 1.53125 0010_0011 1.33125 0100_0011 1.13125 0110_0011 0.93125 0000_0100 1.52500 0010_0100 1.32500 0100_0100 1.12500 0110_0100 0.92500 0000_0101 1.51875 0010_0101 1.31875 0100_0101 1.11875 0110_0101 0.91875 0000_0110 1.51250 0010_0110 1.31250 0100_0110 1.11250 0110_0110 0.91250 0000_0111 1.50625 0010_0111 1.30625 0100_0111 1.10625 0110_0111 0.90625 0000_1000 1.50000 0010_1000 1.30000 0100_1000 1.10000 0110_1000 0.90000 0000_1001 1.49375 0010_1001 1.29375 0100_1001 1.09375 0110_1001 0.89375 0000_1010 1.48750 0010_1010 1.28750 0100_1010 1.08750 0110_1010 0.88750 0000_1011 1.48125 0010_1011 1.28125 0100_1011 1.08125 0110_1011 0.88125 0000_1100 1.47500 0010_1100 1.27500 0100_1100 1.07500 0110_1100 0.87500 0000_1101 1.46875 0010_1101 1.26875 0100_1101 1.06875 0110_1101 0.86875 0000_1110 1.46250 0010_1110 1.26250 0100_1110 1.06250 0110_1110 0.86250 0000_1111 1.45625 0010_1111 1.25625 0100_1111 1.05625 0110_1111 0.85625 0001_0000 1.45000 0011_0000 1.25000 0101_0000 1.05000 0111_0000 0.85000 0001_0001 1.44375 0011_0001 1.24375 0101_0001 1.04375 0111_0001 0.84375 0001_0010 1.43750 0011_0010 1.23750 0101_0010 1.03750 0111_0010 0.83750 0001_0011 1.43125 0011_0011 1.23125 0101_0011 1.03125 0111_0011 0.83125 0001_0100 1.42500 0011_0100 1.22500 0101_0100 1.02500 0111_0100 0.82500 0001_0101 1.41875 0011_0101 1.21875 0101_0101 1.01875 0111_0101 0.81875 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 27 of 49 ISL62776 Table 5. 5. AMD Serial VID Interface 2.0 Serial VID Codes (Continued) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) 0001_0110 1.41250 0011_0110 1.21250 0101_0110 1.01250 0111_0110 0.81250 0001_0111 1.40625 0011_0111 1.20625 0101_0111 1.00625 0111_0111 0.80625 0001_1000 1.40000 0011_1000 1.20000 0101_1000 1.00000 0111_1000 0.80000 0001_1001 1.39375 0011_1001 1.19375 0101_1001 0.99375 0111_1001 0.79375 0001_1010 1.38750 0011_1010 1.18750 0101_1010 0.98750 0111_1010 0.78750 0001_1011 1.38125 0011_1011 1.18125 0101_1011 0.98125 0111_1011 0.78125 0001_1100 1.37500 0011_1100 1.17500 0101_1100 0.97500 0111_1100 0.77500 0001_1101 1.36875 0011_1101 1.16875 0101_1101 0.96875 0111_1101 0.76875 0001_1110 1.36250 0011_1110 1.16250 0101_1110 0.96250 0111_1110 0.76250 0001_1111 1.35625 0011_1111 1.15625 0101_1111 0.95625 0111_1111 0.75625 1000_0000 0.75000 1010_0000 0.55000 (Note 7) 1100_0000 0.35000 (Note 7) 1110_0000 0.15000 (Note 7) 1000_0001 0.74375 1010_0001 0.54375 (Note 7) 1100_0001 0.34375 (Note 7) 1110_0001 0.14375 (Note 7) 1000_0010 0.73750 1010_0010 0.53750 (Note 7) 1100_0010 0.33750 (Note 7) 1110_0010 0.13750 (Note 7) 1000_0011 0.73125 1010_0011 0.53125 (Note 7) 1100_0011 0.33125 (Note 7) 1110_0011 0.13125 (Note 7) 1000_0100 0.72500 1010_0100 0.52500 (Note 7) 1100_0100 0.32500 (Note 7) 1110_0100 0.12500 (Note 7) 1000_0101 0.71875 1010_0101 0.51875 (Note 7) 1100_0101 0.31875 (Note 7) 1110_0101 0.11875 (Note 7) 1000_0110 0.71250 1010_0110 0.51250 (Note 7) 1100_0110 0.31250 (Note 7) 1110_0110 0.11250 (Note 7) 1000_0111 0.70625 1010_0111 0.50625 (Note 7) 1100_0111 0.30625 (Note 7) 1110_0111 0.10625 (Note 7) 1000_1000 0.70000 1010_1000 0.50000 (Note 7) 1100_1000 0.30000 (Note 7) 1110_1000 0.10000 (Note 7) 1000_1001 0.69375 1010_1001 0.49375 (Note 7) 1100_1001 0.29375 (Note 7) 1110_1001 0.09375 (Note 7) 1000_1010 0.68750 1010_1010 0.48750 (Note 7) 1100_1010 0.28750 (Note 7) 1110_1010 0.08750 (Note 7) 1000_1011 0.68125 1010_1011 0.48125 (Note 7) 1100_1011 0.28125 (Note 7) 1110_1011 0.08125 (Note 7) 1000_1100 0.67500 1010_1100 0.47500 (Note 7) 1100_1100 0.27500 (Note 7) 1110_1100 0.07500 (Note 7) 1000_1101 0.66875 1010_1101 0.46875 (Note 7) 1100_1101 0.26875 (Note 7) 1110_1101 0.06875 (Note 7) 1000_1110 0.66250 1010_1110 0.46250 (Note 7) 1100_1110 0.26250 (Note 7) 1110_1110 0.06250 (Note 7) 1000_1111 0.65625 1010_1111 0.45625 (Note 7) 1100_1111 0.25625 (Note 7) 1110_1111 0.05625 (Note 7) 1001_0000 0.65000 1011_0000 0.45000 (Note 7) 1101_0000 0.25000 (Note 7) 1111_0000 0.05000 (Note 7) 1001_0001 0.64375 1011_0001 0.44375 (Note 7) 1101_0001 0.24375 (Note 7) 1111_0001 0.04375 (Note 7) 1001_0010 0.63750 1011_0010 0.43750 (Note 7) 1101_0010 0.23750 (Note 7) 1111_0010 0.03750 (Note 7) R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 28 of 49 ISL62776 Table 5. 5. AMD Serial VID Interface 2.0 Serial VID Codes (Continued) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) SVID[7:0] Voltage (V) 1001_0011 0.63125 1011_0011 0.43125 (Note 7) 1101_0011 0.23125 (Note 7) 1111_0011 0.03125 (Note 7) 1001_0100 0.62500 1011_0100 0.42500 (Note 7) 1101_0100 0.22500 (Note 7) 1111_0100 0.02500 (Note 7) 1001_0101 0.61875 1011_0101 0.41875 (Note 7) 1101_0101 0.21875 (Note 7) 1111_0101 0.01875 (Note 7) 1001_0110 0.61250 1011_0110 0.41250 (Note 7) 1101_0110 0.21250 (Note 7) 1111_0110 0.01250 (Note 7) 1001_0111 0.60625 1011_0111 0.40625 (Note 7) 1101_0111 (Note 7) 0.20625 (Note 7) 1111_0111 0.00625 (Note 7) 1001_1000 0.60000 (Note 7) 1011_1000 0.40000 (Note 7) 1101_1000 0.20000 (Note 7) 1111_1000 OFF (Note 7) 1001_1001 0.59375 (Note 7) 1011_1001 0.39375 (Note 7) 1101_1001 0.19375 (Note 7) 1111_1001 OFF (Note 7) 1001_1010 0.58750 (Note 7) 1011_1010 0.38750 (Note 7) 1101_1010 0.18750 (Note 7) 1111_1010 OFF (Note 7) 1001_1011 0.58125 (Note 7) 1011_1011 0.38125 (Note 7) 1101_1011 0.18125 (Note 7) 1111_1011 OFF (Note 7) 1001_1100 0.57500 (Note 7) 1011_1100 0.37500 (Note 7) 1101_1100 0.17500 (Note 7) 1111_1100 OFF (Note 7) 1001_1101 0.56875 (Note 7) 1011_1101 0.36875 (Note 7) 1101_1101 0.16875 (Note 7) 1111_1101 OFF (Note 7) 1001_1110 0.56250 (Note 7) 1011_1110 0.36250 (Note 7) 1101_1110 0.16250 (Note 7) 1111_1110 OFF (Note 7) 1001_1111 0.55625 (Note 7) 1011_1111 0.35625 (Note 7) 1101_1111 0.15625 (Note 7) 1111_1111 OFF (Note 7) Note: 7. VID not required for AMD Family 10h processors. AMD processor requirements are loosened at these levels. 5.5 SVI Bus Protocol SVC 1 2 3 4 5 6 7 8 9 10 VID BIT [0] PSI1_L PSI0_L The AMD processor bus protocol is compliant with the SMBus send byte protocol for VID transactions. Figure 17 shows the AMD SVD packet structure. VID Bits [7:1] 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 START SVD ACK ACK ACK Figure 17. SVD Packet Structure Table 6 contains the descriptions of each bit of the three bytes that make up the SVI command. During a transaction, the processor sends the start sequence followed by each of the three bytes, which end with an optional Acknowledge (ACK) bit. The ISL62776 does not drive the SVD line during the ACK bit. Finally, the processor sends the stop sequence. After the ISL62776 detects the stop, it can proceed with the commanded action from the transaction. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 29 of 49 ISL62776 Table 6. 5. AMD Serial VID Interface 2.0 SVD Data Packet Bits Description 1:5 Always 11000b 6 Core domain selector bit. If set, the following data byte contains the VID, power state, telemetry control, load line trim, and offset trim to apply to the Core VR. 7 SOC domain selector bit. If set, the following data byte contains the VID, power state, telemetry control, load line trim, and offset trim to apply to the SOC VR. 8 Always 0b 9 ACK bit 10 PSI0_L 11:17 VID code bits [7:1] 18 ACK bit 19 VID code bit [0] 20 PSI1_L 21 TFN (Telemetry Functionality) 22:24 Load line slope trim 25:26 Offset trim [1:0] 27 5.6 ACK bit Power States SVI 2.0 defines two power state indicator levels, PSI0_L and PSI1L. See Table 7 for information about these power state indicators. As processor current consumption is reduced, the power state indicator level changes to improve VR efficiency under low power conditions. Table 7. PSI0_L and PSI1_L Definition Function Bit Description PSI0_L 10 Power State Indicate Level 0. When this signal is asserted (active Low), the processor is in a low enough power state for the ISL62776 to boost efficiency by dropping phases and entering 1-Phase CCM. PSI1_L 20 Power State Indicate Level 1. When this signal is asserted (active Low), the processor is in a low enough power state for the ISL62776 to boost efficiency by dropping phases and entering 1-Phase DEM. When the Core VR is operating in 3-phase mode and PSI0_L is asserted, Channels 2 and 3 are tri-stated and Channel 1 remains active in CCM mode. When PSI1_L is asserted, Channel 1 enters into enters Diode Emulation Mode (DEM) to boost efficiency. When PSI0_L is asserted for the SOC VR, the SOC regulator remains in Continuous Conduction Mode (CCM). When PSI1_L is asserted, the SOC VR transitions to DEM to boost efficiency. The processor can assert or deassert PSI0_L and PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L is deasserted while PSI1_L is still asserted, the ISL62776 returns the selected VR back to full channel CCM operation. 5.7 Dynamic Load Line Slope Trim The ISL62776 supports the SVI 2.0 ability for the processor to manipulate the load line slope of the Core and SOC VRs independently using the serial VID interface. The slope manipulation applies to the initial load line slope. A load line slope trim typically coincides with a VOTF change. See Table 8 for more information about the load line slope trim feature. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 30 of 49 ISL62776 Table 8. 5. AMD Serial VID Interface 2.0 Load Line Slope Trim Definition Load Line Slope Trim [2:0] 5.8 Description 000 Disable LL 001 -40% mΩ change 010 -20% mΩ change 011 No change 100 +20% mΩ change 101 +40% mΩ change 110 +60% mΩ change 111 +80% mΩ change Dynamic Offset Trim The ISL62776 supports the SVI 2.0 ability for the processor to manipulate the output voltage offset of the Core and SOC VRs. See Table 9 for offset values. This offset is in addition to any output voltage offset set from the COMP resistor reader. The dynamic offset trim can disable the COMP resistor programmed offset of either output when Disable All Offset is selected. Table 9. Offset Trim Definition Offset Trim [1:0] Description 00 Disable All Offset 01 -25mV change 10 0mV change 11 +25mV change R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 31 of 49 ISL62776 6. 6. Telemetry Telemetry The ISL62776 can provide voltage and current information to the AMD processor through the telemetry system outlined by the AMD SVI 2.0 specification. The telemetry data is transmitted through the SVC and SVT lines of the SVI 2.0 interface. Current telemetry is based on a voltage generated across the recommended 133kΩ resistor placed from the IMON pin to GND. The current flowing out of the IMON pin is proportional to the load current in the VR. The Isum current defined in Voltage Regulation and Load Line Implementation provides the base conversion from the load current to the Isum current created by the internal amplifier. The Isum current is then divided down by a factor of 4 to create the IMON current, which flows out of the IMON pin. The Isum current measures 36µA when the load current is at full load based on a droop current designed for 45µA at the same load current. The difference between the Isum current and the droop current is provided in Equation 2. The IMON current measures 11.25µA at full load current for the VR and the IMON voltage is 1.2V. The load percentage reported by the IC is based on the this voltage. When the load is 25% of the full load, the voltage on the IMON pin is 25% of 1.2V or 0.3V. The SVI interface allows the selection of no telemetry, voltage only, or voltage and current telemetry on either or both of the VR outputs. The processor uses the TFN bit and the Core and SOC domain selector bits to change the telemetry functionality. See Table 10 for more information. Table 10. TFN Truth Table TFN, Core, SOC Bits [21, 6, 7] Description 1, 0, 1 Telemetry is in voltage and current mode, so the voltage and current are sent for the VDD and VDDSOC domains by the controller. 1, 0, 0 Telemetry is in voltage mode only. The controller sends only the voltage of VDD and VDDSOC domains. 1, 1, 0 Telemetry is disabled. 1, 1, 1 Reserved R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 32 of 49 ISL62776 7. 7. Protection Features Protection Features The Core VR and SOC VR both provide overcurrent, current-balance, undervoltage, and overvoltage fault protections. The controller provides over-temperature protection. 7.1 Overcurrent You can use the IMON voltage to determine the load current at any moment in time. The Overcurrent Protection (OCP) circuitry monitors the IMON voltage to determine when a fault occurs. Based on the description in Voltage Regulation and Load Line Implementation, the current that flows out of the IMON pin is proportional to the Isum current. The Isum current is created from the sensed voltage across Cn, which is a measure of the load current based upon the sensing element selected. The IMON current is generated internally and is 1/4 of the Isum current. The EDC or IDDspike current value for the AMD CPU load sets the maximum current level for droop and the IMON voltage of 1.2V, which indicates 100% loading for telemetry. The Isum current level at maximum load, or IDDspike, is 36µA, which translates to an IMON current level of 9µA. The IMON resistor is 133kΩ and the 9µA flowing through the IMON resistor results in a 1.2V level at maximum loading of the VR. The overcurrent threshold is 1.5V on the IMON pin. Based on a 1.2V IMON voltage equating to 100% loading, the additional 0.3V provided above this level equates to a 25% increase in load current before an OCP fault is detected. The EDC or IDDspike current is sets the 1.2V on IMON for full load current, so the OCP level is 1.25 times the EDC or IDDspike current level. This additional margin above the EDC or IDDspike current allows the AMD CPU to enter and exit the IDDspike performance mode without issue unless the load current is out of line with the IDDspike expectation, thus the need for overcurrent protection. When the voltage on the IMON pin meets the overcurrent threshold of 1.5V, an OCP event occurs. Within 2µs of detecting an OCP event, the controller asserts VR_HOT_L low to communicate to the AMD CPU to throttle back. A fault timer begins counting while IMON is at or above the 1.5V threshold. The fault timer lasts 7.5µs to 11µs, then flags an OCP fault. The controller then tri-states the active channels and goes into shutdown. PGOOD goes low and a fault flag from this VR is sent to the other VR, which is shut down within 10µs. If the IMON voltage drops below the 1.5V threshold before the fault timer count finishes, the fault timer is cleared and VR_HOT_L is taken high. The ISL62776 also features a Way-Overcurrent (WOC) feature that immediately takes the controller into shutdown. This protection is also referred to as fast overcurrent protection for short-circuit protection. If the IMON current reaches 15µA, WOC is triggered, active channels are tri-stated, the controller is placed in shutdown, and PGOOD is pulled low. There is no fault timer on the WOC fault; the controller takes immediate action. The other controller output is also shut down within 10µs. 7.2 Current Balance The controller monitors the ISENx pin voltages to determine current balance protection. If the ISENx pin voltage difference is greater than 9mV for 1ms, the controller declares a fault and latches off. 7.3 Undervoltage If the VSEN pin voltage falls below the output voltage VID value plus any programmed offsets by -325mV, the controller declares an undervoltage fault. The controller deasserts PGOOD and tri-states the power MOSFETs. 7.4 Overvoltage If the VSEN pin voltage exceeds the output voltage VID value plus any programmed offsets by +325mV, the controller declares an overvoltage fault. The controller deasserts PGOOD and turns on the low-side power MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below the VID set value. When the output voltage is below this level, the lower gate is tri-stated. If the output voltage rises above the overvoltage threshold again, the protection process is repeated. This behavior provides the maximum amount of protection against shorted high-side power MOSFETs while preventing output ringing below ground. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 33 of 49 ISL62776 7.5 7. Protection Features Thermal Monitor (NTC, NTC_SOC) The ISL62776 has two thermal monitors that use an external resistor network, which includes an NTC thermistor, to monitor motherboard temperature and alert the AMD CPU of a thermal issue. Figure 18 shows the basic thermal monitor circuit on the Core VR NTC pin. The SOC VR features the same thermal monitor. The controller drives a 30µA current out of the NTC pin and monitors the voltage at the pin. The current flowing out of the NTC pin creates a voltage that is compared to a warning threshold of 660mV. When the voltage at the NTC pin falls to this warning threshold or below, the controller asserts VR_HOT_L to alert the AMD CPU to throttle back load current to stabilize the motherboard temperature. A thermal fault counter begins counting toward a minimum shutdown time of 100µs. The thermal fault counter is an up/down counter, so if the voltage at the NTC pin rises above the warning threshold, it counts down and extends the time for a thermal fault to occur. The warning threshold has 20mV of hysteresis. If the voltage at the NTC pin continues to fall down to the shutdown threshold of 600mV or below, the controller goes into shutdown and triggers a thermal fault. The PGOOD pin is pulled low and tri-states the power MOSFETs. A fault on either side shuts down both VRs. Internal to ISL62776 +V VR_HOT_L 30µA R NTC Monitor Rp VNTC + - RNTC Warning 660mV Rs Shutdown 600mV Figure 18. Circuitry Associated With the Thermal Monitor Feature of the ISL62776 As the board temperature rises, the NTC thermistor resistance decreases and the voltage at the NTC pin drops. When the voltage on the NTC pin drops below the over-temperature trip threshold, VR_HOT is pulled low. The VR_HOT signal changes the CPU operation and decreases power consumption. When the CPU power consumption decreases, the board temperature decreases and the NTC thermistor voltage rises. When the over-temperature threshold is tripped and VR_HOT goes low, the over-temperature threshold changes to the reset level. The addition of hysteresis to the over-temperature threshold prevents nuisance trips. When both pin voltages exceed the over-temperature reset threshold, the pull-down on VR_HOT is released. The signal changes state, the CPU resumes normal operation, and the over-temperature threshold returns to the trip level. Table 11 summarizes the fault protections. Table 11. Fault Protection Summary Fault Type Fault Duration Before Protection Overcurrent 7.5µs to 11.5µs Phase Current Unbalance 1ms Way-Overcurrent (1.5xOC) Immediately Protection Action PWM tri-state, PGOOD latched low Undervoltage -325mV PWM tri-state, PGOOD latched low Overvoltage +325mV PGOOD latched low. Actively pulls the output voltage to below VID value, then tri-states. NTC Thermal R16DS0044EU0200 Rev.2.00 Oct.8.20 100µs minimum Fault Reset ENABLE toggle or VDD toggle PWM tri-state, PGOOD latched low Page 34 of 49 ISL62776 7.6 7. Protection Features Fault Recovery All of the fault conditions can be reset by bringing ENABLE low or by bringing VDD below the POR threshold. When ENABLE and VDD return to their high operating levels, the controller resets the faults and soft-start occurs. 7.7 Interface Pin Protection When removing power to VDD and VDDIO but leaving power applied to the SVC and SVD pins, the SVC and SVD protection diodes must be considered. Figure 19 shows the basic protection on the pins. If SVC and/or SVD are powered but VDD is not, leakage current flows from these pins to VDD. Internal to ISL62776 VDD SVC, SVD GND Figure 19. Protection Diodes on the SVC and SVD Pins R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 35 of 49 ISL62776 8. 8.1 8. Selecting Key Components Selecting Key Components Inductor DCR Current-Sensing Network Figure 20 shows the inductor DCR current-sensing network for a 3-phase solution. An inductor current flows through the DCR and creates a voltage drop. Each inductor has two resistors in Rsum and Ro connected to the pads to accurately sense the inductor current by sensing the DCR voltage drop. The Rsum and Ro resistors are connected in a summing network as shown and feed the total current information to the NTC network (consisting of Rntcs, Rntc, and Rp) and capacitor Cn. Rntc is a negative temperature coefficient (NTC) thermistor that temperature-compensates the inductor DCR change. PHASE1 PHASE2 PHASE3 RSUM RSUM ISUM+ RSUM L L L RNTCS + RP DCR DCR DCR RNTC RO CNVCN - RI ISUM- RO RO IO Figure 20. DCR Current-Sensing Network The inductor output side pads are electrically shorted in the schematic but have some parasitic impedance in actual board layout, so they cannot be shorted together for the current-sensing summing network. Renesas recommends using 1Ω~10Ω Ro to create quality signals. Because the Ro value is much smaller than the rest of the current sensing circuit, the following analysis ignores it. The summed inductor current information is presented to the capacitor Cn. Equations 18 through Equation 22 describe the frequency domain relationship between the inductor total current Io(s) and Cn voltage VCn(s): (EQ. 18)   R ntcnet   DCR V Cn  s  =  ----------------------------------------  -------------  I o  s   A cs  s  N  R sum   R ntcnet + ------------ N (EQ. 19)  R ntcs + R ntc   R p R ntcnet = -------------------------------------------------R ntcs + R ntc + R p (EQ. 20) (EQ. 21) s 1 + ------L A cs  s  = --------------------s 1 + ----------- sns DCR  L = ------------L R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 36 of 49 ISL62776 (EQ. 22) 8. Selecting Key Components 1  sns = -----------------------------------------------------R sum R ntcnet  -------------N ----------------------------------------  C n R sum R ntcnet + -------------N where N is the number of phases. Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, causing a higher reading of the inductor DC current. The NTC Rntc value decrease as its temperature decreases. Proper selection of Rsum, Rntcs, Rp, and Rntc parameters ensures that VCn represents the inductor total DC current over the temperature range of interest. Many sets of parameters can properly temperature-compensate the DCR change. Because the NTC network and the Rsum resistors form a voltage divider, Vcn is always a fraction of the inductor DCR voltage. Renesas recommends using a higher ratio of Vcn to the inductor DCR voltage so the droop circuit has a higher signal level to work with. A typical set of parameters that provide good temperature compensation are: Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters may need to be fine tuned on actual boards. Apply full load DC current and record the output voltage reading immediately, then record the output voltage reading again when the board reaches the thermal steady state. A good NTC network can limit the output voltage drift to within 2mV. Renesas recommends following the evaluation board layout and current sensing network parameters to minimize engineering time. VCn(s) needs to represent real-time Io(s) for the controller to achieve good transient response. Transfer function Acs(s) has a pole wsns and a zero wL. Match wL and wsns so Acs(s) is unity gain at all frequencies. By forcing wL equal to wsns and solving for the solution, Equation 23 gives Cn. (EQ. 23) L C n = -----------------------------------------------------------R sum R ntcnet  -------------N ----------------------------------------  DCR R sum R ntcnet + -------------N For example, given N = 3, Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ, and L = 0.36µH, Equation 23 gives Cn = 0.406µF. Assuming the compensator design is correct, Figure 21 shows the expected load transient response waveforms if Cn is correctly selected. When the load current Icore has a square change, the output voltage Vcore also has a square response. io Vo Figure 21. Desired Load Transient Response Waveforms If Cn is too large or too small, VCn(s) does not accurately represent real-time Io(s) and worsens the transient response. Figure 22 shows the load transient response when Cn is too small. Vcore sags excessively upon load insertion and can create a system failure. Figure 23 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There is excessive overshoot if load insertion occurs during this time, which can negatively affect the CPU reliability. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 37 of 49 ISL62776 8. Selecting Key Components io Vo Figure 22. Load Transient Response When Cn is Too Small io Vo Figure 23. Load Transient Response When Cn is Too Large Figure 24 shows the output voltage ringback problem during load transient response. The load current io has a fast step change but the inductor current iL cannot accurately follow. Instead, iL responds in first-order system fashion due to the nature of the current loop. The ESR and ESL effect of the output capacitors makes the output voltage Vo dip quickly upon load current change. However, the controller regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore, it pulls Vo back to the level dictated by iL, causing ringback. Ringback does not occur if the output capacitor has very low ESR and ESL, as is the case with all ceramic capacitors. io iL Vo Ringback Figure 24. Output Voltage Ringback Problem Figure 25 shows two optional circuits for ringback reduction. Cn is the capacitor used to match the inductor time constant. Usually, two or more parallel capacitors are required to get the desired value. Figure 25 shows that two capacitors (Cn.1 and Cn.2) are in parallel. Resistor Rn is an optional component to reduce the Vo ringback. At steady state, Cn.1 + Cn.2 provides the desired Cn capacitance. At the beginning of the io change, the effective capacitance is less because Rn increases the impedance of the Cn.1 branch. As Figure 22 shows, Vo tends to dip when Cn is too small. This effect reduces the Vo ringback. This effect is more pronounced when Cn.1 is much larger than Cn.2 and when Rn is large. However, the presence of Rn increases the ripple of the Vn signal if Cn.2 is too small. Renesas recommends keeping Cn.2 greater than 2200pF. The Rn value is usually a few Ω. Determine the Cn.1, Cn.2, and Rn values by tuning the load transient response waveforms on an actual board. Rip and Cip form an R-C branch in parallel with Ri, providing a lower impedance path than Ri at the beginning of the io change. Rip and Cip do not have any effect at steady state. By properly selecting the Rip and Cip values, idroop can resemble io rather than iL and Vo does not ring back. The recommended value for Rip is 100Ω. Determine Cip by tuning the load transient response waveforms on an actual board. The recommended range for Cip is 100pF~2000pF. However, the Rip - Cip branch may distort the idroop waveform. Instead of being triangular like the real inductor current, idroop may have sharp spikes, which can adversely affect idroop average value detection and therefore can affect OCP accuracy. User discretion is advised. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 38 of 49 ISL62776 8. Selecting Key Components ISUM+ R ntcs Cn.1 V cn C n.2 Rp Rn Rntc Optional ISUM- Ri Cip R ip Optional Figure 25. Optional Circuits for Ringback Reduction 8.2 Resistor Current-Sensing Network Figure 26 shows the resistor current-sensing network for a 3-phase solution. PHASE1 PHASE2 PHASE3 L L L DCR DCR DCR RSUM RSUM ISUM+ RSUM RSEN RSEN + VCN RSEN RO - CN RI ISUM- RO RO IO Figure 26. Resistor Current-Sensing Network Each inductor has a series current sensing resistor, Rsen. Rsum and Ro are connected to the Rsen pads to accurately capture the inductor current information. The Rsum and Ro resistors are connected to capacitor Cn. Rsum and Cn form a filter for noise attenuation. Equation 24 through Equation 26 give the VCn(s) expression. (EQ. 24) (EQ. 25) (EQ. 26) R sen V Cn  s  = -------------  I o  s   A Rsen  s  N 1 A Rsen  s  = --------------------s 1 + ---------- sns 1  Rsen = --------------------------R sum --------------  C n N R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 39 of 49 ISL62776 8. Selecting Key Components Transfer function ARsen(s) always has unity gain at DC. The current-sensing resistor Rsen value does not have significant variation over-temperature, so the NTC network is not needed. The recommended values are Rsum = 1kΩ and Cn = 5600pF. 8.3 Overcurrent Protection Resistor Ri sets the Isum current which is proportional to droop current and IMON current. See Equation 2 and Figures 20, 24, and 26. Table 1 and Table 2 show the internal OCP threshold based on the IMON pin voltage. Because the Ri resistor impacts both the droop current and the IMON current, fine adjustments to Idroop requires changing the Rcomp resistor. For example, the OCP threshold is 1.5V on the IMON pin, which equates to an IMON current of 11.25µA using a 133kΩ IMON resistor. The corresponding Isum is 45µA, resulting in an Idroop of 56.25µA. At full load current, Iomax, the Isum current is 36µA and the resulting Idroop is 45µA. The ratio of Isum at OCP relative to full load current is 1.25. Therefore, the OCP current trip level is 25% higher than the full load current. For inductor DCR sensing, Equation 27 gives the DC relationship of Vcn(s) and Io(s): (EQ. 27)   R ntcnet  DCR V Cn =  ----------------------------------------  -------------  I o N  R sum   R ntcnet + ------------ N Substituting Equation 27 into Equation 2 gives Equation 28: (EQ. 28) R ntcnet DCR 5 1 I droop = ---  -----  ----------------------------------------  -------------  I o N 4 Ri R sum R ntcnet + -------------N Therefore: (EQ. 29) R ntcnet  DCR  I o 5 R i = ---  -----------------------------------------------------------------------------4 R sum - I N   R ntcnet + ------------ N  droop Substituting Equation 19 and applying the OCP condition in Equation 29 gives Equation 30: (EQ. 30)  R ntcs + R ntc   R p ------------------------------------------------- DCR  I omax R ntcs + R ntc + R p 5 R i = ---  -----------------------------------------------------------------------------------------------------------------------4  R ntcs + R ntc   R p R sum + --------------  I droopmax N   ------------------------------------------------- R N  ntcs + R ntc + R p where Iomax is the full load current and Idroopmax is the corresponding droop current. For example, given N = 3, Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ, Iomax = 65A, and Idroopmax = 45μA, Equation 30 gives Ri = 439Ω. For resistor sensing, Equation 31 gives the DC relationship of Vcn(s) and Io(s). (EQ. 31) R sen V Cn = -------------  I o N R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 40 of 49 ISL62776 8. Selecting Key Components Substituting Equation 31 into Equation 2 gives Equation 32: (EQ. 32) 5 1 R sen I droop = ---  -----  -------------  I o 4 Ri N Therefore: (EQ. 33) 5 R sen  I o R i = ---  -------------------------4 N  I droop Substituting Equation 33 and applying the OCP condition in Equation 29 gives Equation 34: (EQ. 34) 5 R sen  I omax R i = ---  -----------------------------------4 N  I droopmax where Iomax is the full load current and Idroopmax is the corresponding droop current. For example, given N = 3, Rsen = 1mΩ, Iomax = 65A, and Idroopmax = 45µA, Equation 34 gives Ri = 602Ω. 8.4 Load-Line Slope See Figure 13 for load-line implementation. For inductor DCR sensing, substituting Equation 28 into Equation 3 gives the load line slope expression: (EQ. 35) R ntcnet V droop DCR 5 R droop LL = ----------------- = ---  ------------------  ----------------------------------------  ------------N 4 Ri R sum Io R ntcnet + -------------N For resistor sensing, substituting Equation 32 into Equation 3 gives the load line slope expression. (EQ. 36) V droop 5 R sen  R droop LL = ----------------- = ---  ------------------------------------4 N  Ri Io Substituting Equation 29 and rewriting Equation 35, or substituting Equation 33 and rewriting Equation 36, gives the same result as in Equation 37: (EQ. 37) Io R droop = ---------------  LL I droop Use the full-load condition to calculate Rdroop. For example, given Iomax = 65A, Idroopmax = 45µA, and LL = 2.1mΩ, Equation 37 gives Rdroop = 3.03kΩ. Renesas recommends starting with the Rdroop value calculated by Equation 37 and fine-tuning it on the actual board to get accurate load line slope. Record the output voltage readings at no load and at full load for load-line slope calculation. Reading the output voltage at lighter load instead of full load increases the measurement error. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 41 of 49 ISL62776 8.5 8. Selecting Key Components Compensator Figure 21 shows the desired load transient response waveforms. Figure 27 shows the equivalent circuit of a voltage regulator (VR) with the droop function. A VR is equivalent to a voltage source (= VID) and output impedance Zout(s). If Zout(s) is equal to the load-line slope LL (that is, a constant output impedance), Vo has a square response when io has a square change in the entire frequency range. i Zout(s) = LL o VR VID V Load o Figure 27. Voltage Regulator Equivalent Circuit Renesas provides a Microsoft® Excel-®based spreadsheet to help design the compensator and the current sensing network so the VR achieves constant output impedance as a stable system. A VR with active droop function is a dual-loop system consisting of a voltage loop and a droop loop, which is a current loop. However, neither loop alone is sufficient to describe the entire system. The spreadsheet shows two loop gain transfer functions, T1(s) and T2(s), that describe the entire system. Figure 28 conceptually shows T1(s) measurement setup, and Figure 29 conceptually shows T2(s) measurement setup. The VR senses the inductor current, multiplies it by a gain of the load-line slope, adds it on top of the sensed output voltage, and feeds it to the compensator. T1 is measured after the summing node and T2 is measured in the voltage loop before the summing node. The spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) can actually be measured on an ISL62776 regulator. L VO Q1 VIN Gate Driver Q2 iO COUT Load Line Slope 20 - EA MOD. COMP + + VID + Isolation Transformer Channel B Loop Gain = Channel A Channel A Network Analyzer Channel B Excitation Output Figure 28. Loop Gain T1(s) Measurement Setup T1(s) is the total loop gain of the voltage loop and the droop loop. It always has a higher crossover frequency than T2(s), so it has a higher impact on system stability. T2(s) is the voltage loop gain with closed droop loop, so it has a higher impact on output voltage response. Design the compensator to get stable T1(s) and T2(s) with sufficient phase margin and an output impedance equal to or smaller than the load-line slope. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 42 of 49 ISL62776 8. Selecting Key Components L VO Q1 Q2 Gate Driver VIN IO CO Load Line Slope EA MOD. + COMP Loop Gain = + + - 20 VID Isolation Transformer Channel B Channel A Channel A Channel B Network Analyzer Excitation Output Figure 29. Loop Gain T2(s) Measurement Setup 8.6 Current Balancing See Figure 14 through Figure 20 for information about current balancing. The ISL62776 achieves current balancing by matching the ISEN pin voltages. Risen and Cisen form filters to remove the switching ripple of the phase node voltages. Renesas recommends using a long RisenCisen time constant so that the ISEN voltages have minimal ripple and represent the DC current flowing through the inductors. The recommended values are Rs = 10kΩ and Cs = 0.22µF. 8.7 Thermal Monitor Component Selection The ISL62776’s NTC and NTC_SOC pins monitor the motherboard temperature and alert the AMD CPU if a thermal issue arises. The basic function of this circuitry is described in Thermal Monitor (NTC, NTC_SOC). Figure 30 shows the basic configuration of the NTC resistor, RNTC, and offset resistor, RS, used to generate the warning and shutdown voltages at the NTC pin. Internal to ISL62776 +V VR_HOT_L 30µA R NTC Monitor 330kΩ 8.45kΩ RNTC Rs Warning 640mV Shutdown 580mV Figure 30. Thermal Monitor Feature of the ISL62776 As the board temperature rises, the NTC thermistor resistance decreases and the voltage at the NTC pin drops. When the voltage on the NTC pin drops below the thermal warning threshold of 0.640V, VR_HOT_L is pulled low. When the AMD CPU detects VR_HOT_L has gone low, it begins throttling back load current on both outputs to reduce the board temperature. If the board temperature continues to rise, the NTC thermistor resistance drops further and the voltage at the NTC pin could drop below the thermal shutdown threshold of 0.580V. When this threshold is reached, the ISL62776 R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 43 of 49 ISL62776 8. Selecting Key Components shuts down both the Core and SOC VRs, indicating a thermal fault occurred before the thermal fault counter triggered a fault. NTC thermistor selection can vary depending on the resistor network configuration. The equivalent resistance at the typical thermal warning threshold voltage of 0.64V is defined in Equation 38. (EQ. 38) 0.64V ---------------- = 21.3k 30A The equivalent resistance at the typical thermal shutdown threshold voltage of 0.58V required to shutdown both outputs is defined in Equation 39. (EQ. 39) 0.58V ---------------- = 19.3k 30A The NTC thermistor value correlates to the resistance change between the warning and shutdown thresholds and the required temperature change. If the warning level is designed to occur at a board temperature of +100°C and the thermal shutdown level at a board temperature of +105°C, the thermistor resistance change can be calculated. For example, a Panasonic NTC thermistor with B = 4700 has a resistance ratio of 0.03939 of its nominal value at +100°C and 0.03308 of its nominal value at +105°C. Dividing the required resistance change between the thermal warning threshold and the shutdown threshold by the change in resistance ratio of the NTC thermistor at the two temperatures of interest provides the required NTC resistance is defined (see Equation 40). (EQ. 40)  21.3k – 19.3k - = 317k ---------------------------------------------------- 0.03939 – 0.03308  The closest standard thermistor to the value calculated with B = 4700 is 330kΩ. The NTC thermistor part number is ERTJ0EV334J. The actual resistance change of this standard thermistor value between the warning threshold and the shutdown threshold is calculated in Equation 41. (EQ. 41)  330k  0.03939  –  330k  0.03308  = 2.082k Because the NTC thermistor resistance at +105°C is less than the required resistance from Equation 39, additional resistance in series with the thermistor is required to make up the difference. A standard resistor, 1% tolerance, added in series with the thermistor increases the voltage seen at the NTC pin. The additional resistance required is calculated in Equation 42. (EQ. 42) 19.3k – 10.916k = 8.384k The closest standard 1% tolerance resistor is 8.45kΩ. The NTC thermistor is placed in a hot spot on the board, typically near the upper MOSFET of Channel 1 of the respective output. The standard resistor is placed next to the controller. 8.8 Bootstrap Capacitor Selection The external drivers feature an internal bootstrap Schottky diode. Add an external capacitor across the BOOT and PHASE pins to complete the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above VDDP + 4V and its capacitance value can be chosen from Equation 43: (EQ. 43) Q GATE C BOOT_CAP  ----------------------------------V BOOT_CAP Q G1  PVCC Q GATE = -----------------------------------  N Q1 V GS1 where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 44 of 49 ISL62776 9. 9. Layout Guidelines Layout Guidelines 9.1 PCB Layout Considerations 9.1.1 Power and Signal Layers Placement on the PCB Generally, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board. The ground-plane layer should be adjacent to the signal layer to provide shielding. 9.1.2 Component Placement The two critical sets of components in a DC/DC converter are the power components and the small signal components. The power components are the most critical because they switch large amounts of energy. The small signal components connect to sensitive nodes or supply critical bypassing current and signal coupling. Place the power components first (see Figure 31). The power components include MOSFETs, input and output capacitors, and the inductor. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each power train. Symmetrical layout allows heat to be dissipated equally across all power trains. Keeping a minimum distance between the power train and the control IC helps keep the gate drive traces short. The drive signals include LGATE, UGATE, PGND, PHASE, and BOOT. Vias to Ground Plane GND VOUT Inductor Phase Node High-Side MOSFETS VIN Output Capacitors Schottky Diode Low-Side MOSFETS Input Capacitors Figure 31. Typical Power Component Placement When placing MOSFETs, keep the source of the upper MOSFETs and the drain of the lower MOSFETs as close as thermally possible. Place input high-frequency capacitors close to the drain of the upper MOSFETs and the source of the lower MOSFETs. Place the output inductor and output capacitors between the MOSFETs and the load. Place high-frequency output decoupling capacitors (ceramic) as close as possible to the decoupling target (microprocessor), making use of the shortest connection paths to any internal planes. Place the components in such a way that the area under the IC has fewer noise traces with high dV/dt and di/dt, such as gate signals and phase node signals. Table 12 shows pin layout considerations for the ISL62776 controller. Table 12. Layout Guidelines ISL62776 Pin Symbol Layout Guidelines Bottom Pad GND Connect this ground pad to the ground plane through a low-impedance path. A minimum of five vias are recommended to connect this pad to the internal ground plane layers of the PCB. 1 PGOOD_SOC 2 SVC Use good signal integrity practices and follow AMD processor recommendations. 3 VR_HOT_L Follow AMD processor recommendations. Place the pull-up resistor near the IC. 4 5 6 SVD VDDIO SVT Use good signal integrity practices and follow AMD processor recommendations. 7 ENABLE No special considerations. 8 PWROK Use good signal integrity practices and follow AMD processor recommendations. 9 PGOOD No special considerations. R16DS0044EU0200 Rev.2.00 Oct.8.20 No special considerations. Page 45 of 49 ISL62776 9. Layout Guidelines Table 12. Layout Guidelines (Continued) ISL62776 Pin Symbol Layout Guidelines 10 NTC Place the NTC thermistor close to the thermal source that is monitored to determine core thermal throttling. Placement at the hottest spot of the Core VR is recommended. Place additional standard resistors in the resistor network on this pin near the IC. 11 PROG1 Place the PROG1 resistor close to this pin and keep a tight GND connection. 12 13 COMP FB Place the compensation components in the general proximity of the controller. 14 15 16 17 ISEN1 ISEN2 ISEN3 ISEN4 Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN and through another capacitor (Cvsumn) to GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small: Any ISEN pin to another ISEN pin Any ISEN pin to GND The red traces in the following drawing show the loops to be minimized. Phase1 L3 Ro R isen ISEN3 C isen Phase2 Vo L2 Ro R isen ISEN2 C isen Phase3 R isen ISEN1 GND ISUMP ISUMN Ro V vsumn C isen 18 19 L1 C vsumn Place the current-sensing circuit in the general proximity of the controller. Place capacitor Cn very close to the controller. Place the NTC thermistor next to the Core VR Channel 1 inductor so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in parallel fashion with sufficient width (>20 mil). IMPORTANT: To sense the inductor current, route the sensing circuit to the inductor pads. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current-sensing traces. Inductor Inductor Current-Sensing Traces Current-Sensing Traces Vias 20 IMON Place the IMON resistor close to this pin and keep a tight GND connection. 21 FCCM No special considerations. 22 23 24 25 PWM1 PWM2 PWM3 PWM4 No special considerations. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 46 of 49 ISL62776 9. Layout Guidelines Table 12. Layout Guidelines (Continued) ISL62776 Pin Symbol 26 VCC A high-quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close proximity to the pin with the filter resistor nearby the IC. 27 RTN Use signal integrity best practices. 28 GND Connect this ground pad to the ground plane through a low-impedance path. 29 VIN Place the decoupling capacitor in close proximity to the pin with a short connection to the internal GND plane. 30 PWM_SOC No special considerations. 31 FCCM_SOC No special considerations. 32 GND 33 IMON_SOC Place the IMON_SOC resistor close to this pin and keep a tight GND connection. 34 35 ISUMN_SOC ISUMP_SOC Use the same guidelines as the outline for Pins 18 and 19 (ISUMP and ISUMN). 36 37 FB_SOC COMP_SOC Place the compensation components in the general proximity of the controller. 38 PROG2 39 NTC_SOC 40 GND R16DS0044EU0200 Rev.2.00 Oct.8.20 Layout Guidelines Connect this ground pad to the ground plane through a low-impedance path. No special considerations. Place the NTC_SOC thermistor close to the thermal source that is monitored to determine SOC thermal throttling. Placement at the hottest spot of the SOC VR is recommended. Place additional standard resistors in the resistor network on this pin near the IC. Connect this ground pad to the ground plane through a low-impedance path. Page 47 of 49 ISL62776 10. Revision History 10. Revision History Rev. Date Description 2.00 Oct.8.20 SVC Frequency Range maximum value increased. 1.00 Oct.22.19 Initial release R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 48 of 49 ISL62776 11. Package Outline Drawing 11. Package Outline Drawing For the most recent package outline drawing, see L40.5x5. L40.5x5 40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 7/14 5.00 ± 0.05 4x3.60 A B 36x0.40 6 PIN #1 INDEX AREA (4X) 3.50 5.00 ± 0.05 6 PIN 1 INDEX AREA 0.15 40x0.4 ± 0.1 TOP VIEW BOTTOM VIEW 0.20 b 4 0.10 M C A B PACKAGE OUTLINE 0.40 0.750 ± 0.10 3.50 5.00 0.050 SEE DETAIL “X” SIDE VIEW // 0.10 C C BASE PLANE SEATING PLANE 0.08 C (36x0.40) 0.2 REF (40x0.20) C (40x0.60) 5 0.00 MIN 0.05 MAX TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220WHHE-1 either a mold or mark feature. R16DS0044EU0200 Rev.2.00 Oct.8.20 Page 49 of 49 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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