DATASHEET
ISL6341, ISL6341A, ISL6341B, ISL6341C
FN6538
Rev 2.00
Dec 2, 2008
5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
The ISL6341, ISL6341A, ISL6341B, ISL6341C makes
simple work out of implementing a complete control and
protection scheme for a DC/DC stepdown converter driving
N-Channel MOSFETs in a synchronous buck topology. Since
it can work with either 5V or 12V supplies, this one family of
IC’s can be used in a wide variety of applications within a
system. It integrates the control, gate drivers, output
adjustment, monitoring and protection functions into a single
10 Ld Thin DFN package.
The ISL6341, ISL6341A, ISL6341B, ISL6341C (hereafter
referred to as “ISL6341x”, except as needed) provides single
feedback loop, voltage-mode control with fast transient
response. The output voltage can be precisely regulated to as
low as 0.8V, with a maximum tolerance of ±0.8%
over-temperature and line voltage variations. A fixed frequency
oscillator and wide duty cycle range reduces design complexity,
while balancing typical application cost and efficiency. The
frequency, duty cycle and OCP response are the only
differences among the ISL6341x versions. See Table 1.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the lower MOSFET to inhibit PWM
operation appropriately (see “Overcurrent Protection (OCP)”
on page 8 for details). This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor. The output voltage is also
monitored for undervoltage and overvoltage protection, in
addition to monitoring for a PGOOD output.
Ordering Information
PART NUMBER
PART
TEMP.
(Note)
MARKING RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6341ACRZ*
41AC
0 to +70
10 Ld 3x3 TDFN L10.3x3B
ISL6341BCRZ*
41BC
0 to +70
10 Ld 3x3 TDFN L10.3x3B
ISL6341CCRZ*
41CC
0 to +70
10 Ld 3x3 TDFN L10.3x3B
ISL6341CRZ*
341C
0 to +70
10 Ld 3x3 TDFN L10.3x3B
ISL6341AIRZ*
41AI
-40 to +85
10 Ld 3x3 TDFN L10.3x3B
ISL6341BIRZ*
41BI
-40 to +85
10 Ld 3x3 TDFN L10.3x3B
ISL6341CIRZ*
41CI
-40 to +85
10 Ld 3x3 TDFN L10.3x3B
ISL6341IRZ*
6341
-40 to +85
10 Ld 3x3 TDFN L10.3x3B
ISL6341EVAL1Z Evaluation Board
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Operates from +4.5V to 14.4V Supply Voltage (for Bias)
- 1.5V to 12V VIN Input Range (Up to 20V is Possible with
Restrictions; see “Input Voltage Considerations” on
page 12)
- 0.8V to ~VIN Output Range (Duty Cycle Limited)
- Integrated Gate Drivers; LGATE Uses VCC (5V to 12V);
UGATE Uses External Boot Diode to (5V to 12V)
- 0.8V Internal Reference; ±0.8% Tolerance
• Simple Single-Loop Control Design
- Traditional Dual Edge Modulator
- Voltage-Mode PWM Control
- Drives N-Channel MOSFETs
• Fast Transient Response
- High-Bandwidth Error Amplifier
- 0% to 85% Max Duty Cycle for ISL6341, ISL6341C
- 0% to 75% Max Duty Cycle for ISL6341A, ISL6341B
• Lossless, Programmable Overcurrent Protection
- Uses Lower MOSFET’s rDS(ON)
- Latch off mode (ISL6341, ISL6341B)
- Infinite Retry (Hiccup) Mode (ISL6341A)
- Infinite Retry (Hiccup) Mode; no UVP (ISL6341C)
• Output Voltage Monitoring
- Undervoltage and Overvoltage Shutdown
- PGOOD Output
• Small Converter Size in 10 Ld 3x3 Thin DFN
- 300kHz Fixed Oscillator (ISL6341, ISL6341C)
- 600kHz Fixed Oscillator (ISL6341A, ISL6341B)
- Fixed Internal Soft-Start, Capable into a Pre-biased
Load
- Enable/Shutdown Function on COMP/EN Pin
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies for Microprocessors or Peripherals
- PCs, Servers, Memory Supplies
- DSP and Core Communications Processor Supplies
• Subsystem Power Supplies
- PCI, AGP; Graphics Cards; Digital TV
- SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus
Termination Supply
• Cable Modems, Set-Top Boxes, and DSL Modems
• Industrial Power Supplies; General Purpose Supplies
• 5V or 12V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies; Point of Load
FN6538 Rev 2.00
Dec 2, 2008
Page 1 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
Pinout
ISL6341, ISL6341A, ISL6341B, ISL6341C
(10 LD 3x3 TDFN)
TOP VIEW
BOOT
1
10 PGOOD
PHASE
2
9 VOS
UGATE
3
8 FB
LGATE/OCSET
4
7 COMP/EN
GND
5
6 VCC
Block Diagram
VCC
+
-
SAMPLE
AND
HOLD
POR AND
SOFT-START
OC
COMPARATOR
INTERNAL
REGULATOR
BOOT
UGATE
5V INT.
10µA
TO
LGATE/OCSET
ERROR
AMP
0.8V
+
-
20k
PWM
COMPARATOR
+
-
FB
INHIBIT
GATE
CONTROL
PWM LOGIC
VCC
EN
+
+25% 5V INT.
COMP/EN
PHASE
20µA
0.7V
+
-25% +
-
EN
LGATE/OCSET
OV1
GND
UV1
OSCILLATOR
300kHz OR 600kHz
OC
+
+10% -
OV2
PGOOD
VOS
-10% +
-
FN6538 Rev 2.00
Dec 2, 2008
UV2
Page 2 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
Typical Application
VCC
5V TO 12V
VIN
1.5V TO 12V
VGD
5V TO 12V
CDCPL
CHF
CBULK
VCC
BOOT
PGOOD 10
1
CBOOT
TYPE II
COMPENSATION
PHASE
2
SHOWN
COMP/EN
ISL6341x
7
UGATE
3
RF
CI FB 8
LGATE/OCSET
4
5
9
CF
VOS
GND
R
6
LOUT
+VO
COUT
OCSET
ROFFSET
RS
RVOS1
RVOS2
FN6538 Rev 2.00
Dec 2, 2008
Page 3 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
Absolute Maximum Ratings
Thermal Information
Supply Voltage, (VCC) . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . GND - 0.3V to 36V
BOOT to PHASE Voltage (VBOOT - VPHASE) . . . GND - 0.3V to 15V
-0.3V to 16V (
LGATE (12V/DIV)
GND>
UGATE (24V/DIV)
GND>
FIGURE 4. OCP TIMING (ISL6341, ISL6341B)
Figure 4 shows a typical waveform for the ISL6341,
ISL6341B, where the normal inductor current is around 10A,
and the OCP trip is 16A. This is just an illustration; the actual
shape of the waveforms depends on the component values,
as well as the characteristics of the load and the short. On the
third trip, the gate drivers stop switching, and the current goes
to zero. To recover from this latched off condition, the user
must toggle VCC (power-down and power-up) for a new POR,
or toggle COMP/EN pin to restart (either includes initialization
and soft-start).
As the output inductor current rises and falls, the output
voltage is also affected. Note that in extreme cases during
the three consecutive trips, the UV may actually trip before
the OCP. The IC provides protection in either case, but
perhaps not quite at the programmed current. An OCP trip
can be reset by toggling either POR or COMP/EN, but a UV
trip is only reset by toggling POR. See Table 2 for the
protection summary.
Starting up into a shorted load will be handled the same way;
but the waveforms may look different, since the output is not
yet at its final value. OCP is always enabled during soft-start
(UV is not); it will need the three consecutive trips to latch off.
ISL6341A, ISL6341C
Figure 5 shows the same conditions for the ISL6341A,
ISL6341C. For this version, when overcurrent is first
detected (while LGATE is high), the logic will shut off the
output (LGATE and UGATE both go low), and the current
goes to zero.
It will then go into a “hiccup” mode of infinite retries. After two
dummy soft-start time-outs, a real soft-start will begin. If the
short is still there, it will trip during the soft-start ramp, and
will start another retry cycle. Once the short is removed, the
next real soft-start will be successful, and normal operation
can continue.
Page 8 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
.
IINDUCTOR (10A/DIV)
INTERNAL SOFT-START RAMP DELAYS
OC
VOUT
(0.5V/DIV)
0A>
LGATE (12V/DIV)
GND>
UGATE (24V/DIV)
GND>
4.8ms
GND>
FIGURE 5. OCP TIMING (ISL6341A, ISL6341C)
Figure 6 shows the ISL6341A, ISL6341C output response
during a retry of an output shorted to GND. At time t0, the
output has been turned off, due to sensing an overcurrent
condition. There are two internal soft-start delay cycles (t1 and
t2) to allow the MOSFETs to cool down, to keep the average
power dissipation in retry at an acceptable level. At time t2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the
OCSET trip point any time during soft-start ramp period, the
output will shut off and return to time t0 for another delay cycle.
The retry period is thus two dummy soft-start cycles plus one
variable one, which depends on how long it takes to trip the
sensor each time. Figure 6 shows an example where the
output gets about half-way up before shutting down; therefore,
the retry (or hiccup) time will be around 12ms. The minimum
should be nominally 9.6ms and the maximum 14.4ms. If the
short condition is finally removed, the output should ramp up
normally on the next t2 cycle.
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always enabled
during soft-start; once it trips, it will go into retry (hiccup) mode.
The retry cycle will always have two dummy time-outs, plus
whatever fraction of the real soft-start time passes before the
detection and shut-off; at that point, the logic immediately
starts a new two dummy cycle time-out.
Both OCP and UVP protect against shorts to GND, but the
responses (and recovery from) are different, as shown in Table
2. For some combinations of output components and shorting
method, it may be difficult to predict which protection will trip
first (output voltage going too low, or current going too high).
The ISL6341C removes that uncertainty by disabling the UVP,
and relying only on the OCP. Note that for the other 3 versions,
if OCP trips first, it locks out the UVP from also tripping, so that
only the OCP response (and recovery) are active.
FN6538 Rev 2.00
Dec 2, 2008
t0
4.8ms
t1
0ms TO 4.8ms
t2
4.8ms
t0
FIGURE 6. OCP RETRY OPERATION (ISL6341A, ISL6341C)
OVERCURRENT EQUATIONS
For all the ISL6341x, versions, the overcurrent function will trip
at a peak inductor current (IPEAK) determined by Equation 1:
I OCSET xR OCSET
I PEAK = ------------------------------------------------r DS ON
(EQ. 1)
where IOCSET is the internal OCSET current source (10µA
typical). The OC trip point varies in a system mainly due to the
MOSFET’s rDS(ON) variations (over process, current and
temperature). To avoid overcurrent tripping in the normal
operating load range, find the ROCSET resistor from Equation
1 with:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the “Electrical Specification
Table” on page 5.
I
3. Determine IPEAK for I PEAK > I OUT MAX + ---------- ,
2
whereI is the output inductor ripple current.
For an equation for the ripple current see “Output Inductor
Selection” on page 15.
The range of allowable voltages detected (IOCSET*ROCSET) is
0mV to 550mV; but the practical range for typical MOSFETs is
smaller. If the voltage drop across ROCSET is set too low (<
~20mV), that can cause almost continuous OCP tripping. It
would also be very sensitive to system noise and in-rush
current spikes, so it should be avoided. The maximum setting
is 550mV, but most of the recommended MOSFETs for the
ISL6341x are not expected to handle the power of the
maximum trip point.
There is no way to disable the OCP, but setting it above the
maximum value (>600mV) will come close; for most cases, it
should be high enough (compared to the normal expected
range) to appear disabled. No resistor at all could give the
clamped maximum value (unless the loading on the LGATE
prevents charging the node fully). But there is no low-voltage
clamp on LGATE, so it could rise to over 3V and turn-on for
4ms during the sampling; that could discharge a pre-biased
Page 9 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
output. Therefore, to avoid that case, but still come close to
disabling OCP, a resistor (>60k) is recommended.
Note that conditions during power-up may look different than
normal operation. For example, during power-up in a 12V
system, the IC starts operation just above 4V; if the supply
ramp is slow, the soft-start ramp might be over well before 12V
is reached. So with lower gate drive voltages, the rDS(ON) of
the MOSFETs will be higher during power-up, effectively
lowering the OCP trip. In addition, the ripple current will likely
be different at lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient and a current spike to charge the output capacitors.
The height of the current spike is not controlled; it is affected by
the step size of the output, the value of the output capacitors,
as well as the IC error amp compensation. So it is possible to
trip the overcurrent with in-rush current, in addition to the
normal load and ripple considerations.
OCP is always enabled during soft-start, so there is protection
starting up into a shorted load.
Undervoltage Protection
The output is protected against undervoltage conditions by
monitoring the VOS pin. An external resistor divider (similar
ratio to the one on the FB pin) makes the voltage equal the
0.8V internal reference under normal operation. If the output
goes too low (25% below 0.8V = 0.6V nominal on VOS), the
output will latch off, with UGATE and LGATE both forced low.
This requires toggling VCC (power-down and up) to restart
(toggling COMP/EN will NOT restart it). The UV protection is not
enabled until the end of the soft-start ramp (as shown in Figure
2).
Figure 7 shows a case where VOUT (and thus VOS) is pulled
down to the 75% point; both gate drivers stop switching, and
the VOUT is pulled low by the disturbance, as well as the load,
at a rate determine by the conditions, and the output
components.
The ISL6341C version does not have UVP; it relies on the
OCP for shorted loads. The PGOOD UV comparator is
separate, and is still active.
VOUT (0.25V/DIV)
75%
GND>
LGATE (12V/DIV)
GND>
UGATE (24V/DIV)
GND>
FIGURE 7. UNDERVOLTAGE PROTECTION
Overvoltage Protection
The output is protected against overvoltage conditions by
monitoring the VOS pin, similar to undervoltage. If the output
goes too high (25% above 0.8V = 1.0V nominal on VOS), the
output will latch off. As shown in Figure 8, UGATE will be
forced low, but LGATE will be forced high (to try to pull-down
the output) until the output drops to 1/2 of the normal voltage
(50% of 0.8V = 0.4V nominal on VOS). The LGATE will then
shut off, but will keep turning back on whenever the output
goes too high again.
Overvoltage latch-off requires toggling VCC (power-down and
up) to restart (toggling COMP/EN will NOT restart it). The OV
protection is not enabled until the rising VCC POR trip point is
exceeded. The OV protection is active during soft-start at the
fixed 25% above the final expected voltage. The OVP is not
gated off by tripping OCP (but the UVP is gated off if OCP trips
first).
If the VOS pin is disconnected, a small bias current on-chip will
force an overvoltage condition.
VOUT (0.5V/DIV)
125%
50%
GND>
LGATE (12V/DIV)
GND>
UGATE (24V/DIV)
GND>
FIGURE 8. OVERVOLTAGE PROTECTION
FN6538 Rev 2.00
Dec 2, 2008
Page 10 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
PGOOD
The PGOOD function output monitors the output voltage using
the same VOS pin and resistor divider of the undervoltage and
overvoltage protection, but with separate comparators for each.
The rising OV trip point (10% above 0.8V = 0.88V nominal on
VOS) and the falling UV trip point (10% below 0.8V = 0.72V
nominal on VOS) will trip sooner than the protection, in order to
give an early warning to a possible problem. The response time
of the comparators should be less than 1µs; the separate VOS
input is not slowed down by the compensation on the FB pin. It
is NOT recommended to connect the VOS pin to the FB pin, in
order to share the resistor divider. If the VOS pin is accidentally
disconnected, a small bias current on-chip will force an
overvoltage condition.
Figure 9 shows how the PGOOD output responds to a ramp
that trips in each direction (without reaching either protection
trip point at ±25%); PGOOD is valid (high) as long as VOUT
(and thus VOS) is within the ±10% window.
110%
90%
VOUT (0.25V/DIV)
PGOOD output should already be low by the time either
protection is tripped.
TABLE 2. PROTECTION SUMMARY
PROTECTION
ACTION TAKEN
ENABLED
AFTER
RESET
BY
OCP
ISL6341
ISL6341B
VOUT latches off;
LGATE and UGATE low.
OCP
ISL6341A
ISL6341C
POR or
Not
Infinite retries; wait ~10ms,
and try a new Soft-Start ramp. COMP/EN Applicable
ISL6341C has UVP disabled
UVP
(-25%)
VOUT latches off;
after SS
ramp
LGATE and UGATE low.
ISL6341C has UVP disabled
POR
OVP
(+25%)
POR
VOUT latches off;
UGATE low;
LGATE goes low and high to
keep VOUT within 50% and
125% of nominal.
VOS pin open will trigger OV.
POR
PGOOD
(UV; -10%)
PGOOD goes low if VOS is
10% too low.
after SS
ramp
POR or
COMP/EN
PGOOD
(OV; +10%)
PGOOD goes low if VOS is
10% too high.
after SS
ramp
POR or
COMP/EN
PGOOD
(OCP)
PGOOD goes low if OCP trips after SS
ramp
POR or
COMP/EN
or good
SS ramp
GND>
POR or
POR or
COMP/EN COMP/EN
PGOOD (2V/DIV)
Switching Frequency
GND>
FIGURE 9. PGOOD UNDERVOLTAGE AND OVERVOLTAGE
The PGOOD output is an open-drain pull-down NMOS device; it
can deliver 4.0mA of sink current at 0.3V when power is NOT
GOOD. A pull-up resistor to an external supply voltage sets the
high level voltage when power is GOOD. The supply should be
6.0V, and is usually the one that powers the logic monitoring
the PGOOD output. If PGOOD function is not used, the PGOOD
pin can be left floating.
The PGOOD pin will be held low once VCC is above the rising
POR trip point, and during soft-start (but if the PGOOD supply is
up before or with VCC, it may be pulled high initially until the
logic has enough voltage to turn on the output). Once the
soft-start ramp is done (VOUT, VOS and FB should each be at
100% of their final value), the PGOOD pin will be allowed to go
high, if the output voltage is within the expected window. There
is no additional delay after soft-start is done.
Note that the overcurrent protection does directly affect the
PGOOD output, before the output voltage monitoring would
sense when VOUT drops 10%. The overvoltage and
undervoltage protection circuits don’t directly effect PGOOD,
but since the PGOOD UV and OV windows are tighter, the
FN6538 Rev 2.00
Dec 2, 2008
The switching frequency is a fixed 300kHz for the ISL6341,
ISL6341C and 600kHz for the ISL6341A, ISL6341B. It cannot
be adjusted externally, and the various soft-start delays and
ramps are fixed at the same times for either frequency.
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the VIN supply, with the 85%
duty cycle restriction for the ISL6341, ISL6341C (75% for the
ISL6341A, ISL6341B). Additional duty cycle margin due to the
rDS(ON) drop across the upper FET at maximum load needs to
be factored in as well.
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage, and feed it back to the
inverting input of the error amp. See the “Typical Application”
schematic on page 3 for more detail; RS is the upper resistor;
ROFFSET (shortened to RO below) is the lower one. The
recommended value for RS is 1k to 5k (±1% for accuracy)
and then ROFFSET is chosen according to Equation 2. Since
RS is part of the compensation circuit (see “Feedback
Compensation” on page 13), it is often easier to change
ROFFSET to change the output voltage; that way the
compensation calculations do not need to be repeated. If
Page 11 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
VOUT = 0.8V, then ROFFSET can be left open. Output voltages
less than 0.8V are not available.
RS + RO
V OUT = 0.8V --------------------------RO
(EQ. 2)
R S 0.8V
R O = ---------------------------------V OUT – 0.8V
The VOS pin is expected to see the same ratio for its resistor
divider; RVOS1 should also be chosen in the 1k to 5k (±1%
for accuracy) range. To simplify the BOM, RVOS1 should match
RS, and RVOS2 should match ROFFSET.
If margining (or similar programmability) is added externally
(using a switch to change the effective lower resistor value),
the same method may be needed on the VOS pin resistor
divider. If the new VOUT (FB) is shifted too much compared to
the VOS trip, then PGOOD or UV/OV will be more likely to trip
in one direction (and less likely in the other).
Input Voltage Considerations
The “Typical Application” diagram on page 3 shows a standard
configuration where VCC is 5V to 12V, which includes the
standard 5V (±10%) or 12V (±20%) power supply ranges. The
gate drivers use the VCC voltage for LGATE, and VGD (also 5V
to 12V) for BOOT/UGATE. There is an internal 5V regulator for
bias.
The VIN to the upper MOSFET can share the same supply as
VCC, but can also run off a separate supply or other sources,
such as outputs of other regulators. If VCC powers up first, and
the VIN or VGD are not present by the time the initialization is
done, then undervoltage will trip at the end of soft-start (and
will not recover without toggling VCC; toggling COMP/EN will
not restart it). Therefore, either the supplies must be turned on
in the proper order (together, or VCC last), or the COMP/EN pin
should be used to disable VOUT until all supplies are ready.
Figure 10 shows a simple sequencer for this situation. If VCC
powers up first, Q1 will be off and R3 pulling to VCC will turn Q2
on, keeping the ISL6341x in shut-down. When VIN turns on,
the resistor divider R1 and R2 determines when Q1 turns on,
which will turn off Q2, and release the shut-down.
VIN
R1
R2
R3
TO COMP/EN
Q2
FIGURE 10. SEQUENCER CIRCUIT
FN6538 Rev 2.00
Dec 2, 2008
The VIN range can be as low as ~1.5V (for VOUT as low as the
0.8V reference). It can be as high as 20V (for VOUT just below
VIN, limited by the maximum duty cycle). There are some
restrictions for running high VIN voltage.
The first consideration for high VIN is the maximum BOOT
voltage of 36V. The VIN (as seen on PHASE) plus VGD (boot
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If VIN is
20V, that limits VGD plus ringing to 16V.
The second consideration is the maximum voltage ratings for
VCC and BOOT-PHASE (for VGD); both are set at 15V. If VIN is
above the maximum operating range for VCC of 14.4V, then
both VCC and VGD need to be supplied separately. They can
be derived from VIN (using a linear regulator or equivalent), or
they can be independent. In either case, they must satisfy the
power supply sequencing requirements noted earlier (either
power-up in the proper order, or use a sequencer to disable the
output until they are all ready).
The third consideration for high VIN is duty cycle. Very low duty
cycles (such as 20V in to 1.0V out, for 5% duty cycle) require
component selection compatible with that choice (such as low
rDS(ON) lower MOSFET, a good LC output filter, and
compensation values to match). At the other extreme (for
example, 20V in to 12V out), the upper MOSFET needs to be
lower rDS(ON). There is also the maximum duty cycle
restriction. In all cases, the input and output capacitors and
both MOSFETs must be rated for the voltages present.
Application Guidelines
Layout Considerations
VCC
Q1
If VIN powers up first, Q1 will be on, turning Q2 off; so the
ISL6341x will start-up as soon as VCC comes up. The
VENABLE trip point is 0.7V nominal, so a wide variety of
NFET’s or NPN’s or even some logic IC’s can be used as Q1 or
Q2. But Q2 should pull down hard when on, and must be low
leakage when off (open-drain or open-collector) so as not to
interfere with the COMP output. The Vth (or Vbe) of Q2 should
be reviewed over process and temperature variations to insure
that it will work properly under all conditions. Q2 should be
placed near the COMP/EN pin.
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible, using ground plane
construction or single point grounding.
Page 12 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
address a broad range of applications, a type-3 feedback
network is recommended, as shown in the top part of
Figure 13.
.
UGATE
Q1
LO
PHASE
LGATE/OCSET
CIN
Q2
Figure 13 also highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6341x circuit. The output voltage (VOUT) is regulated to the
reference voltage, VREF. The error amplifier output (COMP pin
voltage) is compared with the oscillator (OSC) modified
sawtooth wave to provide a pulse-width modulated wave with
an amplitude of VIN at the PHASE node. The PWM wave is
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
VOUT
LOAD
ISL6341x
VIN
CO
RETURN
FIGURE 11. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 11 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown should be
located as close together as possible. Please note that the
capacitors CIN and CO may each represent numerous physical
capacitors. For best results, locate the ISL6341x within 1 inch of
the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFET
gate and source connections from the ISL6341x must be sized to
handle up to 2A peak current.
The modulator transfer function is the small-signal transfer
function of VOUT /VCOMP. This function is dominated by a DC
gain, given by dMAXVIN /VOSC , and shaped by the output filter,
with a double pole break frequency at FLC and a zero at FCE .
For the purpose of this analysis, L and D represent the channel
inductance and its DCR, while C and E represent the total output
capacitance and its equivalent series resistance.
1
F LC = --------------------------2 L C
1
F CE = -----------------------2 C E
C2
+VGD
VOS
COMP/EN
FB
ISL6341x
+VCC
BOOT
+VIN
CBOOT
Q1 LO
COMP
R2
Q2
CO
E/A
CVCC
GND
ROCSET
Figure 12 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Provide local VCC decoupling between
VCC and GND pins. Locate the capacitor, CBOOT as close as
practical to the BOOT and PHASE pins. Locate the resistor,
ROSCET close to the LGATE/OCSET pin because the internal
current source is only 10µA. Minimize any leakage current
paths on the COMP/EN pin. All components used for feedback
compensation and VOS resistor divider (inside the dotted box)
should be located as close to the IC as practical. Near the load,
pick a point VOUT that will be the regulation center; run a single
unloaded narrow trace from there to the compensation
components. The same trace can also be used for VOS
divider.
Feedback Compensation
This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
+
R1
FB
Ro
VREF
FIGURE 12. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
FN6538 Rev 2.00
Dec 2, 2008
C3
R3
C1
PHASE
LGATE/OCSET
VCC
VOUT
LOAD
VOUT
(EQ. 3)
VOUT
OSCILLATOR
VIN
PWM
CIRCUIT
VOSC
UGATE
HALF-BRIDGE
DRIVE
L
D
PHASE
C
E
LGATE
ISL6341x
EXTERNAL CIRCUIT
FIGURE 13. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The compensation network consists of the error amplifier (internal
to the ISL6341x) and the external R1 to R3, C1 to C3
components. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing frequency
Page 13 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
(F0; typically 0.1 to 0.3 of fSW) and adequate phase margin
(better than 45°). Phase margin is the difference between the
closed loop phase at F0dB and 180°. The equations that follow
relate the compensation network’s poles, zeros and gain to the
components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 13. Use the
following guidelines for locating the poles and zeros of the
compensation network:
4. Select a value for R1 (1k to 5k, typically). Calculate the
value for R2 for desired converter bandwidth (F0). If setting
the output voltage via an offset resistor connected to the FB
pin (Ro in Figure 13), the design procedure can be followed
as presented in Equation 4.
V OSC R 1 F 0
R 2 = --------------------------------------------d MAX V IN F LC
(EQ. 4)
5. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired
number). The higher the quality factor of the output filter and/or
the higher the ratio FCE/FLC, the lower the FZ1 frequency (to
maximize phase boost at FLC).
1
C 1 = ----------------------------------------------2 R 2 0.5 F LC
R
G CL f = G MOD f G FB f
where s f = 2 f j
(EQ. 8)
COMPENSATION BREAK FREQUENCY EQUATIONS
1
F P1 = -------------------------------------------C
C
R
1 2
2 2 -------------------C
C
1+ 2
1
F Z1 = -----------------------------R
C
2 2 1
1
F Z2 = -----------------------------------------------R
R
C
2 1 + 3 3
(EQ. 9)
1
F P2 = -----------------------------R
C
2 3 3
FP1
FP2
GAIN
FZ1 FZ2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
(EQ. 6)
7. Calculate R3 such that FZ2 is placed at FLC. Calculate C3
such that FP2 is placed below fSW (typically, 0.5 to 1.0 times
fSW). fSW represents the switching frequency. Change the
numerical factor to reflect desired placement of this pole.
Placement of FP2 lower in frequency helps reduce the gain
of the compensation network at high frequency, in turn
reducing the HF ripple component at the COMP pin and
minimizing resultant duty cycle jitter.
1
C 3 = ----------------------------------------------2 R 3 0.7 f SW
R
2
20 log --------
R
1
d MAX V
IN
20 log --------------------------------V OSC
0
GFB
GCL
LOG
C1
C 2 = -------------------------------------------------------2 R 2 C 1 F CE – 1
C
1 + sf 2 1
G FB f = ---------------------------------------------------
R
C
C
sf 1 1 + 2
R
R
C
1 + sf 1 + 3 3
-----------------------------------------------------------------------------------------------------------------------
C1 C2
R
C
R
1 + s f 3 3 1 + s f 2 --------------------
C1 + C2
(EQ. 5)
6. Calculate C2 such that FP1 is placed at FCE.
R1
R 3 = -------------------f SW
----------- – 1
F LC
d MAX V IN
1 + sf E C
G MOD f = ------------------------------ ---------------------------------------------------------------------------------------2
V OSC
1 + sf E + D C + s f L C
GMOD
LOG
FLC
FCE
F0
FREQUENCY
FIGURE 14. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
(EQ. 7)
It is recommended that a mathematical model be used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 8 and 9 describe the frequency
response of the modulator (GMOD), feedback compensation
(GFB) and closed-loop response (GCL):
Figure 14 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter, which
is not shown. Using the previous guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 against the capabilities of the error
amplifier. The closed loop gain, GCL, is constructed on the log-log
graph of Figure 14 by adding the modulator gain, GMOD (in dB),
to the feedback compensation gain, GFB (in dB). This is
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
FN6538 Rev 2.00
Dec 2, 2008
Page 14 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of the
switching frequency, fSW.
This is just one method to calculate compensation components;
there are variations of the compensation break frequency
equations. The error amp is similar to that on other Intersil
regulators, so existing tools can be used here as well. Special
consideration is needed if the size of a ceramic output
capacitance in parallel with bulk capacitors gets too large; the
calculation needs to model them both separately (attempting to
combine two different capacitors types into one composite
component model may not work properly; a special tool may be
needed; contact your local Intersil person for assistance).
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current. The
load transient requirements are a function of the slew rate
(di/dt) and the magnitude of the transient load current. These
requirements are generally met with a mix of capacitors and
careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate seen
by the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (Effective Series Resistance)
and voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for switchingregulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor’s ESR value is related to the case size with
lower ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately, ESL
is not a specified parameter. Work with your capacitor supplier
and measure the capacitor’s impedance with frequency to select
a suitable component. In most cases, multiple electrolytic
capacitors of small case size perform better than a single large
case capacitor.
FN6538 Rev 2.00
Dec 2, 2008
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function of
the ripple current. The ripple voltage and current are
approximated by Equation 10:
I =
VIN - VOUT
Fsw x L
x
VOUT
VOUT = I x ESR
VIN
(EQ. 10)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6341x will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval, the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the application
of load and the removal of load. Equation 11 gives the
approximate response time interval for application and removal
of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
(EQ. 11)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be
sure to check Equation 11 at the minimum and maximum
output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors
for high frequency decoupling and bulk capacitors to supply the
current needed each time Q1 turns on. Place the small ceramic
capacitors physically close to the MOSFETs and between the
drain of Q1 and the source of Q2 .
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25x greater than the maximum input
voltage and a voltage rating of 1.5x is a conservative guideline.
The RMS current rating requirement for the input capacitor of a
buck regulator is approximately 1/2 the DC load current.
Page 15 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
MOSFET Selection/Considerations
The ISL6341x requires 2 N-Channel power MOSFETs. These
should be selected based upon rDS(ON) , gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design factors.
The power dissipation includes two loss components; conduction
loss and switching loss. The conduction losses are the largest
component of power dissipation for both the upper and the lower
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor. The switching losses seen
when sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower switch
realizes most of the switching losses when the converter is
sinking current (see Equation 12). Equation 12 assumes linear
voltage-current transitions and does not adequately model power
loss due to the reverse-recovery of the upper and lower
MOSFET’s body diode. The gate-charge losses are dissipated by
the ISL6341x and don't heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases the
MOSFET switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
MOSFETs. Look for rDS(ON) ratings at 4.5V. Caution should be
exercised with devices exhibiting very low VGS(ON)
characteristics. The shoot-through protection present aboard
the ISL6341x may be circumvented by these MOSFETs if they
have large parasitic impedences and/or capacitances that
would inhibit the gate of the MOSFET from being discharged
below its threshold level before the complementary MOSFET is
turned on. Also avoid MOSFETs with excessive switching
times; the circuitry is expecting transitions to occur in under
50ns or so.
BOOTSTRAP Considerations
Figure 15 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from VGD. For convenience, VGD usually
shares the VIN or VCC supply; it can be any voltage in the 5V
to 12V range. The boot capacitor, CBOOT, develops a floating
supply voltage referenced to the PHASE pin. The supply is
refreshed to a voltage of VGD less the boot diode drop (VD)
each time the lower MOSFET, Q2 , turns on. Check that the
voltage rating of the capacitor is above the maximum VCC
voltage in the system; a 16V rating should be sufficient for a
12V system. A value of 0.1µF is typical for many systems
driving single MOSFETs.
If VCC is 12V, but VIN is lower (such as 5V), then another
option is to connect the BOOT pin to 12V, and remove the
BOOT cap (although, you may want to add a local capacitor
from BOOT to GND). This will make the UGATE VGS voltage
equal to (12V - 5V = 7V). That should be high enough to drive
most MOSFETs, and low enough to improve the efficiency
slightly. This also saves a boot diode and capacitor.
+VGD
+VCC
VCC
ISL6341x
BOOT
CBOOT
Losses while Sourcing Current
1
P UPPER = Io r DS ON D + --- Io V IN t SW F S
2
PLOWER = Io2 x rDS(ON) x (1 - D)
2
UGATE
Where: D is the duty cycle = VOUT / VIN ,
tSW is the combined switch ON and OFF time, and
fSW is the switching frequency.
Q1
PHASE
VG-S VGD - VD
VCC
Losses while Sinking Current
(EQ. 12)
PUPPER = Io2 x rDS(ON) x D
2
1
P LOWER = Io r DS ON 1 – D + --- Io V IN t SW F S
2
+VIN
- VD +
For a through-hole design, several electrolytic capacitors may be
needed. For surface mount designs, solid tantalum capacitors can
also be used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be capable
of handling the surge current at power-up. Some capacitor series
available from reputable manufacturers are surge current tested.
Q2
-
+
LGATE/OCSET
VG-S VCC
GND
FIGURE 15. UPPER GATE DRIVE BOOTSTRAP
When operating with a 12V power supply for VCC (or down to a
minimum supply voltage of 4.5V), a wide variety of
N-MOSFETs can be used. Check the absolute maximum VGS
rating for both MOSFETs; it needs to be above the highest VCC
voltage allowed in the system; that usually means a 20V VGS
rating (which typically correlates with a 30V VDS maximum
rating). Low threshold transistors (around 1V or below) are not
recommended, as explained in the following.
For 5V only operation, given the reduced available gate bias
voltage (5V), logic-level transistors should be used for both N-
FN6538 Rev 2.00
Dec 2, 2008
Page 16 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3B
2X
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
0.15 C A
A
D
MILLIMETERS
2X
0.15 C B
E
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A3
6
INDEX
AREA
b
0.20 REF
0.18
D
TOP VIEW
D2
B
A
C
SEATING
PLANE
D2
6
INDEX
AREA
0.08 C
A3
SIDE VIEW
(DATUM B)
0.10 C
7
8
2.23
2.38
2.48
7, 8
1.74
7, 8
3.00 BSC
1.49
e
-
1.64
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
10
Nd
5
2
3
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
CL
NX (b)
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
(DATUM A)
8
5, 8
NOTES:
2
N
0.30
Rev. 0 2/06
D2/2
1
E2
0.25
3.00 BSC
E
//
-
(A1)
9 L
5
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FN6538 Rev 2.00
Dec 2, 2008
Page 17 of 18
ISL6341, ISL6341A, ISL6341B, ISL6341C
© Copyright Intersil Americas LLC 2007-2008. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6538 Rev 2.00
Dec 2, 2008
Page 18 of 18
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