ISL6410IUZ

DATASHEET ISL6410, ISL6410A FN9149 Rev 3.00 September 17, 2004 Single Synchronous Buck Regulators with Integrated FET The ISL6410, ISL6410A are synchronous current-mode PWM regulators designed to provide a total DC-DC solution for microcontrollers, microprocessors, CPLDs, FPGAs, core processors/BBP/MAC, and ASICs. The ISL6410 should be selected for applications using 3.3V ±10% as an input voltage and the ISL6410A in applications requiring 5.0V ±10%. These synchronous current mode PWM regulators have integrated N- and P-Channel power MOSFETs and provide pre-set pin programmable outputs. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and a reduced external component count. The operating frequency of 750kHz typical allows the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. A power good signal “PG” is generated when the output voltage falls outside the regulation limits. Other features include overcurrent protection and thermal overload shutdown. The ISL6410, ISL6410A are available in an MSOP 10 lead package. Ordering Information PKG. DWG. # ISL6410IR -40 to 85 16 Ld 4x4 QFN L16.4x4 ISL6410IRZ (Note) -40 to 85 16 Ld 4x4 QFN (Pb-free) L16.4x4 ISL6410IU -40 to 85 10 Ld MSOP M10.118 ISL6410IUZ (Note) -40 to 85 10 Ld MSOP (Pb-free) M10.118 ISL6410AIR -40 to 85 16 Ld 4x4 QFN L16.4x4 ISL6410AIRZ (Note) -40 to 85 16 Ld 4x4 QFN (Pb-free) L16.4x4 ISL6410AIU -40 to 85 10 Ld MSOP M10.118 ISL6410AIUZ (Note) -40 to 85 10 Ld MSOP (Pb-free) M10.118 • Continuous Output Current . . . . . . . . . . . . . . . . . . 600mA • Ultra-Compact DC-DC Converter Design • Stable with Small Ceramic Output Capacitors • High Conversion Efficiency • Extensive Circuit Protection and Monitoring features - Overvoltage, UVLO - Overcurrent - Thermal Shutdown • Available in MSOP and QFN packages • QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile • Pb-Free Packaging Available Applications • CPUs, DSP, CPLDs, FPGAs • ASICs • DVD and DSL applications • WLAN Cards • Generic 5V to 3.3V Conversion Pinouts ISL6410 (MSOP) TOP VIEW PVCC 1 10 PGND PVCC L PGND NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. ISL6410 (QFN) TOP VIEW VIN *For tape and reel, add “-T”, “-TK” or “-T5K” suffix. VIN 2 9 L 16 15 14 13 GND 3 8 EN PG 4 7 FB 5 6 VIN 1 12 NC SYNC CT 2 11 VSET GND 3 10 EN PG 4 9 FB 5 FN9149 Rev 3.00 September 17, 2004 6 7 8 PG PACKAGE • PWM Fixed Output Voltage Options - 1.8V, 1.5V or 1.2V with ISL6410 (VIN = 3.3V) - 3.3V, 1.8V or 1.2V with ISL6410A (VIN = 5.0V) VSET TEMP. RANGE (°C) • Fully Integrated Synchronous Buck Regulator NC PART NUMBER* Features Page 1 of 13 RESET SYNC VIN 0.1µF 10µF PVCC 2 VIN 3 GND 1 CURRENT SENSE SLOPE COMPENSATION SOFT START EN EA PWM OVERCURRENT, OVERVOLTAGE LOGIC GM L1 8.2µH GATE DRIVE L 9 VOUT 10µF COMPENSATION PGND 7 SYNC 6 VSET 10 750kHz OSCILLATOR POWER GOOD PWM VOUT UVLO 8 PWM REFERENCE 0.45V EN FB 4 PG Page 2 of 13 NOTES: 1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A. 2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A. 5 ISL6410, ISL6410A FN9149 Rev 3.00 September 17, 2004 Functional Block Diagram for MSOP Version VIN 0.1µF 10µF PVCC CURRENT SENSE 16 VIN 3 15 SLOPE COMPENSATION SOFT START GND EN EA L1 8.2µH PWM OVERCURRENT, OVERVOLTAGE LOGIC GM L GATE DRIVE 14 VOUT 10µF COMPENSATION PGND 9 SYNC 7 VSET 13 750kHz OSCILLATOR POWER GOOD PWM VIN 11 VOUT RESET BLOCK UVLO RESET PWM REFERENCE 0.45V 10 EN FB 4 PG 8 PG 2 C T Page 3 of 13 NOTES: 1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A. 2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A. 5 ISL6410, ISL6410A FN9149 Rev 3.00 September 17, 2004 Functional Block Diagram for QFN Version ISL6410, ISL6410A Typical Application Schematics VIN 3.3V ±10% CIN 10µF 0.1µF 1 PVCC 2 VIN L1 8.2µH PGND 10 3 GND VOUT 1.8V L 9 ISL6410 EN 8 4 PG SYNC 7 5 FB VSET 6 COUT 10µF FIGURE 1. SCHEMATIC USING THE ISL6410 MSOP VIN 5.0V ±10% CIN 10µF 0.1µF 1 PVCC L1 12µH PGND 10 2 VIN ISL6410A 3 GND VOUT 3.3V L 9 EN 8 4 PG SYNC 7 5 FB VSET 6 COUT 10µF FIGURE 2. SCHEMATIC USING THE ISL6410A MSOP L1 +3.3V VIN +1.2V VOUT 8.2µH 1 2 VIN L VIN GND PGND 16 15 14 13 1µF PVCC CIN 10µF COUT 10µF NC 12 GND 11 CT RESET U1 10 GND ISL6410IR EN 9 4 PG SYNC 17 EP VSET 5 PG CT 0.01µF FB C7 0.1µF NC 3 6 7 8 RESET BAR FIGURE 3. SCHEMATIC USING THE ISL6410 QFN FN9149 Rev 3.00 September 17, 2004 Page 4 of 13 ISL6410, ISL6410A Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V SYNC, FB, VSET & Enable Input (Note 3) . . . . -0.3V to VCC+0.3V ESD Classification (Human Body Model) . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Typical) JA (°C/W) JC (°C/W) MSOP Package (Note 4) . . . . . . . . . . . 128 NA QFN Package (Notes 4, 5). . . . . . . . . . 45 7.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (10s, soldering . . . . . . . . . . . . . 260°C Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . -40°C to 85°C Junction Temperature Range. . . . . . . . . . . . . . . . . . . -40°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. All voltages are with respect to GND. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended operating conditions unless otherwise noted. VIN = 3.3V ±10% (ISL6410) or 5V ±10% (ISL6410A), TA = 25°C (Note 6). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIN (ISL6410) 3.0 3.3 3.6 V VIN (ISL6410A) 4.5 5.0 5.5 V VTR (ISL6410) Rising 2.62 2.68 2.73 V VTF (ISL6410) Falling 2.53 2.59 2.64 V VTR (ISL6410A) Rising 4.27 4.37 4.45 V VTF (ISL6410A) Falling 4.1 4.22 4.32 V - 2.3 - mA VCC SUPPLY Supply Voltage Range Input UVLO Threshold Quiescent Supply Current Shutdown Supply Current Thermal Shutdown Temperature (Note 7) IOUT = 0mA EN = GND, TA = 25°C - 5 10 A EN = GND, TA = 85°C - 10 15 A Rising Threshold - 150 - °C - 20 25 °C ISL6410, VSET = L - 1.2 - V ISL6410, VSET = H - 1.8 - V ISL6410, VSET = OPEN - 1.5 - V ISL6410A, VSET = L - 1.2 - V ISL6410A, VSET = H - 3.3 - V ISL6410A, VSET = OPEN - 1.8 - V Thermal Shutdown Hysteresis (Note 7) SYNCHRONOUS BUCK PWM REGULATOR Output Voltage Output Voltage Accuracy IOUT = 3mA, TA = -40°C to 85°C -1.5 - +1.5 % Line Regulation IOUT = 3mA -0.5 - +0.5 % Load Regulation IOUT = 3mA to 600mA -1.5 - +1.5 % Maximum Output Current - - 600 mA Peak Output Current Limit 700 - 1300 mA PMOS rDS(ON) IOUT = 200mA - 230 - m NMOS rDS(ON) IOUT = 200mA - 230 - m Efficiency IOUT = 200mA, VIN = 3.3V, VO = 1.8V (ISL6410) - 92 - % FN9149 Rev 3.00 September 17, 2004 Page 5 of 13 ISL6410, ISL6410A Electrical Specifications Recommended operating conditions unless otherwise noted. VIN = 3.3V ±10% (ISL6410) or 5V ±10% (ISL6410A), TA = 25°C (Note 6). (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Efficiency IOUT = 200mA, VIN = 5.0V, VO = 3.3V (ISL6410A) - 93 - % Efficiency IOUT = 600mA, VIN = 5.0V, VO = 3.3V (ISL6410A) - 91 - % Soft-Start Time 4096 Clock Cycles @ 750kHz - 5.5 - ms 620 750 860 kHz OSCILLATOR Oscillator Frequency Frequency Synchronization Range (fSYNC) Clock signal on SYNC pin 500 - 1000 kHz SYNC High Level Input Voltage As % of VIN 70 - - % SYNC Low Level Input Voltage As % of VIN - - 30 % Sync Input Leakage Current SYNC = GND or VIN -1 - 1 A 20 - 60 % +5.0 8.0 +10.5 % -10.5 -8.0 -5.0 % - 1 - % 70 - - % - 30 % 1 A Duty Cycle of External Clock Signal (Note 7) PGOOD (ISL6410 interfaces to 3.3V Logic, ISL6410A interfaces to 5.0V Logic) Rising Threshold 1mA minimum source/sink Falling Threshold Rising/Falling Hysteresis ENABLE EN High Level Input Voltage As % of VIN EN Low Level Input Voltage As % of VIN - EN Input Leakage Current EN = GND or VIN -1 OVERVOLTAGE Overvoltage Threshold 27 30 33 % 0.8VIN - - V - - 0.3 V RESET BLOCK SPECIFICATIONS RESET (reset released) ISL6410, ISOURCE = 500µA, VIN = 2.90V RESET (reset asserted) ISL6410, ISINK = 1.2mA, VIN = 2.50V RESET Rising Threshold ISL6410 2.74 2.78 2.81 V RESET Falling Threshold ISL6410 2.72 2.77 2.79 V RESET (reset released) ISL6410A, ISOURCE = 800µA, VIN = 4.70V 0.8VIN - - V RESET (reset asserted) ISL6410A, ISINK = 3.2mA, VIN = 4.10V - - 0.4 V RESET Rising Threshold ISL6410A 4.5 4.58 4.64 V RESET Falling Threshold ISL6410A 4.47 4.55 4.61 V RESET Threshold Hysteresis ISL6410 - 20 - mV RESET Threshold Hysteresis ISL6410A - 30 - mV RESET Active Timeout Period (Note 8) CT = 0.01mF - 25 - ms VSET High Level Input VIN-0.4V - - V VSET Low Level Input - - 0.4 V VSET Open Level Input - VIN /2 - V VSET NOTES: 6. Specifications at -40°C and +85°C are guaranteed by design, not production tested. 7. Guaranteed by design, not production tested. 8. The RESET Timeout period is linear with CT at a slope of 2.5ms/nF, thus a 10nF capacitor provides for 25ms. FN9149 Rev 3.00 September 17, 2004 Page 6 of 13 ISL6410, ISL6410A Pin Description VIN - Supply voltage for the IC. It is recommended to place a 1µF decoupling capacitor as close as possible to the IC. GND - Small signal ground for the PWM controller stage. All internal control circuits are referenced to this pin. PG - The Power good is an open-drain output. A pull-up resistor should be connected between PG and VIN. It is asserted active high when the output voltage reaches 94.5% of the nominal value. FB - The Feedback pin is used to sense the output voltage, and should be connected to VOUT for normal operation. VSET - This pin is used to program the output voltages. Refer to Table 1 below for details. TABLE 1. VSET ISL6410 Vo ISL6410A Vo High 1.8V 3.3V Open (NC) 1.5V 1.8V Low 1.2V 1.2V of 750kHz typical allows the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. The PG output indicates loss of regulation on PWM output. The PWM is based on the peak current mode control topology with internal slope compensation. At the beginning of each clock cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an internal circuit. On exceeding a preset limit the high side switch is turned off causing the PWM comparator to trip. This occurs whenever the output voltage is in regulation or when the inductor current reaches the current limit. After a minimum dead time to prevent shoot through current, the low side Nchannel MOSFET turns on and the current ramps down. As the clock cycle is completed, the low side switch turns off and the next clock cycle is initiated. The control loop is internally compensated thus reducing the amount of external components. The switch current is internally sensed and the maximum current limit is 1300mA peak. Synchronization L - This pin is the drain junction of the internal power MOSFETs and is to be connected to the external inductor. The typical operating frequency for the converter is 750kHz. It is possible to synchronize the converter to an external clock frequency in the range of 500kHz to 1000kHz when an external signal is applied to SYNC pin. The device will automatically detect and synchronize to the rising edge of the first clock pulse. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues its operation without interruption. The switch over will be initiated if no rising edge triggers are present on the SYNC pin for a duration of four clock cycles. PGND - Power ground. Connect all power grounds to this pin. Soft-Start SYNC - This pin is used for synchronization. The converter switching frequency can be synchronized to an external CMOS clock signal in the range of (500kHz to 1MHz). EN - A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 10A at 25°C. This pin should be pulled up to VCC via a 10K resistor. PVCC - This pin provides the Input supply for the internal MOSFETs. It is recommended to place a 1µF decoupling capacitor as close as possible to the IC. CT - Timing capacitor connection to set the 25ms minimum pulse width for the RESET signal. RESET - The outputs of the reset supervisory circuit, which monitors VIN. The IC asserts these RESET signals whenever the supply voltage drops below a preset threshold and keeps it asserted for at least 25ms after VCC (VIN) has risen above the reset threshold. These outputs are push-pull. RESET is LOW when re-setting the microprocessor. The PWM will continue to operate until VIN drops below the UVLO threshold. As the EN (Enable) pin goes high, the soft-start function will generate an internal voltage ramp. This causes the start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start duration is typically 5.5ms with 750kHz switching frequency. When the soft-start is completed, the error amplifier will be connected directly to the internal voltage reference. Enable Logic low on EN pin forces the PWM section into shutdown. In the shutdown mode all the major blocks of the PWM including power switches, drivers, voltage reference, and oscillator are turned off. Undervoltage Lockout Functional Description The ISL6410, ISL6410A is a synchronous buck regulator with integrated N- and P-channel power MOSFET and provides pre-set pin programmable outputs. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and reduced number of external components. Operating frequency FN9149 Rev 3.00 September 17, 2004 An undervoltage lockout circuit prevents the converter from turning on when the voltage on VIN is less than the values specified in the Input UVLO Threshold section of the electrical specification. Page 7 of 13 ISL6410, ISL6410A Power Good Input Capacitor Selection This output is asserted high when the PWM is enabled, and Vout is within 8.0% typical of its final value, and is active low outside this range. When disabled, the output turns active low. It is recommended to leave the PG pin unconnected when not used. The input current to the buck converter is pulsed, and therefore a low ESR input capacitor is required. This results in good input voltage filtering and minimizes the interference it causes to other circuits. The input capacitor should have a minimum value of 10F and a higher value can be selected for improving input voltage filtering. The input capacitor should be rated for the maximum input ripple current calculated as: PWM Overvoltage and Overcurrent Protection The PWM output current is sampled at the end of each PWM cycle, exceeding the overcurrent limit, causes a 4 bit up/down counter to increment by one LSB. A normal current state causes the counter to decrement by one LSB (the counter will not however “rollover” or count below 0000). When the PWM goes into overcurrent, the counter rapidly reaches count 1111 and the PWM output is shut down and the soft-start counter is reset. After 16 clocks the PWM output is enabled and the softstart cycle is started. If Vout exceeds the overvoltage limit for 32 consecutive clock cycles the PWM output is shut off and the soft-start cycle is initiated. No Load Operation If there is no load connected to the output, the converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time. Output Capacitor Selection For best performance, a low ESR output capacitor is needed. Output voltages below 1.8V require a larger output capacitor and ESR value to improve the performance and stability of the converter. For 1.8V output applications, a ceramic capacitor of 10µF or higher value with ESR 50m is recommended. The RMS ripple current is calculated as: Vo Vo I RMS = Io  max   ---------   1 – --------- Vin  Vin The worst case RMS ripple current occurs at D = 0.5 and is calculated as: Irms = Io/2. D = Duty Cycle Ceramic capacitors are preferred because of their low ESR value. They are also less sensitive to voltage transients when compared to tantalum capacitors. It is good practice to place the input capacitor as close as possible to the input pin of the IC for optimum performance. Inductor Selection The ISL6410 is an internally compensated device and hence a minimum of 8.2H must be used for the ISL6410 and a minimum of 12H for the ISL6410A. The selected inductor must have a low DC resistance and a saturation current greater than the maximum inductor current value can be calculated from the equations below Vo 1 – --------Vin -----------------dIL = Vo  Lf dIL IL max = Io max + --------2 Vo 1 – --------Vin 1 I RMS  Co  = Vo  -------------------  ----------------Lf 2 3 where dIL = the peak to peak inductor current L = the inductor value f = the switching frequency L = the inductor value f = the switching frequency The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR and the voltage ripple caused by charge and discharge of the output capacitor: Vo 1 – --------Vin 1 Vo = Vo  -------------------   ------------------------- + ESR  8  Co  f  Lf Where the highest output voltage ripple occurs at the highest input voltage VIN. ILmax = the max inductor current TABLE 3. RECOMMENDED INDUCTORS COMPONENT SUPPLIER INDUCTOR VALUE DCR (m 8.2H 75 Coilcraft MSS6122-822MX 12H 100 Coilcraft MSS6122-123MX TABLE 2. RECOMMENDED OUTPUT CAPACITORS CAPACITOR VALUE 10F ESR (m COMPONENT SUPPLIER