DATASHEET
ISL6551
FN9066
Rev 7.00
Oct 28, 2015
ZVS Full Bridge PWM Controller
The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM
controller designed for isolated power systems. This part
implements a unique control algorithm for fixed-frequency ZVS
current mode control, yielding high efficiency with low EMI. The
two lower drivers are PWM controlled on the trailing edge and
employ resonant delay while the two upper drivers are driven
at a fixed 50% duty cycle.
Features
This IC integrates many features in 28 Ld SOIC package to
yield a complete and sophisticated power supply solution.
Control features include programmable soft-start for
controlled start-up, programmable resonant delay for zero
voltage switching, programmable leading edge blanking to
prevent false triggering of the PWM comparator due to the
leading edge spike of the current ramp, adjustable ramp for
slope compensation, drive signals for implementing
synchronous rectification in high output current, ultra high
efficiency applications and current share support for
paralleling up to 10 units, which helps achieve higher reliability
and availability as well as better thermal management.
Protective features include adjustable cycle-by-cycle peak
current limiting for overcurrent protection, fast short-circuit
protection (in hiccup mode), a latching shutdown input to turn
off the IC completely on output overvoltage conditions or other
extreme and undesirable faults, a non-latching enable input to
accept an enable command when monitoring the input voltage
and thermal condition of a converter and VDD undervoltage
lockout with hysteresis. Additionally, the ISL6551 includes
high current high-side and low-side totem-pole drivers to avoid
additional external drivers for moderate gate capacitance (up
to 1.6nF at 1MHz) applications, an uncommitted high
bandwidth (10MHz) error amplifier for feedback loop
compensation, a precision bandgap reference with ±1.5%
(ISL6551AB) or ±1% (ISL6551IB) tolerance across
recommended operating conditions and a ±5% “in regulation”
monitor.
• 10MHz error amplifier bandwidth
In addition to the ISL6551, other external elements such as
transformers, pulse transformers, capacitors, inductors and
Schottky or synchronous rectifiers are required for a complete
power supply solution. A detailed 200W telecom power supply
reference design using the ISL6551 with companion Intersil
ICs, Supervisor and Monitor ISL6550, and Half-bridge Driver
HIP2100, is presented in application note AN1002.
• AN1002, 200W, 470kHz, Telecom Power Supply Using
ISL6551 Full-Bridge Controller and ISL6550 Supervisor and
Monitor.
• High speed PWM (up to 1MHz) for ZVS full bridge control
• Current mode control compatible
• High current high-side and low-side totem-pole drivers
• Adjustable resonant delay for ZVS
• Programmable soft-start
• Precision bandgap reference
• Latching shutdown input
• Non-latching enable input
• Adjustable leading edge blanking
• Adjustable dead time control
• Adjustable ramp for slope compensation
• Fast short-circuit protection (hiccup mode)
• Adjustable cycle-by-cycle peak current limiting
• Drive signals to implement synchronous rectification
• VDD undervoltage lockout
• Current share support
• ±5% “in regulation” indication
• Pb-free (RoHS compliant)
Applications
• Full-bridge and push-pull converters
• Power supplies for off-line and Telecom/Datacom
• Power supplies for high end microprocessors and servers
Related Literature
In addition, the ISL6551 can also be designed in push-pull
converters using all of the features except the two upper
drivers and adjustable resonant delay features.
FN9066 Rev 7.00
Oct 28, 2015
Page 1 of 27
ISL6551
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Drive Signals Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagram Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Shutdown Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Shutdown Timing Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block/Pin Functional Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Additional Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System Blocks Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Primary FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Main Transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supervisor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Primary FET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Full Bridge Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Simplified Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Small Outline Plastic Packages (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FN9066 Rev 7.00
Oct 28, 2015
Page 2 of 27
ISL6551
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6551IBZ
ISL6551IBZ
0 to +85
28 Ld SOIC
M28.3
ISL6551ABZ
(No longer available, recommended
replacement: ISL6551IBZ, ISL6551IBZ-T)
ISL6551ABZ
-40 to +105
28 Ld SOIC
M28.3
NOTES:
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6551. For more information on MSL, please see tech brief TB363.
Pin Configuration
ISL6551
28 LD (SOIC)
TOP VIEW
FN9066 Rev 7.00
Oct 28, 2015
VSS
1
28
VDD
CT
2
27
VDDP1
RD
3
26
VDDP2
R_RESDLY
4
25
PGND
R_RA
5
24
UPPER1
ISENSE
6
23
UPPER2
PKILIM
7
22
LOWER1
BGREF
8
21
LOWER2
R_LEB
9
20
SYNC1
CS_COMP 10
19
SYNC2
CSS 11
18
ON/OFF
EANI 12
17
DCOK
EAI 13
16
LATSD
EAO 14
15
SHARE
Page 3 of 27
ISL6551
Functional Pin Description
PIN #
PIN NAME
DESCRIPTION
1
VSS
Reference ground. All control circuits are referenced to this pin.
2
CT
Set the oscillator frequency, up to 1MHz.
3
RD
Adjust the clock dead time from 50ns to 1000ns.
4
R_RESDLY
Program the resonant delay from 50ns to 500ns.
5
R_RA
Adjust the ramp for slope compensation (from 50mV to 250mV).
6
ISENSE
The pin receives the current information via a current sense transformer or a power resistor.
7
PKILIM
Set the overcurrent limit with the bandgap reference as the trip threshold.
8
BGREF
Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.
9
R_LEB
Program the leading edge blanking from 50ns to 300ns.
10
CS_COMP
Set a low current sharing loop bandwidth with a capacitor.
11
CSS
Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.
12
EANI
Noninverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
13
EAI
Inverting input of error amp. It receives the feedback voltage.
14
EAO
Output of error amp. It is clamped by the voltage at the CSS pin (Vclamp).
15
SHARE
This pin is the SHARE BUS connecting with other unit(s) for current share operation.
16
LATSD
The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.
17
DCOK
Power-good indication with a ±5% window.
18
ON/OFF
This is an Enable pin that controls the states of all drive signals and the soft-start.
19, 20
SYNC2, SYNC1
These are the gate control signals for the output synchronous rectifiers.
21, 22
LOWER2, LOWER1
Both lower drivers are PWM controlled on the trailing edge.
UPPER2, UPPER1
Both upper drivers are driven at a fixed 50% duty cycle.
PGND
Power ground. High current return paths for both the upper and the lower drivers.
23, 24
25
26, 27
28
VDDP2, VDDP1
Power is delivered to both the upper and the lower drivers through these pins.
VDD
Power is delivered to all control circuits including SYNC1 and SYNC2 via this pin.
FN9066 Rev 7.00
Oct 28, 2015
Page 4 of 27
ISL6551
BANDGAP
REFERENCE
BGREF
11 CSS
16 LATSD
28 VDD
18 ON/OFF
Functional Block Diagram
SHUTDOWN
SHUTDOWN
LATCH
LATCH
UVLO
SOFT
SOFTSTART
START
8
PKILIM 7
SHUTDOWN
SHUTDOWN
27 VDDP1
UPPER1
DRIVER
24 UPPER1
R_LEB 9
R_RESDLY 4
RESODLY
UPPER2
DRIVER
LEB
ISENSE 6
R_RA 5
CT 2
RD 3
EAO 14
EAI 13
EANI 12
23 UPPER2
RAMP
ADJUST
26 VDDP2
CLOCK
GENERATOR
PWM
LOGIC
ERROR AMP
Figure 7
22 LOWER1
LOWER2
DRIVER
21 LOWER2
CURRENT
SHARE
DC OK
25 PGND
20 SYNC1
19 SYNC2
15 SHARE
VSS
10 CS_COMP
1
17 DCOK
CIRCUITS REFERENCED TO VSS
LOWER1
DRIVER
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FN9066 Rev 7.00
Oct 28, 2015
Page 5 of 27
ISL6551
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . . . . . . . . . -0.3 to 16V
Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Power Good Sink Current (IDCOK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . 3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOIC Package (Note 4) . . . . . . . . . . . . . . . .
55
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range
ISL6551IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
ISL6551AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . .10.8V to 13.2V
Supply Voltage Range, VDDP1 and VDDP2. . . . . . . . . . . . . . . . . . . . BGREF
B
ILIM_OUT
F
VDDOFF
PKILIM < BGREF
SOFT
START
DRIVER
ENABLE
SOFT-START
SHUTDOWN
FAULT
FAULT
OFF
OVER
CURRENT
LATCHED
OFF/ON
LATCH
RESET
UNDER VOLTAGE
LOCKOUT
FIGURE 3. SHUTDOWN TIMING DIAGRAMS
Shutdown Timing Descriptions
A (ON/OFF) - When the ON/OFF is pulled low, the soft-start
capacitor is discharged and all the drivers are disabled. When the
ON/OFF is released without a fault condition, a soft-start is
initiated.
B (OVERCURRENT) - If the output of the converter is over loaded,
i.e., the PKILIM is above the bandgap reference voltage (BGREF),
the soft-start capacitor is discharged very quickly and all the
drivers are turned off. Thereafter, the soft-start capacitor is
charged slowly and discharged quickly if the output is overloaded
again. The soft-start will remain in hiccup mode as long as the
overload conditions persist. Once the overload is removed, the
soft-start capacitor is charged up and the converter is then back
to normal operation.
FN9066 Rev 7.00
Oct 28, 2015
C (LATCHING SHUTDOWN) - The IC is latched off completely as the
LATSD pin is pulled high and the soft-start capacitor is reset.
D (ON/OFF) - The latch cannot be reset by the ON/OFF.
E (LATCH RESET) - The latch is reset by removing the VDD. The
soft-start capacitor starts to be charged after VDD increases
above the turn-on threshold VDDON.
F (VDD UVLO) - The IC is turned off when the VDD is below the
turn-off threshold VDDOFF. Hysteresis VDDHYS is incorporated in
the undervoltage lockout (UVLO) circuit.
Page 10 of 27
ISL6551
Block/Pin Functional
Descriptions
• Undervoltage Lockout (UVLO)
- UVLO establishes an orderly start-up and verifies that VDD
is above the turn-on threshold voltage (VDDON). All the
drivers are held low during the lockout. UVLO incorporates
hysteresis VDDHYS to prevent multiple startup/shutdowns
while powering up.
- UVLO limits are not applicable to VDDP1 and VDDP2.
Detailed descriptions of each individual block in the functional
block diagram on page 5 are included in this section.
Application information and design considerations for each pin
and/or each block are also included.
• Bandgap Reference (BGREF)
- The reference voltage VREF is generated by a precision
bandgap circuit.
- This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
- This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
• IC Bias Power (VDD, VDDP1, VDDP2)
- The IC is powered from a 12V ±10% supply.
- VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
- VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
- Heavy copper should be attached to these pins for a
better heat spreading.
• Clock Generator (CT, RD)
- This free-running oscillator is set by two external
components as shown in Figure 4. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD
and CT should be tied to the VSS pin on their other ends
as close as possible. The corresponding CT for a particular
frequency can be selected from Figure 5.
- The switching frequency (fsw) of the power train is half of
the clock frequency (Fclock), as shown in Equation 1.
• IC GNDs (VSS, PGND)
- VSS is the reference ground, the return of VDD, of all
control circuits and must be kept away from nodes with
switching noises. It should be connected to the PGND in
only one location as close to the IC as practical. For a
secondary side control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinout(s). For a primary side control system, it should be
connected to the net before the input capacitors, i.e., the
input return pinout(s).
- PGND is the power return, the high-current return path of
both VDDP1 and VDDP2. It should be connected to the
SOURCE pins of two lower power switches or the RETURNs
- of external drivers as close as possible with heavy copper
traces.
- Copper planes should be attached to both pins.
RD
Fclock
f sw = ------------------2
(EQ. 1)
SET CLOCK
DEAD TIME (DT)
RD
VDDI_CT
VMAX
+
OUT
CT
CT
CLK
S
I_CT
VMIN
- OUT
+
R
Q
Q
Q
Q
CLK
DT
DT
FIGURE 4. SIMPLIFIED CLOCK GENERATOR CIRCUIT
FN9066 Rev 7.00
Oct 28, 2015
Page 11 of 27
ISL6551
3,000
2
DEAD TIME (µs)
0°C
60°C
2,500
120°C
F (kHz)
2,000
1,500
1.6
1.2
0.8
0.4
1,000
0
0
500
0
20
40
60
80
100
120
140
160
RD (kΩ)
10
100
CT (pF)
1,000
RECOMMENDED RANGE
FIGURE 5. CT vs FREQUENCY
- Note that the capacitance of a scope probe (~12pF for
single ended) would induce a smaller frequency at the CT
pin. It can be easily seen at a higher frequency. An
accurate operating frequency can be measured at the
outputs of the bridge/synchronous drivers.
- The dead time is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or
is responding to load transients or input line dipping
conditions. This helps to prevent shoot through between
the upper FET and the lower FET that are located at the
same side of the bridge. The dead time can be estimated
using Equation 2:
M RD
DT = -------------------k
(ns)
FIGURE 6. RD vs DEAD TIME (VDD = 12V)
10,000
(EQ. 2)
WHERE M = 11.4(VDD = 12V), 11.1(VDD = 14V) and
12(VDD = 10V) and RD is in kΩ. This relationship is shown
in Figure 6.
• Error Amplifier (EAI, EANI, EAO)
- This amplifier compares the feedback signal received at
the EAI pin to a reference signal set at the EANI pin and
provides an error signal (EAO) to the PWM Logic. The
feedback loop compensation can be programmed via
these pins.
- Both EANI and EAO are clamped by the voltage (Vclamp)
set at the CSS pin, as shown in Figure 7. Note that the
diodes in the functional block diagram represent the
clamp function of the CSS in a simplified way.
• Soft-start (CSS)
- The voltage on an external capacitor charged by an
internal current source ISS is fed into a control pin on the
error amplifier. This causes the Error Amplifier to: 1) limit
the EAO to the soft-start voltage level; and 2) over ride the
reference signal at the EANI with the soft-start voltage,
when the EANI voltage is higher than the soft-start
voltage. Thus, both the output voltage and current of the
power supply can be controlled by the soft-start.
- The clamping voltage determines the cycle-by-cycle peak
current limiting of the power supply. It should be set above
the EANI and EAO voltages and can be programmed by an
external resistor as shown in Figure 7 using Equation 3.
Vclamp = Rcss Iss
400mV
VDD
CSS
+
-
(EQ. 3)
(V)
Figure 12
SSL
(TO
BLANKING
CIRCUIT)
EAI
(–)
Iss
EANI
(+)
RCSS
SHUTDOWN
ERROR AMP
EAO
FIGURE 7. SIMPLIFIED CLAMP/SOFT-START
FN9066 Rev 7.00
Oct 28, 2015
Page 12 of 27
ISL6551
- Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a referencebased clamp circuit as shown in Figure 8. To make the
Vclamp less dependent on the soft-start current (Iss), the
currents flowing through R1 and R2 should be scaled
much greater than Iss. The relationship of this circuit can
be found in Equation 4.
divider from the ISENSE pin. The resistor divider relationship
is defined in Equation 7.
- In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
ISENSE
RUP
PKILIM
RDOWN
VREF
R1
FIGURE 9. PEAK CURRENT LIMIT SET CIRCUIT
CSS
R DOWN
BGREF
---------------------------------------- = ----------------------------------------R DOWN + R UP
ISENSE max
FIGURE 8. REFERENCE-BASED CLAMP CIRCUIT
R2
R1 R2
Vclamp Iss --------------------- + Vref --------------------R1 + R2
R1 + R2
(EQ. 4)
- The soft-start rise time (Tss) can be calculated with
Equation 5. The rise time (Trise) of the output voltage is
approximated with Equation 6.
Vclamp Css
t ss = --------------------------------------Iss
EANI Css
t rise = -------------------------------Iss
(s)
(s)
(EQ. 5)
(EQ. 6)
• Drivers (Upper1, Upper2, Lower1, Lower2)
- The two upper drivers are driven at a fixed 50% duty cycle
and the two lower drivers are PWM controlled on the
trailing edge while the leading edge employs resonant delay.
They are biased by VDDP1 and VDDP2, respectively.
- Each driver is capable of driving capacitive loads up to CL at
1MHz clock frequency and higher loads at lower frequencies
on a layout with high effective thermal conductivity.
- The UVLO holds all the drivers low until the VDD has reached
the turn-on threshold VDDON.
- The upper drivers require assistance of external level-shifting
circuits such as Intersil’s HIP2100 or pulse transformers to
drive the upper power switches of a bridge converter.
• Peak Current Limit (PKILIM)
- When the voltage at PKILIM exceeds the BGREF voltage, the
gate pulses are terminated and held low until the next clock
cycle. The peak current limit circuit has a high-speed loop
with propagation delay IpkDel. Peak current shutdown
initiates a soft-start sequence.
- The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated
in a short-circuit condition. The limit can be set with a resistor
(EQ. 7)
• Latching Shutdown (LATSD)
- A high TTL level on LATSD latches the IC off. The IC goes into
a low power mode and is reset only after the power at the
VDD pin is removed completely. The ON/OFF cannot reset
the latch.
- This pin can be used to latch the power supply off on output
overvoltage or other undesired conditions.
• ON/OFF (ON/OFF)
- A high standard TTL input (safe also for VDD level) signals the
controller to turn on. A low TTL input turns off the controller
and terminates all drive signals including the SYNC outputs.
The soft-start is reset.
- This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the
thermal condition of a converter.
• Resonant Delay (R_RESDLY)
- A resistor tied between R_RESDLY and VSS determines the
delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
(EQ. 8)
tRESDLY = 4.01 x R_RESDLY/k + 13 (ns)
- Figure 10 illustrates the relationship of the value of the
resistor (R_RESDLY) and the resonant delay (tRESDLY). The
percentages in the figure are the tolerances at the two end
points of the curve.
500
+18%
450
-24%
400
tRESDLY (ns)
R2
350
300
250
200
150
+37%
100
+4%
50
0
20
40
60
80
100
120
R_RESDLY (kΩ)
FIGURE 10. R_RESDLY vs RESDLY
FN9066 Rev 7.00
Oct 28, 2015
Page 13 of 27
ISL6551
• Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent false
triggering, the leading edge of the sensed current signal is
blanked out by a period that can be programmed with the
R_LEB resistor. Internal switches gate the analog input to the
PWM comparator, implementing the blanking function that
eliminates response degrading delays, which would be
caused if filtering of the current feedback was incorporated.
The current ramp is blanked out during the resonant delay
period because no switching occurs in the lower FETs. The
leading edge blanking function will not be activated until the
soft-start (CSS) reaches over 400mV, as illustrated in
Figures 7 and 12. The leading edge blanking (LEB) function
can be disabled by tying the R_LEB pin to VDD, i.e., LEB = 1.
Never leave the pin floating.
- The blanking time can be estimated with Equation 9, whose
relationship can be seen in Figure 11. The percentages in
the figure are the tolerances at the two endpoints of the
curve.
tLEB = 2 x R_LEB / kΩ + 15 (ns)
(EQ. 9)
300
+20%
-18%
250
tLEB (ns)
200
150
+51%
100
-11%
50
0
20
40
60
80
100
120
140
R_LEB (KΩ)
FIGURE 11. R_LEB vs tLEB
0.1µ
VDD
ADJ_RAMP
ADJ_RAMP
399k
200mV
RAMP_OUT
(TO PWM
COMPARATOR)
BGREF
R_RA
ISENSE
0
RAMP_OUT
200mV
R_RA
BLANK
ADD RAMP
+
ISENSE
200mV
R_LEB
R_LEB
SET
BLANKING
TIME
RESDLY
LEB
SSL
See Figure 7
-
RESDLY
LEB
SSL
RAMP_OUT
0
X
X
BLANK
X
0
0
BLANK
1
1
X
NO BLANK
1
X
1
NO BLANK
FIGURE 12. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
FN9066 Rev 7.00
Oct 28, 2015
Page 14 of 27
ISL6551
• Ramp Adjust (R_RA, ISENSE)
- The ramp adjust block adds an offset component
(200mV) and a slope adjust component to the ISENSE
signal before processing it at the PWM Logic block, as
shown in Figure 12. This ensures that the ramp voltage is
always higher than the OAGS (ground sensing opamp)
minimum voltage to achieve a “zero” state.
- It is critical that the input signal to ISENSE decays to zero
prior to or during the clock dead time. The level-shifting
and capacitive summing circuits in the RAMP ADJUST
block are reset during the dead time. Any input signal
transitions that occur after the rising edge of CLK and
prior to the rising edge of RESDLY can cause severe errors
in the signal reaching the PWM comparator.
- Typical ramp values are hundreds of mV over the period
on a 3V full scale current. Too much ramp makes the
controller look like a voltage mode PWM and too little
ramp leads to noise issues (jitter). The amount of ramp
(Vramp), as shown in Figure 12, is programmed with the
R_RA resistor and can be calculated with Equation 10.
Vramp = BGREF x dt /(R_RA x 500E-12) (V)
synchronous rectifiers. When using these drive schemes,
the user should understand the issues that might occur in
his/her applications, especially the impacts on current
share operation and light load operation. Refer to
application note AN1002 for more details.
- External high current drivers controlled by the
synchronous signals are required to drive the synchronous
rectifiers. A pulse transformer is required to pass the drive
signals to the secondary side if the IC is used in a primary
control system.
• Share Support (SHARE, CS_COMP)
- The unit with the highest reference is the master. Other
units, as slaves, adjust their references via a source
resistor to match the master reference sharing the load
current. The source resistor is typically 1kΩ connecting
the EANI pin and the OUTPUT REFERENCE (external
reference or BGREF), as shown in Figure 13. The share
bus represents a 30kΩ resistive load per unit, up to 10
units.
- The output (ADJ) of “Operational Transconductance
Amplifier (OTA)” can only pull high and it is floating while
in master mode. This ensures that no current is sourced to
the OUTPUT REFERENCE when the IC is working by itself.
- The slave units attempt to drive their error amplifier
voltage to be within a predetermined offset (30mV
typical) of the master error voltage (the share bus). The
current-share error is nominally (30mV/EAO)*100%
assuming no other source of error. With a 2.5V full load
error amp voltage, the current-share error at full load
would be -1.2% (slaves relative to master).
- The bandwidth of the current sharing loop should be
much lower than that of the voltage loop to eliminate
noise pickup and interactions between the voltage
regulation loop and the current loop. A 0.1µF capacitor is
recommended between CS_COMP and VSS pins to
achieve a low current sharing loop bandwidth (100Hz to
500Hz).
(EQ. 10)
Where dt = Duty Cycle / fSW - tLEB (s). Duty cycle is
discussed in detail in application note AN1002.
- The voltage representation of the current flowing
through the power train at ISENSE pin is normally scaled
such that the desired peak current is less than or equal
to Vclamp-200mV-Vramp, where the clamping voltage is
set at the CSS pin.
• SYNC Outputs (SYNC1, SYNC2)
- SYNC1 and SYNC2 are the gate control signals for the
output synchronous rectifiers. They are biased by VDD and
are capable of driving capacitive loads up to 20pF at
1MHz clock frequency (500kHz switching frequency).
These outputs are turned off sooner than the turn-off at
UPPER1 and UPPER2 by the clock dead time, DT.
- Inverting both SYNC signals or both LOWER signals is
another possible way to control the drivers of the
CS_COMP
0.1µF
30mV
+
-
+
-
EAO
+
OTA
1k
ADJ
EANI
(+)
OUTPUT
REFERENCE
SHARE
30k
FIGURE 13. SIMPLIFIED CURRENT SHARE CIRCUIT
FN9066 Rev 7.00
Oct 28, 2015
Page 15 of 27
ISL6551
• Power-good (DCOK)
- DCOK pin is an open-drain output capable of sinking 5mA.
It is low when the output voltage is within the UVOV
window. The static regulation limit is ±3%, while the ±5%
is the dynamic regulation limit. It indicates power-good
when the EAI is within -3% to +5% on the rising edge and
within +3% to -5%on the falling edge, as shown in
Figure 14.
18K
EAI
VOUT
1K
EANI
R
15N
C
+
EAO
1.10V
EAI
+5%
VOUT
1.00V
+3%
EANI
0.90V
-3%
1.05V
-5%
1.00V
EAI
0.95V
FIGURE 15. OUTPUT TRANSIENT REJECTION
DCOK
FAULT
FIGURE 14. UNDERVOLTAGE-OVERVOLTAGE WINDOW
- The DCOK comparator might not be triggered even though
the output voltage exceeds ±5% limits at load transients.
This is because the feedback network of the error amplifier
filters out part of the transients and the EAI only sees the
remaining portion that is still within the limits, as illustrated
in Figure 15. The lower the “zero (1/RC)” of the error
amplifier, the larger the portion of the transient is filtered
out.
FN9066 Rev 7.00
Oct 28, 2015
Page 16 of 27
ISL6551
Additional Applications
Information
operation of the ISL6551, see Block/Pin Functional
Descriptions.
Table 1 highlights parameter setting for the ISL6551.
Designers can use this table as a design checklist. For detailed
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST
PARAMETER
PIN NAME
FORMULA OR SETTING HIGHLIGHT
UNIT
FIGURE #
kHz
1, 5
Frequency
CT
Set 50% Duty Cycle Pulses with a fixed frequency
Dead Time
RD
DT = M x RD/kΩ , where M = 11.4
ns
6
tRESDLY = 4.01 x R_RESDLY/kΩ + 13
ns
10
Vramp = BGREF/(R_RA x 500E-12) x dt
V
-
Resonant Delay
R_RESDLY
Ramp Adjust
R_RA
Current Sense
ISENSE
